Classes
struct	ns_desc32

struct	ns_desc64

Enumerations
enum	DeviceRegisterAddress { CR = 0x00, CFGR = 0x04, MEAR = 0x08, PTSCR = 0x0c, ISR = 0x10, IMR = 0x14, IER = 0x18, IHR = 0x1c, TXDP = 0x20, TXDP_HI = 0x24, TX_CFG = 0x28, GPIOR = 0x2c, RXDP = 0x30, RXDP_HI = 0x34, RX_CFG = 0x38, PQCR = 0x3c, WCSR = 0x40, PCR = 0x44, RFCR = 0x48, RFDR = 0x4c, BRAR = 0x50, BRDR = 0x54, SRR = 0x58, MIBC = 0x5c, MIB_START = 0x60, MIB_END = 0x88, VRCR = 0xbc, VTCR = 0xc0, VDR = 0xc4, CCSR = 0xcc, TBICR = 0xe0, TBISR = 0xe4, TANAR = 0xe8, TANLPAR = 0xec, TANER = 0xf0, TESR = 0xf4, M5REG = 0xf8, LAST = 0xf8, RESERVED = 0xfc }

enum	ChipCommandRegister { CR_TXE = 0x00000001, CR_TXD = 0x00000002, CR_RXE = 0x00000004, CR_RXD = 0x00000008, CR_TXR = 0x00000010, CR_RXR = 0x00000020, CR_SWI = 0x00000080, CR_RST = 0x00000100 }

enum	ConfigurationRegisters { CFGR_ZERO = 0x00000000, CFGR_LNKSTS = 0x80000000, CFGR_SPDSTS = 0x60000000, CFGR_SPDSTS1 = 0x40000000, CFGR_SPDSTS0 = 0x20000000, CFGR_DUPSTS = 0x10000000, CFGR_TBI_EN = 0x01000000, CFGR_RESERVED = 0x0e000000, CFGR_MODE_1000 = 0x00400000, CFGR_AUTO_1000 = 0x00200000, CFGR_PINT_CTL = 0x001c0000, CFGR_PINT_DUPSTS = 0x00100000, CFGR_PINT_LNKSTS = 0x00080000, CFGR_PINT_SPDSTS = 0x00040000, CFGR_TMRTEST = 0x00020000, CFGR_MRM_DIS = 0x00010000, CFGR_MWI_DIS = 0x00008000, CFGR_T64ADDR = 0x00004000, CFGR_PCI64_DET = 0x00002000, CFGR_DATA64_EN = 0x00001000, CFGR_M64ADDR = 0x00000800, CFGR_PHY_RST = 0x00000400, CFGR_PHY_DIS = 0x00000200, CFGR_EXTSTS_EN = 0x00000100, CFGR_REQALG = 0x00000080, CFGR_SB = 0x00000040, CFGR_POW = 0x00000020, CFGR_EXD = 0x00000010, CFGR_PESEL = 0x00000008, CFGR_BROM_DIS = 0x00000004, CFGR_EXT_125 = 0x00000002, CFGR_BEM = 0x00000001 }

enum	EEPROMAccessRegister { MEAR_EEDI = 0x00000001, MEAR_EEDO = 0x00000002, MEAR_EECLK = 0x00000004, MEAR_EESEL = 0x00000008, MEAR_MDIO = 0x00000010, MEAR_MDDIR = 0x00000020, MEAR_MDC = 0x00000040 }

enum	PCITestControlRegister { PTSCR_EEBIST_FAIL = 0x00000001, PTSCR_EEBIST_EN = 0x00000002, PTSCR_EELOAD_EN = 0x00000004, PTSCR_RBIST_FAIL = 0x000001b8, PTSCR_RBIST_DONE = 0x00000200, PTSCR_RBIST_EN = 0x00000400, PTSCR_RBIST_RST = 0x00002000, PTSCR_RBIST_RDONLY = 0x000003f9 }

enum	InterruptStatusRegister { ISR_RESERVE = 0x80000000, ISR_TXDESC3 = 0x40000000, ISR_TXDESC2 = 0x20000000, ISR_TXDESC1 = 0x10000000, ISR_TXDESC0 = 0x08000000, ISR_RXDESC3 = 0x04000000, ISR_RXDESC2 = 0x02000000, ISR_RXDESC1 = 0x01000000, ISR_RXDESC0 = 0x00800000, ISR_TXRCMP = 0x00400000, ISR_RXRCMP = 0x00200000, ISR_DPERR = 0x00100000, ISR_SSERR = 0x00080000, ISR_RMABT = 0x00040000, ISR_RTAB = 0x00020000, ISR_RXSOVR = 0x00010000, ISR_HIBINT = 0x00008000, ISR_PHY = 0x00004000, ISR_PME = 0x00002000, ISR_SWI = 0x00001000, ISR_MIB = 0x00000800, ISR_TXURN = 0x00000400, ISR_TXIDLE = 0x00000200, ISR_TXERR = 0x00000100, ISR_TXDESC = 0x00000080, ISR_TXOK = 0x00000040, ISR_RXORN = 0x00000020, ISR_RXIDLE = 0x00000010, ISR_RXEARLY = 0x00000008, ISR_RXERR = 0x00000004, ISR_RXDESC = 0x00000002, ISR_RXOK = 0x00000001, ISR_ALL = 0x7FFFFFFF, ISR_DELAY, ISR_NODELAY = (ISR_ALL & ~ISR_DELAY), ISR_IMPL, ISR_NOIMPL = (ISR_ALL & ~ISR_IMPL) }

enum	TransmitConfigurationRegister { TX_CFG_CSI = 0x80000000, TX_CFG_HBI = 0x40000000, TX_CFG_MLB = 0x20000000, TX_CFG_ATP = 0x10000000, TX_CFG_ECRETRY = 0x00800000, TX_CFG_BRST_DIS = 0x00080000, TX_CFG_MXDMA1024 = 0x00000000, TX_CFG_MXDMA512 = 0x00700000, TX_CFG_MXDMA256 = 0x00600000, TX_CFG_MXDMA128 = 0x00500000, TX_CFG_MXDMA64 = 0x00400000, TX_CFG_MXDMA32 = 0x00300000, TX_CFG_MXDMA16 = 0x00200000, TX_CFG_MXDMA8 = 0x00100000, TX_CFG_MXDMA = 0x00700000, TX_CFG_FLTH_MASK = 0x0000ff00, TX_CFG_DRTH_MASK = 0x000000ff }

enum	GeneralPurposeIOControlRegister { GPIOR_UNUSED = 0xffff8000, GPIOR_GP5_IN = 0x00004000, GPIOR_GP4_IN = 0x00002000, GPIOR_GP3_IN = 0x00001000, GPIOR_GP2_IN = 0x00000800, GPIOR_GP1_IN = 0x00000400, GPIOR_GP5_OE = 0x00000200, GPIOR_GP4_OE = 0x00000100, GPIOR_GP3_OE = 0x00000080, GPIOR_GP2_OE = 0x00000040, GPIOR_GP1_OE = 0x00000020, GPIOR_GP5_OUT = 0x00000010, GPIOR_GP4_OUT = 0x00000008, GPIOR_GP3_OUT = 0x00000004, GPIOR_GP2_OUT = 0x00000002, GPIOR_GP1_OUT = 0x00000001 }

enum	ReceiveConfigurationRegister { RX_CFG_AEP = 0x80000000, RX_CFG_ARP = 0x40000000, RX_CFG_STRIPCRC = 0x20000000, RX_CFG_RX_FD = 0x10000000, RX_CFG_ALP = 0x08000000, RX_CFG_AIRL = 0x04000000, RX_CFG_MXDMA512 = 0x00700000, RX_CFG_MXDMA = 0x00700000, RX_CFG_DRTH = 0x0000003e, RX_CFG_DRTH0 = 0x00000002 }

enum	PauseControlStatusRegister { PCR_PSEN = (1 << 31), PCR_PS_MCAST = (1 << 30), PCR_PS_DA = (1 << 29), PCR_STHI_8 = (3 << 23), PCR_STLO_4 = (1 << 23), PCR_FFHI_8K = (3 << 21), PCR_FFLO_4K = (1 << 21), PCR_PAUSE_CNT = 0xFFFE }

enum	ReceiveFilterMatchControlRegister { RFCR_RFEN = 0x80000000, RFCR_AAB = 0x40000000, RFCR_AAM = 0x20000000, RFCR_AAU = 0x10000000, RFCR_APM = 0x08000000, RFCR_APAT = 0x07800000, RFCR_APAT3 = 0x04000000, RFCR_APAT2 = 0x02000000, RFCR_APAT1 = 0x01000000, RFCR_APAT0 = 0x00800000, RFCR_AARP = 0x00400000, RFCR_MHEN = 0x00200000, RFCR_UHEN = 0x00100000, RFCR_ULM = 0x00080000, RFCR_RFADDR = 0x000003ff }

enum	ReceiveFilterMatchDataRegister { RFDR_BMASK = 0x00030000, RFDR_RFDATA0 = 0x000000ff, RFDR_RFDATA1 = 0x0000ff00 }

enum	ManagementInformationBaseControlRegister { MIBC_MIBS = 0x00000008, MIBC_ACLR = 0x00000004, MIBC_FRZ = 0x00000002, MIBC_WRN = 0x00000001 }

enum	VLANIPReceiveControlRegister { VRCR_RUDPE = 0x00000080, VRCR_RTCPE = 0x00000040, VRCR_RIPE = 0x00000020, VRCR_IPEN = 0x00000010, VRCR_DUTF = 0x00000008, VRCR_DVTF = 0x00000004, VRCR_VTREN = 0x00000002, VRCR_VTDEN = 0x00000001 }

enum	VLANIPTransmitControlRegister { VTCR_PPCHK = 0x00000008, VTCR_GCHK = 0x00000004, VTCR_VPPTI = 0x00000002, VTCR_VGTI = 0x00000001 }

enum	ClockrunControlStatusRegister { CCSR_CLKRUN_EN = 0x00000001 }

enum	TBIControlRegister { TBICR_MR_LOOPBACK = 0x00004000, TBICR_MR_AN_ENABLE = 0x00001000, TBICR_MR_RESTART_AN = 0x00000200 }

enum	TBIStatusRegister { TBISR_MR_LINK_STATUS = 0x00000020, TBISR_MR_AN_COMPLETE = 0x00000004 }

enum	TBIAutoNegotiationAdvertisementRegister { TANAR_NP = 0x00008000, TANAR_RF2 = 0x00002000, TANAR_RF1 = 0x00001000, TANAR_PS2 = 0x00000100, TANAR_PS1 = 0x00000080, TANAR_HALF_DUP = 0x00000040, TANAR_FULL_DUP = 0x00000020, TANAR_UNUSED = 0x00000E1F }

enum	M5ControlRegister { M5REG_RESERVED = 0xfffffffc, M5REG_RSS = 0x00000004, M5REG_RX_THREAD = 0x00000002, M5REG_TX_THREAD = 0x00000001 }

enum	CMDSTSFlatsForDescriptors { CMDSTS_OWN = 0x80000000, CMDSTS_MORE = 0x40000000, CMDSTS_INTR = 0x20000000, CMDSTS_ERR = 0x10000000, CMDSTS_OK = 0x08000000, CMDSTS_LEN_MASK = 0x0000ffff, CMDSTS_DEST_MASK = 0x01800000, CMDSTS_DEST_SELF = 0x00800000, CMDSTS_DEST_MULTI = 0x01000000 }

enum	ExtendedFlagsForDescriptors { EXTSTS_UDPERR = 0x00400000, EXTSTS_UDPPKT = 0x00200000, EXTSTS_TCPERR = 0x00100000, EXTSTS_TCPPKT = 0x00080000, EXTSTS_IPERR = 0x00040000, EXTSTS_IPPKT = 0x00020000 }

Functions
static int	SPDSTS_POLARITY (int lnksts)

Detailed Description

Ethernet device register definitions for the National Semiconductor DP83820 Ethernet controller

Definition in file ns_gige_reg.h.

Enumeration Type Documentation

◆ ChipCommandRegister

enum ChipCommandRegister

Enumerator
CR_TXE
CR_TXD
CR_RXE
CR_RXD
CR_TXR
CR_RXR
CR_SWI
CR_RST

Definition at line 81 of file ns_gige_reg.h.

◆ ClockrunControlStatusRegister

enum ClockrunControlStatusRegister

Enumerator
CCSR_CLKRUN_EN

Definition at line 317 of file ns_gige_reg.h.

◆ CMDSTSFlatsForDescriptors

enum CMDSTSFlatsForDescriptors

Enumerator
CMDSTS_OWN
CMDSTS_MORE
CMDSTS_INTR
CMDSTS_ERR
CMDSTS_OK
CMDSTS_LEN_MASK
CMDSTS_DEST_MASK
CMDSTS_DEST_SELF
CMDSTS_DEST_MULTI

Definition at line 369 of file ns_gige_reg.h.

◆ ConfigurationRegisters

enum ConfigurationRegisters

Enumerator
CFGR_ZERO
CFGR_LNKSTS
CFGR_SPDSTS
CFGR_SPDSTS1
CFGR_SPDSTS0
CFGR_DUPSTS
CFGR_TBI_EN
CFGR_RESERVED
CFGR_MODE_1000
CFGR_AUTO_1000
CFGR_PINT_CTL
CFGR_PINT_DUPSTS
CFGR_PINT_LNKSTS
CFGR_PINT_SPDSTS
CFGR_TMRTEST
CFGR_MRM_DIS
CFGR_MWI_DIS
CFGR_T64ADDR
CFGR_PCI64_DET
CFGR_DATA64_EN
CFGR_M64ADDR
CFGR_PHY_RST
CFGR_PHY_DIS
CFGR_EXTSTS_EN
CFGR_REQALG
CFGR_SB
CFGR_POW
CFGR_EXD
CFGR_PESEL
CFGR_BROM_DIS
CFGR_EXT_125
CFGR_BEM

Definition at line 93 of file ns_gige_reg.h.

◆ DeviceRegisterAddress

enum DeviceRegisterAddress

Enumerator
CR
CFGR
MEAR
PTSCR
ISR
IMR
IER
IHR
TXDP
TXDP_HI
TX_CFG
GPIOR
RXDP
RXDP_HI
RX_CFG
PQCR
WCSR
PCR
RFCR
RFDR
BRAR
BRDR
SRR
MIBC
MIB_START
MIB_END
VRCR
VTCR
VDR
CCSR
TBICR
TBISR
TANAR
TANLPAR
TANER
TESR
M5REG
LAST
RESERVED

Definition at line 38 of file ns_gige_reg.h.

◆ EEPROMAccessRegister

enum EEPROMAccessRegister

Enumerator
MEAR_EEDI
MEAR_EEDO
MEAR_EECLK
MEAR_EESEL
MEAR_MDIO
MEAR_MDDIR
MEAR_MDC

Definition at line 129 of file ns_gige_reg.h.

◆ ExtendedFlagsForDescriptors

enum ExtendedFlagsForDescriptors

Enumerator
EXTSTS_UDPERR
EXTSTS_UDPPKT
EXTSTS_TCPERR
EXTSTS_TCPPKT
EXTSTS_IPERR
EXTSTS_IPPKT

Definition at line 383 of file ns_gige_reg.h.

◆ GeneralPurposeIOControlRegister

enum GeneralPurposeIOControlRegister

Enumerator
GPIOR_UNUSED
GPIOR_GP5_IN
GPIOR_GP4_IN
GPIOR_GP3_IN
GPIOR_GP2_IN
GPIOR_GP1_IN
GPIOR_GP5_OE
GPIOR_GP4_OE
GPIOR_GP3_OE
GPIOR_GP2_OE
GPIOR_GP1_OE
GPIOR_GP5_OUT
GPIOR_GP4_OUT
GPIOR_GP3_OUT
GPIOR_GP2_OUT
GPIOR_GP1_OUT

Definition at line 217 of file ns_gige_reg.h.

◆ InterruptStatusRegister

enum InterruptStatusRegister

Enumerator
ISR_RESERVE
ISR_TXDESC3
ISR_TXDESC2
ISR_TXDESC1
ISR_TXDESC0
ISR_RXDESC3
ISR_RXDESC2
ISR_RXDESC1
ISR_RXDESC0
ISR_TXRCMP
ISR_RXRCMP
ISR_DPERR
ISR_SSERR
ISR_RMABT
ISR_RTAB
ISR_RXSOVR
ISR_HIBINT
ISR_PHY
ISR_PME
ISR_SWI
ISR_MIB
ISR_TXURN
ISR_TXIDLE
ISR_TXERR
ISR_TXDESC
ISR_TXOK
ISR_RXORN
ISR_RXIDLE
ISR_RXEARLY
ISR_RXERR
ISR_RXDESC
ISR_RXOK
ISR_ALL
ISR_DELAY
ISR_NODELAY
ISR_IMPL
ISR_NOIMPL

Definition at line 152 of file ns_gige_reg.h.

◆ M5ControlRegister

enum M5ControlRegister

Enumerator
M5REG_RESERVED
M5REG_RSS
M5REG_RX_THREAD
M5REG_TX_THREAD

Definition at line 347 of file ns_gige_reg.h.

◆ ManagementInformationBaseControlRegister

enum ManagementInformationBaseControlRegister

Enumerator
MIBC_MIBS
MIBC_ACLR
MIBC_FRZ
MIBC_WRN

Definition at line 289 of file ns_gige_reg.h.

◆ PauseControlStatusRegister

enum PauseControlStatusRegister

Enumerator
PCR_PSEN
PCR_PS_MCAST
PCR_PS_DA
PCR_STHI_8
PCR_STLO_4
PCR_FFHI_8K
PCR_FFLO_4K
PCR_PAUSE_CNT

Definition at line 251 of file ns_gige_reg.h.

◆ PCITestControlRegister

enum PCITestControlRegister

Enumerator
PTSCR_EEBIST_FAIL
PTSCR_EEBIST_EN
PTSCR_EELOAD_EN
PTSCR_RBIST_FAIL
PTSCR_RBIST_DONE
PTSCR_RBIST_EN
PTSCR_RBIST_RST
PTSCR_RBIST_RDONLY

Definition at line 140 of file ns_gige_reg.h.

◆ ReceiveConfigurationRegister

enum ReceiveConfigurationRegister

Enumerator
RX_CFG_AEP
RX_CFG_ARP
RX_CFG_STRIPCRC
RX_CFG_RX_FD
RX_CFG_ALP
RX_CFG_AIRL
RX_CFG_MXDMA512
RX_CFG_MXDMA
RX_CFG_DRTH
RX_CFG_DRTH0

Definition at line 237 of file ns_gige_reg.h.

◆ ReceiveFilterMatchControlRegister

enum ReceiveFilterMatchControlRegister

Enumerator
RFCR_RFEN
RFCR_AAB
RFCR_AAM
RFCR_AAU
RFCR_APM
RFCR_APAT
RFCR_APAT3
RFCR_APAT2
RFCR_APAT1
RFCR_APAT0
RFCR_AARP
RFCR_MHEN
RFCR_UHEN
RFCR_ULM
RFCR_RFADDR

Definition at line 263 of file ns_gige_reg.h.

◆ ReceiveFilterMatchDataRegister

enum ReceiveFilterMatchDataRegister

Enumerator
RFDR_BMASK
RFDR_RFDATA0
RFDR_RFDATA1

Definition at line 282 of file ns_gige_reg.h.

◆ TBIAutoNegotiationAdvertisementRegister

enum TBIAutoNegotiationAdvertisementRegister

Enumerator
TANAR_NP
TANAR_RF2
TANAR_RF1
TANAR_PS2
TANAR_PS1
TANAR_HALF_DUP
TANAR_FULL_DUP
TANAR_UNUSED

Definition at line 335 of file ns_gige_reg.h.

◆ TBIControlRegister

enum TBIControlRegister

Enumerator
TBICR_MR_LOOPBACK
TBICR_MR_AN_ENABLE
TBICR_MR_RESTART_AN

Definition at line 322 of file ns_gige_reg.h.

◆ TBIStatusRegister

enum TBIStatusRegister

Enumerator
TBISR_MR_LINK_STATUS
TBISR_MR_AN_COMPLETE

Definition at line 329 of file ns_gige_reg.h.

◆ TransmitConfigurationRegister

enum TransmitConfigurationRegister

Enumerator
TX_CFG_CSI
TX_CFG_HBI
TX_CFG_MLB
TX_CFG_ATP
TX_CFG_ECRETRY
TX_CFG_BRST_DIS
TX_CFG_MXDMA1024
TX_CFG_MXDMA512
TX_CFG_MXDMA256
TX_CFG_MXDMA128
TX_CFG_MXDMA64
TX_CFG_MXDMA32
TX_CFG_MXDMA16
TX_CFG_MXDMA8
TX_CFG_MXDMA
TX_CFG_FLTH_MASK
TX_CFG_DRTH_MASK

Definition at line 195 of file ns_gige_reg.h.

◆ VLANIPReceiveControlRegister

enum VLANIPReceiveControlRegister

Enumerator
VRCR_RUDPE
VRCR_RTCPE
VRCR_RIPE
VRCR_IPEN
VRCR_DUTF
VRCR_DVTF
VRCR_VTREN
VRCR_VTDEN

Definition at line 297 of file ns_gige_reg.h.

◆ VLANIPTransmitControlRegister

enum VLANIPTransmitControlRegister

Enumerator
VTCR_PPCHK
VTCR_GCHK
VTCR_VPPTI
VTCR_VGTI

Definition at line 309 of file ns_gige_reg.h.

Function Documentation

◆ SPDSTS_POLARITY()

static int SPDSTS_POLARITY ( int lnksts )

inlinestatic

Definition at line 394 of file ns_gige_reg.h.

References CFGR_DUPSTS, CFGR_LNKSTS, CFGR_SPDSTS0, CFGR_SPDSTS1, and CFGR_ZERO.

Classes

Enumerations

Functions