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41 #ifndef __CPU_O3_DECODE_HH__
42 #define __CPU_O3_DECODE_HH__
49 struct DerivO3CPUParams;
63 typedef typename Impl::O3CPU
O3CPU;
65 typedef typename Impl::CPUPol
CPUPol;
110 std::string
name()
const;
238 std::queue<DynInstPtr>
insts[Impl::MaxThreads];
323 #endif // __CPU_O3_DECODE_HH__
void squash(const DynInstPtr &inst, ThreadID tid)
Squashes if there is a PC-relative branch that was predicted incorrectly.
Stats::Scalar squashCycles
Stat for total number of squashing cycles.
Addr bdelayDoneSeqNum[Impl::MaxThreads]
SeqNum of Squashing Branch Delay Instruction (used for MIPS)
TimeBuffer< TimeStruct > * timeBuffer
Time buffer interface.
Cycles renameToDecodeDelay
Rename to decode delay.
bool checkStall(ThreadID tid) const
Checks all stall signals, and returns if any are true.
Stats::Scalar decodedInsts
Stat for total number of decoded instructions.
bool checkSignalsAndUpdate(ThreadID tid)
Checks all input signals and updates decode's status appropriately.
CPUPol::TimeStruct TimeStruct
int16_t ThreadID
Thread index/ID type.
std::queue< DynInstPtr > insts[Impl::MaxThreads]
Queue of all instructions coming from fetch this cycle.
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
ThreadStatus decodeStatus[Impl::MaxThreads]
Per-thread status.
Stats::Scalar runCycles
Stat for total number of normal running cycles.
Source of possible stalls.
Cycles iewToDecodeDelay
IEW to decode delay.
bool squashAfterDelaySlot[Impl::MaxThreads]
Tells when their is a pending delay slot inst.
TimeBuffer< TimeStruct >::wire fromRename
Wire to get rename's output from backwards time buffer.
Impl::DynInstPtr DynInstPtr
std::string name() const
Returns the name of decode.
void drainSanityCheck() const
Perform sanity checks after a drain.
CPUPol::FetchStruct FetchStruct
void takeOverFrom()
Takes over from another CPU's thread.
unsigned toRenameIndex
Index of instructions being sent to rename.
This is a simple scalar statistic, like a counter.
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets the main backwards communication time buffer pointer.
CPUPol::DecodeStruct DecodeStruct
Stats::Scalar unblockCycles
Stat for total number of unblocking cycles.
TimeBuffer< TimeStruct >::wire fromCommit
Wire to get commit's information from backwards time buffer.
void skidInsert(ThreadID tid)
Inserts a thread's instructions into the skid buffer, to be decoded once decode unblocks.
bool block(ThreadID tid)
Switches decode to blocking, and signals back that decode has become blocked.
Stats::Scalar blockedCycles
Stat for total number of blocked cycles.
Stats::Scalar controlMispred
Stat for number of times decode detected a non-control instruction incorrectly predicted as a branch.
std::list< ThreadID > * activeThreads
List of active thread ids.
std::queue< DynInstPtr > skidBuffer[Impl::MaxThreads]
Skid buffer between fetch and decode.
ThreadStatus
Individual thread status.
Stats::Scalar idleCycles
Stat for total number of idle cycles.
DecodeStatus
Overall decode stage status.
TimeBuffer< TimeStruct >::wire toFetch
Wire to write information heading to previous stages.
Stats::Scalar branchMispred
Stat for number of times a branch mispredict is detected.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
O3CPU * cpu
CPU interface.
Stalls stalls[Impl::MaxThreads]
Tracks which stages are telling decode to stall.
DecodeStatus _status
Decode status.
TimeBuffer< FetchStruct >::wire fromFetch
Wire to get fetch's output from fetch queue.
bool fetchInstsValid()
Returns if there any instructions from fetch on this cycle.
void clearStates(ThreadID tid)
Clear all thread-specific states.
TimeBuffer< DecodeStruct >::wire toRename
Wire used to write any information heading to rename.
void updateStatus()
Updates overall decode status based on all of the threads' statuses.
void sortInsts()
Separates instructions from fetch into individual lists of instructions sorted by thread.
void decodeInsts(ThreadID tid)
Processes instructions from fetch and passes them on to rename.
void tick()
Ticks decode, processing all input signals and decoding as many instructions as possible.
Stats::Scalar squashedInsts
Stat for total number of squashed instructions.
unsigned decodeWidth
The width of decode, in instructions.
DefaultDecode::DecodeStats stats
bool skidsEmpty()
Returns if all of the skid buffers are empty.
DefaultDecode class handles both single threaded and SMT decode.
TimeBuffer< DecodeStruct > * decodeQueue
Decode instruction queue.
bool wroteToTimeBuffer
Variable that tracks if decode has written to the time buffer this cycle.
TimeBuffer< FetchStruct > * fetchQueue
Fetch instruction queue interface.
DynInstPtr squashInst[Impl::MaxThreads]
Instruction used for squashing branch (used for MIPS)
Cycles is a wrapper class for representing cycle counts, i.e.
void setFetchQueue(TimeBuffer< FetchStruct > *fq_ptr)
Sets pointer to time buffer coming from fetch.
void setDecodeQueue(TimeBuffer< DecodeStruct > *dq_ptr)
Sets pointer to time buffer used to communicate to the next stage.
bool isDrained() const
Has the stage drained?
Stats::Scalar branchResolved
Stat for number of times a branch is resolved at decode.
void decode(bool &status_change, ThreadID tid)
Determines what to do based on decode's current status.
ThreadID numThreads
number of Active Threads
DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
DefaultDecode constructor.
bool unblock(ThreadID tid)
Switches decode to unblocking if the skid buffer is empty, and signals back that decode has unblocked...
unsigned skidBufferMax
Maximum size of the skid buffer.
Cycles commitToDecodeDelay
Commit to decode delay.
TimeBuffer< TimeStruct >::wire fromIEW
Wire to get iew's information from backwards time buffer.
Cycles fetchToDecodeDelay
Fetch to decode delay.
void readStallSignals(ThreadID tid)
Reads all stall signals from the backwards communication timebuffer.
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