#include <sys/types.h>
#include "base/bitfield.hh"
#include "base/bitunion.hh"

Classes
union	PCIConfig

struct	PMCAP

struct	MSICAP

union	MSIXCAP

union	MSIXTable

struct	MSIXPbaEntry

struct	PXCAP

Macros
#define	PCI_VENDOR_ID 0x00

#define	PCI_DEVICE_ID 0x02

#define	PCI_COMMAND 0x04

#define	PCI_STATUS 0x06

#define	PCI_REVISION_ID 0x08

#define	PCI_CLASS_CODE 0x09

#define	PCI_SUB_CLASS_CODE 0x0A

#define	PCI_BASE_CLASS_CODE 0x0B

#define	PCI_CACHE_LINE_SIZE 0x0C

#define	PCI_LATENCY_TIMER 0x0D

#define	PCI_HEADER_TYPE 0x0E

#define	PCI_BIST 0x0F

#define	PCI_CMD_BME 0x04

#define	PCI_CMD_MSE 0x02

#define	PCI_CMD_IOSE 0x01

#define	PCI0_BASE_ADDR0 0x10

#define	PCI0_BASE_ADDR1 0x14

#define	PCI0_BASE_ADDR2 0x18

#define	PCI0_BASE_ADDR3 0x1C

#define	PCI0_BASE_ADDR4 0x20

#define	PCI0_BASE_ADDR5 0x24

#define	PCI0_CIS 0x28

#define	PCI0_SUB_VENDOR_ID 0x2C

#define	PCI0_SUB_SYSTEM_ID 0x2E

#define	PCI0_ROM_BASE_ADDR 0x30

#define	PCI0_CAP_PTR 0x34

#define	PCI0_RESERVED 0x35

#define	PCI0_INTERRUPT_LINE 0x3C

#define	PCI0_INTERRUPT_PIN 0x3D

#define	PCI0_MINIMUM_GRANT 0x3E

#define	PCI0_MAXIMUM_LATENCY 0x3F

#define	PCI1_BASE_ADDR0 0x10

#define	PCI1_BASE_ADDR1 0x14

#define	PCI1_PRI_BUS_NUM 0x18

#define	PCI1_SEC_BUS_NUM 0x19

#define	PCI1_SUB_BUS_NUM 0x1A

#define	PCI1_SEC_LAT_TIMER 0x1B

#define	PCI1_IO_BASE 0x1C

#define	PCI1_IO_LIMIT 0x1D

#define	PCI1_SECONDARY_STATUS 0x1E

#define	PCI1_MEM_BASE 0x20

#define	PCI1_MEM_LIMIT 0x22

#define	PCI1_PRF_MEM_BASE 0x24

#define	PCI1_PRF_MEM_LIMIT 0x26

#define	PCI1_PRF_BASE_UPPER 0x28

#define	PCI1_PRF_LIMIT_UPPER 0x2C

#define	PCI1_IO_BASE_UPPER 0x30

#define	PCI1_IO_LIMIT_UPPER 0x32

#define	PCI1_RESERVED 0x34

#define	PCI1_ROM_BASE_ADDR 0x38

#define	PCI1_INTR_LINE 0x3C

#define	PCI1_INTR_PIN 0x3D

#define	PCI1_BRIDGE_CTRL 0x3E

#define	PCI_DEVICE_SPECIFIC 0x40

#define	PCI_CONFIG_SIZE 0xFF

#define	PCI_VENDOR_DEC 0x1011

#define	PCI_VENDOR_NCR 0x101A

#define	PCI_VENDOR_QLOGIC 0x1077

#define	PCI_VENDOR_SIMOS 0x1291

#define	PCI_PRODUCT_DEC_PZA 0x0008

#define	PCI_PRODUCT_NCR_810 0x0001

#define	PCI_PRODUCT_QLOGIC_ISP1020 0x1020

#define	PCI_PRODUCT_SIMOS_SIMOS 0x1291

#define	PCI_PRODUCT_SIMOS_ETHER 0x1292

#define	PMCAP_ID 0x00
	PCIe capability list offsets internal to the entry. More...

#define	PMCAP_PC 0x02

#define	PMCAP_PMCS 0x04

#define	PMCAP_SIZE 0x06

#define	MSICAP_ID 0x00

#define	MSICAP_MC 0x02

#define	MSICAP_MA 0x04

#define	MSICAP_MUA 0x08

#define	MSICAP_MD 0x0C

#define	MSICAP_MMASK 0x10

#define	MSICAP_MPEND 0x14

#define	MSICAP_SIZE 0x18

#define	MSIXCAP_ID 0x00

#define	MSIXCAP_MXC 0x02

#define	MSIXCAP_MTAB 0x04

#define	MSIXCAP_MPBA 0x08

#define	MSIXCAP_SIZE 0x0C

#define	PXCAP_ID 0x00

#define	PXCAP_PXCAP 0x02

#define	PXCAP_PXDCAP 0x04

#define	PXCAP_PXDC 0x08

#define	PXCAP_PXDS 0x0A

#define	PXCAP_PXLCAP 0x0C

#define	PXCAP_PXLC 0x10

#define	PXCAP_PXLS 0x12

#define	PXCAP_PXDCAP2 0x24

#define	PXCAP_PXDC2 0x28

#define	PXCAP_SIZE 0x30

#define	MSIXVECS_PER_PBA 64

Macro Definition Documentation

◆ MSICAP_ID

#define MSICAP_ID 0x00

Definition at line 174 of file pcireg.h.

◆ MSICAP_MA

#define MSICAP_MA 0x04

Definition at line 176 of file pcireg.h.

◆ MSICAP_MC

#define MSICAP_MC 0x02

Definition at line 175 of file pcireg.h.

◆ MSICAP_MD

#define MSICAP_MD 0x0C

Definition at line 178 of file pcireg.h.

◆ MSICAP_MMASK

#define MSICAP_MMASK 0x10

Definition at line 179 of file pcireg.h.

◆ MSICAP_MPEND

#define MSICAP_MPEND 0x14

Definition at line 180 of file pcireg.h.

◆ MSICAP_MUA

#define MSICAP_MUA 0x08

Definition at line 177 of file pcireg.h.

◆ MSICAP_SIZE

#define MSICAP_SIZE 0x18

Definition at line 181 of file pcireg.h.

◆ MSIXCAP_ID

#define MSIXCAP_ID 0x00

Definition at line 183 of file pcireg.h.

◆ MSIXCAP_MPBA

#define MSIXCAP_MPBA 0x08

Definition at line 186 of file pcireg.h.

◆ MSIXCAP_MTAB

#define MSIXCAP_MTAB 0x04

Definition at line 185 of file pcireg.h.

◆ MSIXCAP_MXC

#define MSIXCAP_MXC 0x02

Definition at line 184 of file pcireg.h.

◆ MSIXCAP_SIZE

#define MSIXCAP_SIZE 0x0C

Definition at line 187 of file pcireg.h.

◆ MSIXVECS_PER_PBA

#define MSIXVECS_PER_PBA 64

Definition at line 295 of file pcireg.h.

◆ PCI0_BASE_ADDR0

#define PCI0_BASE_ADDR0 0x10

Definition at line 106 of file pcireg.h.

◆ PCI0_BASE_ADDR1

#define PCI0_BASE_ADDR1 0x14

Definition at line 107 of file pcireg.h.

◆ PCI0_BASE_ADDR2

#define PCI0_BASE_ADDR2 0x18

Definition at line 108 of file pcireg.h.

◆ PCI0_BASE_ADDR3

#define PCI0_BASE_ADDR3 0x1C

Definition at line 109 of file pcireg.h.

◆ PCI0_BASE_ADDR4

#define PCI0_BASE_ADDR4 0x20

Definition at line 110 of file pcireg.h.

◆ PCI0_BASE_ADDR5

#define PCI0_BASE_ADDR5 0x24

Definition at line 111 of file pcireg.h.

◆ PCI0_CAP_PTR

#define PCI0_CAP_PTR 0x34

Definition at line 116 of file pcireg.h.

◆ PCI0_CIS

#define PCI0_CIS 0x28

Definition at line 112 of file pcireg.h.

◆ PCI0_INTERRUPT_LINE

#define PCI0_INTERRUPT_LINE 0x3C

Definition at line 118 of file pcireg.h.

◆ PCI0_INTERRUPT_PIN

#define PCI0_INTERRUPT_PIN 0x3D

Definition at line 119 of file pcireg.h.

◆ PCI0_MAXIMUM_LATENCY

#define PCI0_MAXIMUM_LATENCY 0x3F

Definition at line 121 of file pcireg.h.

◆ PCI0_MINIMUM_GRANT

#define PCI0_MINIMUM_GRANT 0x3E

Definition at line 120 of file pcireg.h.

◆ PCI0_RESERVED

#define PCI0_RESERVED 0x35

Definition at line 117 of file pcireg.h.

◆ PCI0_ROM_BASE_ADDR

#define PCI0_ROM_BASE_ADDR 0x30

Definition at line 115 of file pcireg.h.

◆ PCI0_SUB_SYSTEM_ID

#define PCI0_SUB_SYSTEM_ID 0x2E

Definition at line 114 of file pcireg.h.

◆ PCI0_SUB_VENDOR_ID

#define PCI0_SUB_VENDOR_ID 0x2C

Definition at line 113 of file pcireg.h.

◆ PCI1_BASE_ADDR0

#define PCI1_BASE_ADDR0 0x10

Definition at line 124 of file pcireg.h.

◆ PCI1_BASE_ADDR1

#define PCI1_BASE_ADDR1 0x14

Definition at line 125 of file pcireg.h.

◆ PCI1_BRIDGE_CTRL

#define PCI1_BRIDGE_CTRL 0x3E

Definition at line 145 of file pcireg.h.

◆ PCI1_INTR_LINE

#define PCI1_INTR_LINE 0x3C

Definition at line 143 of file pcireg.h.

◆ PCI1_INTR_PIN

#define PCI1_INTR_PIN 0x3D

Definition at line 144 of file pcireg.h.

◆ PCI1_IO_BASE

#define PCI1_IO_BASE 0x1C

Definition at line 130 of file pcireg.h.

◆ PCI1_IO_BASE_UPPER

#define PCI1_IO_BASE_UPPER 0x30

Definition at line 139 of file pcireg.h.

◆ PCI1_IO_LIMIT

#define PCI1_IO_LIMIT 0x1D

Definition at line 131 of file pcireg.h.

◆ PCI1_IO_LIMIT_UPPER

#define PCI1_IO_LIMIT_UPPER 0x32

Definition at line 140 of file pcireg.h.

◆ PCI1_MEM_BASE

#define PCI1_MEM_BASE 0x20

Definition at line 133 of file pcireg.h.

◆ PCI1_MEM_LIMIT

#define PCI1_MEM_LIMIT 0x22

Definition at line 134 of file pcireg.h.

◆ PCI1_PRF_BASE_UPPER

#define PCI1_PRF_BASE_UPPER 0x28

Definition at line 137 of file pcireg.h.

◆ PCI1_PRF_LIMIT_UPPER

#define PCI1_PRF_LIMIT_UPPER 0x2C

Definition at line 138 of file pcireg.h.

◆ PCI1_PRF_MEM_BASE

#define PCI1_PRF_MEM_BASE 0x24

Definition at line 135 of file pcireg.h.

◆ PCI1_PRF_MEM_LIMIT

#define PCI1_PRF_MEM_LIMIT 0x26

Definition at line 136 of file pcireg.h.

◆ PCI1_PRI_BUS_NUM

#define PCI1_PRI_BUS_NUM 0x18

Definition at line 126 of file pcireg.h.

◆ PCI1_RESERVED

#define PCI1_RESERVED 0x34

Definition at line 141 of file pcireg.h.

◆ PCI1_ROM_BASE_ADDR

#define PCI1_ROM_BASE_ADDR 0x38

Definition at line 142 of file pcireg.h.

◆ PCI1_SEC_BUS_NUM

#define PCI1_SEC_BUS_NUM 0x19

Definition at line 127 of file pcireg.h.

◆ PCI1_SEC_LAT_TIMER

#define PCI1_SEC_LAT_TIMER 0x1B

Definition at line 129 of file pcireg.h.

◆ PCI1_SECONDARY_STATUS

#define PCI1_SECONDARY_STATUS 0x1E

Definition at line 132 of file pcireg.h.

◆ PCI1_SUB_BUS_NUM

#define PCI1_SUB_BUS_NUM 0x1A

Definition at line 128 of file pcireg.h.

◆ PCI_BASE_CLASS_CODE

#define PCI_BASE_CLASS_CODE 0x0B

Definition at line 94 of file pcireg.h.

◆ PCI_BIST

#define PCI_BIST 0x0F

Definition at line 98 of file pcireg.h.

◆ PCI_CACHE_LINE_SIZE

#define PCI_CACHE_LINE_SIZE 0x0C

Definition at line 95 of file pcireg.h.

◆ PCI_CLASS_CODE

#define PCI_CLASS_CODE 0x09

Definition at line 92 of file pcireg.h.

◆ PCI_CMD_BME

#define PCI_CMD_BME 0x04

Definition at line 101 of file pcireg.h.

◆ PCI_CMD_IOSE

#define PCI_CMD_IOSE 0x01

Definition at line 103 of file pcireg.h.

◆ PCI_CMD_MSE

#define PCI_CMD_MSE 0x02

Definition at line 102 of file pcireg.h.

◆ PCI_COMMAND

#define PCI_COMMAND 0x04

Definition at line 89 of file pcireg.h.

◆ PCI_CONFIG_SIZE

#define PCI_CONFIG_SIZE 0xFF

Definition at line 149 of file pcireg.h.

◆ PCI_DEVICE_ID

#define PCI_DEVICE_ID 0x02

Definition at line 88 of file pcireg.h.

◆ PCI_DEVICE_SPECIFIC

#define PCI_DEVICE_SPECIFIC 0x40

Definition at line 148 of file pcireg.h.

◆ PCI_HEADER_TYPE

#define PCI_HEADER_TYPE 0x0E

Definition at line 97 of file pcireg.h.

◆ PCI_LATENCY_TIMER

#define PCI_LATENCY_TIMER 0x0D

Definition at line 96 of file pcireg.h.

◆ PCI_PRODUCT_DEC_PZA

#define PCI_PRODUCT_DEC_PZA 0x0008

Definition at line 158 of file pcireg.h.

◆ PCI_PRODUCT_NCR_810

#define PCI_PRODUCT_NCR_810 0x0001

Definition at line 159 of file pcireg.h.

◆ PCI_PRODUCT_QLOGIC_ISP1020

#define PCI_PRODUCT_QLOGIC_ISP1020 0x1020

Definition at line 160 of file pcireg.h.

◆ PCI_PRODUCT_SIMOS_ETHER

#define PCI_PRODUCT_SIMOS_ETHER 0x1292

Definition at line 162 of file pcireg.h.

◆ PCI_PRODUCT_SIMOS_SIMOS

#define PCI_PRODUCT_SIMOS_SIMOS 0x1291

Definition at line 161 of file pcireg.h.

◆ PCI_REVISION_ID

#define PCI_REVISION_ID 0x08

Definition at line 91 of file pcireg.h.

◆ PCI_STATUS

#define PCI_STATUS 0x06

Definition at line 90 of file pcireg.h.

◆ PCI_SUB_CLASS_CODE

#define PCI_SUB_CLASS_CODE 0x0A

Definition at line 93 of file pcireg.h.

◆ PCI_VENDOR_DEC

#define PCI_VENDOR_DEC 0x1011

Definition at line 152 of file pcireg.h.

◆ PCI_VENDOR_ID

#define PCI_VENDOR_ID 0x00

Definition at line 87 of file pcireg.h.

◆ PCI_VENDOR_NCR

#define PCI_VENDOR_NCR 0x101A

Definition at line 153 of file pcireg.h.

◆ PCI_VENDOR_QLOGIC

#define PCI_VENDOR_QLOGIC 0x1077

Definition at line 154 of file pcireg.h.

◆ PCI_VENDOR_SIMOS

#define PCI_VENDOR_SIMOS 0x1291

Definition at line 155 of file pcireg.h.

◆ PMCAP_ID

#define PMCAP_ID 0x00

PCIe capability list offsets internal to the entry.

Actual offsets in the PCI config space are defined in the python files setting up the system.

Definition at line 169 of file pcireg.h.

◆ PMCAP_PC

#define PMCAP_PC 0x02

Definition at line 170 of file pcireg.h.

◆ PMCAP_PMCS

#define PMCAP_PMCS 0x04

Definition at line 171 of file pcireg.h.

◆ PMCAP_SIZE

#define PMCAP_SIZE 0x06

Definition at line 172 of file pcireg.h.

◆ PXCAP_ID

#define PXCAP_ID 0x00

Definition at line 189 of file pcireg.h.

◆ PXCAP_PXCAP

#define PXCAP_PXCAP 0x02

Definition at line 190 of file pcireg.h.

◆ PXCAP_PXDC

#define PXCAP_PXDC 0x08

Definition at line 192 of file pcireg.h.

◆ PXCAP_PXDC2

#define PXCAP_PXDC2 0x28

Definition at line 198 of file pcireg.h.

◆ PXCAP_PXDCAP

#define PXCAP_PXDCAP 0x04

Definition at line 191 of file pcireg.h.

◆ PXCAP_PXDCAP2

#define PXCAP_PXDCAP2 0x24

Definition at line 197 of file pcireg.h.

◆ PXCAP_PXDS

#define PXCAP_PXDS 0x0A

Definition at line 193 of file pcireg.h.

◆ PXCAP_PXLC

#define PXCAP_PXLC 0x10

Definition at line 195 of file pcireg.h.

◆ PXCAP_PXLCAP

#define PXCAP_PXLCAP 0x0C

Definition at line 194 of file pcireg.h.

◆ PXCAP_PXLS

#define PXCAP_PXLS 0x12

Definition at line 196 of file pcireg.h.

◆ PXCAP_SIZE

#define PXCAP_SIZE 0x30

Definition at line 199 of file pcireg.h.

Classes

Macros