gem5
v20.1.0.0
systemc
tests
systemc
misc
unit
control
wait_until
rdy_gen.h
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/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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rdy_gen.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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/******************************************************************************/
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/*************************** RDY_GEN **********************/
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/******************************************************************************/
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SC_MODULE
( RDY_GEN )
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{
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SC_HAS_PROCESS
( RDY_GEN );
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sc_in_clk
clk;
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sc_signal<bool>& ready;
// Output
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RDY_GEN ( sc_module_name NAME,
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sc_clock& TICK_P,
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sc_signal<bool>& READY )
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:
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ready (READY)
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{
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clk (TICK_P);
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SC_CTHREAD
( entry, clk.pos() );
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}
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void
entry();
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};
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void
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RDY_GEN::entry()
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{
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ready.write(1);
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wait
();
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cout <<
sc_time_stamp
() <<
" : "
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<<
"WRITING ready = 1"
<< endl;
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ready.write(0);
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wait
();
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cout <<
sc_time_stamp
() <<
" : "
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<<
"WRITING ready = 0"
<< endl;
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ready.write(1);
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wait
();
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cout <<
sc_time_stamp
() <<
" : "
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<<
"WRITING ready = 1"
<< endl;
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}
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition:
sc_clock.hh:116
SC_MODULE
SC_MODULE(RDY_GEN)
Definition:
rdy_gen.h:42
sc_core::wait
void wait()
Definition:
sc_module.cc:653
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition:
sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition:
sc_module.hh:319
sc_core::sc_time_stamp
const sc_time & sc_time_stamp()
Definition:
sc_main.cc:128
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