gem5  v20.1.0.0
sinicreg.hh
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28 
29 #ifndef __DEV_NET_SINICREG_HH__
30 #define __DEV_NET_SINICREG_HH__
31 
32 #define __SINIC_REG32(NAME, VAL) static const uint32_t NAME = (VAL);
33 #define __SINIC_REG64(NAME, VAL) static const uint64_t NAME = (VAL);
34 
35 #define __SINIC_VAL32(NAME, OFFSET, WIDTH) \
36  static const uint32_t NAME##_width = WIDTH; \
37  static const uint32_t NAME##_offset = OFFSET; \
38  static const uint32_t NAME##_mask = (1 << WIDTH) - 1; \
39  static const uint32_t NAME = ((1 << WIDTH) - 1) << OFFSET; \
40  static inline uint32_t get_##NAME(uint32_t reg) \
41  { return (reg & NAME) >> OFFSET; } \
42  static inline uint32_t set_##NAME(uint32_t reg, uint32_t val) \
43  { return (reg & ~NAME) | ((val << OFFSET) & NAME); }
44 
45 #define __SINIC_VAL64(NAME, OFFSET, WIDTH) \
46  static const uint64_t NAME##_width = WIDTH; \
47  static const uint64_t NAME##_offset = OFFSET; \
48  static const uint64_t NAME##_mask = (ULL(1) << WIDTH) - 1; \
49  static const uint64_t NAME = ((ULL(1) << WIDTH) - 1) << OFFSET; \
50  static inline uint64_t get_##NAME(uint64_t reg) \
51  { return (reg & NAME) >> OFFSET; } \
52  static inline uint64_t set_##NAME(uint64_t reg, uint64_t val) \
53  { return (reg & ~NAME) | ((val << OFFSET) & NAME); }
54 
55 namespace Sinic {
56 namespace Regs {
57 
58 static const int VirtualShift = 8;
59 static const int VirtualMask = 0xff;
60 
61 // Registers
62 __SINIC_REG32(Config, 0x00) // 32: configuration register
63 __SINIC_REG32(Command, 0x04) // 32: command register
64 __SINIC_REG32(IntrStatus, 0x08) // 32: interrupt status
65 __SINIC_REG32(IntrMask, 0x0c) // 32: interrupt mask
66 __SINIC_REG32(RxMaxCopy, 0x10) // 32: max bytes per rx copy
67 __SINIC_REG32(TxMaxCopy, 0x14) // 32: max bytes per tx copy
68 __SINIC_REG32(ZeroCopySize, 0x18) // 32: bytes to copy if below threshold
69 __SINIC_REG32(ZeroCopyMark, 0x1c) // 32: only zero-copy above this threshold
70 __SINIC_REG32(VirtualCount, 0x20) // 32: number of virutal NICs
71 __SINIC_REG32(RxMaxIntr, 0x24) // 32: max receives per interrupt
72 __SINIC_REG32(RxFifoSize, 0x28) // 32: rx fifo capacity in bytes
73 __SINIC_REG32(TxFifoSize, 0x2c) // 32: tx fifo capacity in bytes
74 __SINIC_REG32(RxFifoLow, 0x30) // 32: rx fifo low watermark
75 __SINIC_REG32(TxFifoLow, 0x34) // 32: tx fifo low watermark
76 __SINIC_REG32(RxFifoHigh, 0x38) // 32: rx fifo high watermark
77 __SINIC_REG32(TxFifoHigh, 0x3c) // 32: tx fifo high watermark
78 __SINIC_REG32(RxData, 0x40) // 64: receive data
79 __SINIC_REG32(RxDone, 0x48) // 64: receive done
80 __SINIC_REG32(RxWait, 0x50) // 64: receive done (busy wait)
81 __SINIC_REG32(TxData, 0x58) // 64: transmit data
82 __SINIC_REG32(TxDone, 0x60) // 64: transmit done
83 __SINIC_REG32(TxWait, 0x68) // 64: transmit done (busy wait)
84 __SINIC_REG32(HwAddr, 0x70) // 64: mac address
85 __SINIC_REG32(RxStatus, 0x78)
86 __SINIC_REG32(Size, 0x80) // register addres space size
87 
88 // Config register bits
89 __SINIC_VAL32(Config_ZeroCopy, 12, 1) // enable zero copy
90 __SINIC_VAL32(Config_DelayCopy,11, 1) // enable delayed copy
91 __SINIC_VAL32(Config_RSS, 10, 1) // enable receive side scaling
92 __SINIC_VAL32(Config_RxThread, 9, 1) // enable receive threads
93 __SINIC_VAL32(Config_TxThread, 8, 1) // enable transmit thread
94 __SINIC_VAL32(Config_Filter, 7, 1) // enable receive filter
95 __SINIC_VAL32(Config_Vlan, 6, 1) // enable vlan tagging
96 __SINIC_VAL32(Config_Vaddr, 5, 1) // enable virtual addressing
97 __SINIC_VAL32(Config_Desc, 4, 1) // enable tx/rx descriptors
98 __SINIC_VAL32(Config_Poll, 3, 1) // enable polling
99 __SINIC_VAL32(Config_IntEn, 2, 1) // enable interrupts
100 __SINIC_VAL32(Config_TxEn, 1, 1) // enable transmit
101 __SINIC_VAL32(Config_RxEn, 0, 1) // enable receive
102 
103 // Command register bits
104 __SINIC_VAL32(Command_Intr, 1, 1) // software interrupt
105 __SINIC_VAL32(Command_Reset, 0, 1) // reset chip
106 
107 // Interrupt register bits
108 __SINIC_VAL32(Intr_Soft, 8, 1) // software interrupt
109 __SINIC_VAL32(Intr_TxLow, 7, 1) // tx fifo dropped below watermark
110 __SINIC_VAL32(Intr_TxFull, 6, 1) // tx fifo full
111 __SINIC_VAL32(Intr_TxDMA, 5, 1) // tx dma completed w/ interrupt
112 __SINIC_VAL32(Intr_TxPacket, 4, 1) // packet transmitted
113 __SINIC_VAL32(Intr_RxHigh, 3, 1) // rx fifo above high watermark
114 __SINIC_VAL32(Intr_RxEmpty, 2, 1) // rx fifo empty
115 __SINIC_VAL32(Intr_RxDMA, 1, 1) // rx dma completed w/ interrupt
116 __SINIC_VAL32(Intr_RxPacket, 0, 1) // packet received
117 __SINIC_REG32(Intr_All, 0x01ff) // all valid interrupts
118 __SINIC_REG32(Intr_NoDelay, 0x01cc) // interrupts that aren't coalesced
119 __SINIC_REG32(Intr_Res, ~0x01ff) // reserved interrupt bits
120 
121 // RX Data Description
122 __SINIC_VAL64(RxData_NoDelay, 61, 1) // Don't Delay this copy
123 __SINIC_VAL64(RxData_Vaddr, 60, 1) // Addr is virtual
124 __SINIC_VAL64(RxData_Len, 40, 20) // 0 - 256k
125 __SINIC_VAL64(RxData_Addr, 0, 40) // Address 1TB
126 
127 // TX Data Description
128 __SINIC_VAL64(TxData_More, 63, 1) // Packet not complete (will dma more)
129 __SINIC_VAL64(TxData_Checksum, 62, 1) // do checksum
130 __SINIC_VAL64(TxData_Vaddr, 60, 1) // Addr is virtual
131 __SINIC_VAL64(TxData_Len, 40, 20) // 0 - 256k
132 __SINIC_VAL64(TxData_Addr, 0, 40) // Address 1TB
133 
134 // RX Done/Busy Information
135 __SINIC_VAL64(RxDone_Packets, 32, 16) // number of packets in rx fifo
136 __SINIC_VAL64(RxDone_Busy, 31, 1) // receive dma busy copying
137 __SINIC_VAL64(RxDone_Complete, 30, 1) // valid data (packet complete)
138 __SINIC_VAL64(RxDone_More, 29, 1) // Packet has more data (dma again)
139 __SINIC_VAL64(RxDone_Empty, 28, 1) // rx fifo is empty
140 __SINIC_VAL64(RxDone_High, 27, 1) // rx fifo is above the watermark
141 __SINIC_VAL64(RxDone_NotHigh, 26, 1) // rxfifo never hit the high watermark
142 __SINIC_VAL64(RxDone_TcpError, 25, 1) // TCP packet error (bad checksum)
143 __SINIC_VAL64(RxDone_UdpError, 24, 1) // UDP packet error (bad checksum)
144 __SINIC_VAL64(RxDone_IpError, 23, 1) // IP packet error (bad checksum)
145 __SINIC_VAL64(RxDone_TcpPacket, 22, 1) // this is a TCP packet
146 __SINIC_VAL64(RxDone_UdpPacket, 21, 1) // this is a UDP packet
147 __SINIC_VAL64(RxDone_IpPacket, 20, 1) // this is an IP packet
148 __SINIC_VAL64(RxDone_CopyLen, 0, 20) // up to 256k
149 
150 // TX Done/Busy Information
151 __SINIC_VAL64(TxDone_Packets, 32, 16) // number of packets in tx fifo
152 __SINIC_VAL64(TxDone_Busy, 31, 1) // transmit dma busy copying
153 __SINIC_VAL64(TxDone_Complete, 30, 1) // valid data (packet complete)
154 __SINIC_VAL64(TxDone_Full, 29, 1) // tx fifo is full
155 __SINIC_VAL64(TxDone_Low, 28, 1) // tx fifo is below the watermark
156 __SINIC_VAL64(TxDone_Res0, 27, 1) // reserved
157 __SINIC_VAL64(TxDone_Res1, 26, 1) // reserved
158 __SINIC_VAL64(TxDone_Res2, 25, 1) // reserved
159 __SINIC_VAL64(TxDone_Res3, 24, 1) // reserved
160 __SINIC_VAL64(TxDone_Res4, 23, 1) // reserved
161 __SINIC_VAL64(TxDone_Res5, 22, 1) // reserved
162 __SINIC_VAL64(TxDone_Res6, 21, 1) // reserved
163 __SINIC_VAL64(TxDone_Res7, 20, 1) // reserved
164 __SINIC_VAL64(TxDone_CopyLen, 0, 20) // up to 256k
165 
166 __SINIC_VAL64(RxStatus_Dirty, 48, 16)
167 __SINIC_VAL64(RxStatus_Mapped, 32, 16)
168 __SINIC_VAL64(RxStatus_Busy, 16, 16)
169 __SINIC_VAL64(RxStatus_Head, 0, 16)
170 
171 struct Info
172 {
173  uint8_t size;
174  bool read;
175  bool write;
176  const char *name;
177 };
178 
179 } // namespace Regs
180 
181 inline const Regs::Info&
182 regInfo(Addr daddr)
183 {
184  static Regs::Info invalid = { 0, false, false, "invalid" };
185  static Regs::Info info [] = {
186  { 4, true, true, "Config" },
187  { 4, false, true, "Command" },
188  { 4, true, true, "IntrStatus" },
189  { 4, true, true, "IntrMask" },
190  { 4, true, false, "RxMaxCopy" },
191  { 4, true, false, "TxMaxCopy" },
192  { 4, true, false, "ZeroCopySize" },
193  { 4, true, false, "ZeroCopyMark" },
194  { 4, true, false, "VirtualCount" },
195  { 4, true, false, "RxMaxIntr" },
196  { 4, true, false, "RxFifoSize" },
197  { 4, true, false, "TxFifoSize" },
198  { 4, true, false, "RxFifoLow" },
199  { 4, true, false, "TxFifoLow" },
200  { 4, true, false, "RxFifoHigh" },
201  { 4, true, false, "TxFifoHigh" },
202  { 8, true, true, "RxData" },
203  invalid,
204  { 8, true, false, "RxDone" },
205  invalid,
206  { 8, true, false, "RxWait" },
207  invalid,
208  { 8, true, true, "TxData" },
209  invalid,
210  { 8, true, false, "TxDone" },
211  invalid,
212  { 8, true, false, "TxWait" },
213  invalid,
214  { 8, true, false, "HwAddr" },
215  invalid,
216  { 8, true, false, "RxStatus" },
217  invalid,
218  };
219 
220  return info[daddr / 4];
221 }
222 
223 inline bool
224 regValid(Addr daddr)
225 {
226  if (daddr > Regs::Size)
227  return false;
228 
229  if (regInfo(daddr).size == 0)
230  return false;
231 
232  return true;
233 }
234 
235 } // namespace Sinic
236 
237 #endif // __DEV_NET_SINICREG_HH__
Sinic::Regs::VirtualMask
static const int VirtualMask
Definition: sinicreg.hh:59
Sinic::Regs::Info
Definition: sinicreg.hh:171
Sinic::Regs::VirtualShift
static const int VirtualShift
Definition: sinicreg.hh:58
Sinic::Regs::Info::read
bool read
Definition: sinicreg.hh:174
Sinic
Definition: sinic.cc:49
Sinic::Regs::Info::size
uint8_t size
Definition: sinicreg.hh:173
Sinic::regInfo
const Regs::Info & regInfo(Addr daddr)
Definition: sinicreg.hh:182
Sinic::Regs::__SINIC_VAL64
__SINIC_VAL64(RxData_Vaddr, 60, 1) __SINIC_VAL64(RxData_Len
Sinic::Regs::Info::name
const char * name
Definition: sinicreg.hh:176
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
Sinic::Regs::Info::write
bool write
Definition: sinicreg.hh:175
Sinic::regValid
bool regValid(Addr daddr)
Definition: sinicreg.hh:224
Sinic::Regs::__SINIC_VAL32
__SINIC_VAL32(Config_ZeroCopy, 12, 1) __SINIC_VAL32(Config_DelayCopy
Sinic::Regs::__SINIC_REG32
__SINIC_REG32(Config, 0x00) __SINIC_REG32(Command
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