gem5
v20.1.0.0
systemc
tests
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misc
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regfile.h
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/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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regfile.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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struct
test
: sc_module {
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sc_in<bool>
reset
;
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sc_in_clk
clk
;
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sc_in<sc_lv<14> >
dati
;
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sc_out<sc_lv<14> >
dato
;
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sc_out<sc_logic>
ready
,
done
;
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SC_HAS_PROCESS
(
test
);
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test
(
const
char
*NAME) : sc_module(NAME) {
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SC_CTHREAD
(
reset_loop
,
clk
.pos() );
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reset_signal_is(
reset
,
true
);
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end_module();
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}
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void
reset_loop
();
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};
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test::reset
sc_in< bool > reset
Definition:
test.h:71
test
Definition:
test.h:38
test::ready
sc_out< sc_logic > ready
Definition:
regfile.h:75
test::SC_HAS_PROCESS
SC_HAS_PROCESS(test)
test::done
sc_out< bool > done
Definition:
test.h:75
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition:
sc_clock.hh:116
test::dati
sc_in< sc_uint< 8 > > dati
Definition:
test.h:73
test::test
test(const char *NAME)
Definition:
test.h:79
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition:
sc_module.hh:319
test::clk
sc_in_clk clk
Definition:
test.h:72
test::reset_loop
void reset_loop()
test::dato
sc_out< sc_uint< 8 > > dato
Definition:
test.h:74
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