Go to the documentation of this file.
29 #ifndef __CPU_O3_STORE_SET_HH__
30 #define __CPU_O3_STORE_SET_HH__
64 StoreSet(uint64_t clear_period,
int SSIT_size,
int LFST_size);
70 void init(uint64_t clear_period,
int SSIT_size,
int LFST_size);
116 {
return ((PC ^ (PC >> 10)) %
LFSTSize); }
135 typedef std::map<InstSeqNum, int, ltseqnum>::iterator
SeqNumMapIt;
158 #endif // __CPU_O3_STORE_SET_HH__
std::vector< InstSeqNum > LFST
Last Fetched Store Table.
void dump()
Debug function to dump the contents of the store list.
void insertStore(Addr store_PC, InstSeqNum store_seq_num, ThreadID tid)
Inserts a store into the store set predictor.
int16_t ThreadID
Thread index/ID type.
void insertLoad(Addr load_PC, InstSeqNum load_seq_num)
Inserts a load into the store set predictor.
InstSeqNum checkInst(Addr PC)
Checks if the instruction with the given PC is dependent upon any store.
int indexMask
Mask to obtain the index.
std::map< InstSeqNum, int, ltseqnum >::iterator SeqNumMapIt
void init(uint64_t clear_period, int SSIT_size, int LFST_size)
Initializes the store set predictor with the given table sizes.
int calcIndex(Addr PC)
Calculates the index into the SSIT based on the PC.
std::vector< bool > validSSIT
Bit vector to tell if the SSIT has a valid entry.
StoreSet()
Default constructor.
bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
Implements a store set predictor for determining if memory instructions are dependent upon each other...
int SSITSize
Store Set ID Table size, in entries.
void squash(InstSeqNum squashed_num, ThreadID tid)
Squashes for a specific thread until the given sequence number.
void checkClear()
Clears the store set predictor every so often so that all the entries aren't used and stores are cons...
void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store)
Records this PC/sequence number as issued.
std::vector< bool > validLFST
Bit vector to tell if the LFST has a valid entry.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
uint64_t clearPeriod
Number of loads/stores to process before wiping predictor so all entries don't get saturated.
void violation(Addr store_PC, Addr load_PC)
Records a memory ordering violation between the younger load and the older store.
std::map< InstSeqNum, int, ltseqnum > storeList
Map of stores that have been inserted into the store set, but not yet issued or squashed.
int LFSTSize
Last Fetched Store Table size, in entries.
void clear()
Resets all tables.
int memOpsPred
Number of memory operations predicted since last clear of predictor.
std::vector< SSID > SSIT
The Store Set ID Table.
SSID calcSSID(Addr PC)
Calculates a Store Set ID based on the PC.
~StoreSet()
Default destructor.
Generated on Wed Sep 30 2020 14:02:09 for gem5 by doxygen 1.8.17