gem5
v20.1.0.0
cpu
testers
traffic_gen
stream_gen.cc
Go to the documentation of this file.
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/*
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* Copyright (c) 2018 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed here under. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
stream_gen.hh
"
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#include "
base/random.hh
"
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StreamGen
*
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StreamGen::create
(
const
BaseTrafficGenParams *
p
)
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{
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switch
(
p
->stream_gen) {
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case
StreamGenType::fixed:
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return
new
FixedStreamGen
(
p
);
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case
StreamGenType::random
:
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return
new
RandomStreamGen
(
p
);
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case
StreamGenType::none
:
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default
:
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return
nullptr
;
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}
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}
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uint32_t
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RandomStreamGen::randomPick
(
const
std::vector<uint32_t>
&svec)
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{
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// Pick a random entry in the vector of IDs
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return
svec[
random_mt
.
random
<
size_t
>(0, svec.size()-1)];
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}
FixedStreamGen
Definition:
stream_gen.hh:102
random.hh
std::vector< uint32_t >
Stats::none
const FlagsType none
Nothing extra to print.
Definition:
info.hh:43
random_mt
Random random_mt
Definition:
random.cc:96
StreamGen::create
static StreamGen * create(const BaseTrafficGenParams *p)
Factory method for constructing a Stream generator.
Definition:
stream_gen.cc:43
stream_gen.hh
StreamGen
Definition:
stream_gen.hh:49
RandomStreamGen
Definition:
stream_gen.hh:121
RandomStreamGen::randomPick
uint32_t randomPick(const std::vector< uint32_t > &svec)
Function to pick one of the preset Stream or Substream ID.
Definition:
stream_gen.cc:57
Random::random
std::enable_if< std::is_integral< T >::value, T >::type random()
Use the SFINAE idiom to choose an implementation based on whether the type is integral or floating po...
Definition:
random.hh:86
MipsISA::random
random
Definition:
pra_constants.hh:50
MipsISA::p
Bitfield< 0 > p
Definition:
pra_constants.hh:323
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