GicV2::BankedRegs Struct Reference

Registers "banked for each connected processor" per ARM IHI0048B. More...

#include <gic_v2.hh>

Inheritance diagram for GicV2::BankedRegs:

Public Member Functions
void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...
void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...
	BankedRegs ()
Public Member Functions inherited from Serializable
	Serializable ()
virtual	~Serializable ()
void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...
void	serializeSection (CheckpointOut &cp, const std::string &name) const
void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...
void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Attributes
uint32_t	intEnabled
	GICD_I{S,C}ENABLER0 interrupt enable bits for first 32 interrupts, 1b per interrupt. More...
uint32_t	pendingInt
	GICD_I{S,C}PENDR0 interrupt pending bits for first 32 interrupts, 1b per interrupt. More...
uint32_t	activeInt
	GICD_I{S,C}ACTIVER0 interrupt active bits for first 32 interrupts, 1b per interrupt. More...
uint32_t	intGroup
	GICD_IGROUPR0 interrupt group bits for first 32 interrupts, 1b per interrupt. More...
uint32_t	intConfig [2]
	GICD_ICFGR0, GICD_ICFGR1 interrupt config bits for first 32 interrupts, 2b per interrupt. More...
uint8_t	intPriority [SGI_MAX+PPI_MAX]
	GICD_IPRIORITYR{0..7} interrupt priority for SGIs and PPIs. More...

Additional Inherited Members
Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...
static void	serializeAll (const std::string &cpt_dir)
	Serializes all the SimObjects. More...
static void	unserializeGlobals (CheckpointIn &cp)

Detailed Description

Registers "banked for each connected processor" per ARM IHI0048B.

Definition at line 179 of file gic_v2.hh.

Constructor & Destructor Documentation

BankedRegs()

GicV2::BankedRegs::BankedRegs ( )

inline

Definition at line 207 of file gic_v2.hh.

Member Function Documentation

serialize()

void GicV2::BankedRegs::serialize ( CheckpointOut &  cp ) const

overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Definition at line 1024 of file gic_v2.cc.

References activeInt, intConfig, intEnabled, intGroup, intPriority, pendingInt, GicV2::PPI_MAX, SERIALIZE_ARRAY, SERIALIZE_SCALAR, and GicV2::SGI_MAX.

unserialize()

void GicV2::BankedRegs::unserialize ( CheckpointIn &  cp )

overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Definition at line 1084 of file gic_v2.cc.

References GicV2::activeInt, GicV2::intConfig, GicV2::intEnabled, GicV2::intGroup, GicV2::intPriority, GicV2::pendingInt, GicV2::PPI_MAX, GicV2::SGI_MAX, UNSERIALIZE_ARRAY, and UNSERIALIZE_SCALAR.

Referenced by GicV2::unserialize().

Member Data Documentation

activeInt

uint32_t GicV2::BankedRegs::activeInt

GICD_I{S,C}ACTIVER0 interrupt active bits for first 32 interrupts, 1b per interrupt.

Definition at line 190 of file gic_v2.hh.

Referenced by GicV2::getActiveInt(), and serialize().

intConfig

uint32_t GicV2::BankedRegs::intConfig[2]

GICD_ICFGR0, GICD_ICFGR1 interrupt config bits for first 32 interrupts, 2b per interrupt.

Definition at line 198 of file gic_v2.hh.

Referenced by GicV2::getIntConfig(), and serialize().

intEnabled

uint32_t GicV2::BankedRegs::intEnabled

GICD_I{S,C}ENABLER0 interrupt enable bits for first 32 interrupts, 1b per interrupt.

Definition at line 182 of file gic_v2.hh.

Referenced by GicV2::getIntEnabled(), and serialize().

intGroup

uint32_t GicV2::BankedRegs::intGroup

GICD_IGROUPR0 interrupt group bits for first 32 interrupts, 1b per interrupt.

Definition at line 194 of file gic_v2.hh.

Referenced by GicV2::getIntGroup(), and serialize().

intPriority

uint8_t GicV2::BankedRegs::intPriority[SGI_MAX+PPI_MAX]

GICD_IPRIORITYR{0..7} interrupt priority for SGIs and PPIs.

Definition at line 202 of file gic_v2.hh.

Referenced by GicV2::getIntPriority(), and serialize().

pendingInt

uint32_t GicV2::BankedRegs::pendingInt

GICD_I{S,C}PENDR0 interrupt pending bits for first 32 interrupts, 1b per interrupt.

Definition at line 186 of file gic_v2.hh.

Referenced by GicV2::getPendingInt(), and serialize().

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The documentation for this struct was generated from the following files:

• dev/arm/gic_v2.hh
• dev/arm/gic_v2.cc