TimeBufStruct< Impl >::commitComm Struct Reference

#include <comm.hh>

Public Attributes
TheISA::PCState	pc
	The pc of the next instruction to execute. More...
DynInstPtr	mispredictInst
	Provide fetch the instruction that mispredicted, if this pointer is not-null a misprediction occured. More...
DynInstPtr	squashInst
	Instruction that caused the a non-mispredict squash. More...
DynInstPtr	strictlyOrderedLoad
	Hack for now to send back a strictly ordered access to the IEW stage. More...
InstSeqNum	nonSpecSeqNum
	Communication specifically to the IQ to tell the IQ that it can schedule a non-speculative instruction. More...
InstSeqNum	doneSeqNum
	Represents the instruction that has either been retired or squashed. More...
unsigned	freeROBEntries
	Tell Rename how many free entries it has in the ROB. More...
bool	squash
bool	robSquashing
bool	usedROB
	Rename should re-read number of free rob entries. More...
bool	emptyROB
	Notify Rename that the ROB is empty. More...
bool	branchTaken
	Was the branch taken or not. More...
bool	interruptPending
	If an interrupt is pending and fetch should stall. More...
bool	clearInterrupt
	If the interrupt ended up being cleared before being handled. More...
bool	strictlyOrdered
	Hack for now to send back an strictly ordered access to the IEW stage. More...

Detailed Description

template<class Impl>
struct TimeBufStruct< Impl >::commitComm

Definition at line 156 of file comm.hh.

Member Data Documentation

branchTaken

template<class Impl >

bool TimeBufStruct< Impl >::commitComm::branchTaken

Was the branch taken or not.

Definition at line 207 of file comm.hh.

clearInterrupt

template<class Impl >

bool TimeBufStruct< Impl >::commitComm::clearInterrupt

If the interrupt ended up being cleared before being handled.

Definition at line 211 of file comm.hh.

doneSeqNum

template<class Impl >

InstSeqNum TimeBufStruct< Impl >::commitComm::doneSeqNum

Represents the instruction that has either been retired or squashed.

Similar to having a single bus that broadcasts the retired or squashed sequence number.

Definition at line 192 of file comm.hh.

emptyROB

template<class Impl >

bool TimeBufStruct< Impl >::commitComm::emptyROB

Notify Rename that the ROB is empty.

Definition at line 204 of file comm.hh.

freeROBEntries

template<class Impl >

unsigned TimeBufStruct< Impl >::commitComm::freeROBEntries

Tell Rename how many free entries it has in the ROB.

Definition at line 195 of file comm.hh.

interruptPending

template<class Impl >

bool TimeBufStruct< Impl >::commitComm::interruptPending

If an interrupt is pending and fetch should stall.

Definition at line 209 of file comm.hh.

mispredictInst

template<class Impl >

DynInstPtr TimeBufStruct< Impl >::commitComm::mispredictInst

Provide fetch the instruction that mispredicted, if this pointer is not-null a misprediction occured.

Definition at line 176 of file comm.hh.

nonSpecSeqNum

template<class Impl >

InstSeqNum TimeBufStruct< Impl >::commitComm::nonSpecSeqNum

Communication specifically to the IQ to tell the IQ that it can schedule a non-speculative instruction.

Definition at line 187 of file comm.hh.

pc

template<class Impl >

TheISA::PCState TimeBufStruct< Impl >::commitComm::pc

The pc of the next instruction to execute.

This is the next instruction for a branch mispredict, but the same instruction for order violation and the like

Definition at line 172 of file comm.hh.

robSquashing

template<class Impl >

bool TimeBufStruct< Impl >::commitComm::robSquashing

Definition at line 198 of file comm.hh.

squash

template<class Impl >

bool TimeBufStruct< Impl >::commitComm::squash

Definition at line 197 of file comm.hh.

squashInst

template<class Impl >

DynInstPtr TimeBufStruct< Impl >::commitComm::squashInst

Instruction that caused the a non-mispredict squash.

Definition at line 179 of file comm.hh.

strictlyOrdered

template<class Impl >

bool TimeBufStruct< Impl >::commitComm::strictlyOrdered

Hack for now to send back an strictly ordered access to the IEW stage.

Definition at line 215 of file comm.hh.

strictlyOrderedLoad

template<class Impl >

DynInstPtr TimeBufStruct< Impl >::commitComm::strictlyOrderedLoad

Hack for now to send back a strictly ordered access to the IEW stage.

Definition at line 183 of file comm.hh.

usedROB

template<class Impl >

bool TimeBufStruct< Impl >::commitComm::usedROB

Rename should re-read number of free rob entries.

Definition at line 201 of file comm.hh.

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The documentation for this struct was generated from the following file:

• cpu/o3/comm.hh