gem5
v20.1.0.0
systemc
tests
systemc
misc
synth
add_chain
tb.h
Go to the documentation of this file.
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/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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tb.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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/******************************************************************************/
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/*************************** Testbench Function **********************/
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/******************************************************************************/
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/* */
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/* The testbench module has the following hierarchy: */
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/* */
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/* testbench */
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/* - RESET_STIM */
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/* - DATA_GEN */
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/* */
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/******************************************************************************/
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struct
testbench
:
public
sc_module {
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sc_signal<int>
addr
;
// Address of input memory
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sc_signal<bool>
reset
;
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sc_signal<bool>
ready
;
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signal_bool_vector8
data
;
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signal_bool_vector4
sum
;
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RESET_STIM
rd1
;
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DATA_GEN
dg1
;
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ADD_CHAIN
ac1
;
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DISPLAY
d1
;
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/*** Constructor ***/
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testbench
(
const
sc_module_name& NAME,
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sc_clock& TICK )
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: sc_module(),
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rd1
(
"RD1"
, TICK,
ready
,
reset
,
addr
),
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dg1
(
"DG1"
, TICK,
ready
,
data
,
addr
),
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ac1
(
"AC1"
, TICK,
reset
,
data
,
sum
,
ready
),
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d1
(
"D1"
,
ready
,
data
,
sum
)
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{
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end_module();
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}
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};
testbench::ac1
ADD_CHAIN ac1
Definition:
tb.h:89
testbench::reset
sc_signal< bool > reset
Definition:
tb.h:83
testbench
Definition:
tb.h:50
testbench::ready
sc_signal< bool > ready
Definition:
tb.h:84
testbench::d1
DISPLAY d1
Definition:
tb.h:90
testbench::rd1
RESET_STIM rd1
Definition:
tb.h:87
signal_bool_vector4
sc_signal< bool_vector4 > signal_bool_vector4
Definition:
common.h:46
testbench::data
signal_bool_vector8 data
Definition:
tb.h:85
testbench::addr
sc_signal< int > addr
Definition:
tb.h:82
testbench::sum
signal_bool_vector4 sum
Definition:
tb.h:86
testbench::dg1
DATA_GEN dg1
Definition:
tb.h:88
signal_bool_vector8
sc_signal< sc_bv< 8 > > signal_bool_vector8
Definition:
common.h:43
testbench::testbench
testbench(const sc_module_name &NAME, sc_clock &TICK)
Definition:
tb.h:93
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