gem5  v20.1.0.0
stimgen.h
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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6  Accellera licenses this file to you under the Apache License, Version 2.0
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20 /*****************************************************************************
21 
22  stimgen.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38  /**************************************/
39  /* Interface Filename: stimgen.h */
40  /**************************************/
41 
42 #include "common.h"
43 
44 SC_MODULE( stimgen )
45 {
46  SC_HAS_PROCESS( stimgen );
47 
48  sc_in_clk clk;
49 
50  // Inputs
51  const signal_bool_vector8& c;
52  const signal_bool_vector16& d;
53  const sc_signal<bool>& done;
54  // Outputs
57  sc_signal<int>& mode;
58  sc_signal<bool>& ready;
59 
60  // Constructor
61  stimgen (sc_module_name NAME,
62  sc_clock& TICK,
63  const signal_bool_vector8& C,
64  const signal_bool_vector16& D,
65  const sc_signal<bool>& DONE,
68  sc_signal<int>& MODE,
69  sc_signal<bool>& READY )
70 
71  :
72  c (C),
73  d (D),
74  done (DONE),
75  a (A),
76  b (B),
77  mode (MODE),
78  ready (READY)
79 
80  {
81  clk (TICK);
82  SC_CTHREAD( entry, clk.pos() );
83  }
84 
85  void entry();
86 };
common.h
ArmISA::a
Bitfield< 8 > a
Definition: miscregs_types.hh:62
SC_MODULE
SC_MODULE(stimgen)
Definition: stimgen.h:44
ArmISA::d
Bitfield< 9 > d
Definition: miscregs_types.hh:60
ArmISA::mode
Bitfield< 4, 0 > mode
Definition: miscregs_types.hh:70
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
ArmISA::b
Bitfield< 7 > b
Definition: miscregs_types.hh:376
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:319
ArmISA::c
Bitfield< 29 > c
Definition: miscregs_types.hh:50
signal_bool_vector8
sc_signal< sc_bv< 8 > > signal_bool_vector8
Definition: common.h:43
signal_bool_vector16
sc_signal< sc_bv< 16 > > signal_bool_vector16
Definition: common.h:44

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