gem5
v20.1.0.0
systemc
ext
tlm_core
1
analysis
write_if.hh
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/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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#ifndef __SYSTEMC_EXT_TLM_CORE_1_ANALYSIS_WRITE_IF_HH__
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#define __SYSTEMC_EXT_TLM_CORE_1_ANALYSIS_WRITE_IF_HH__
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#include "../../../core/sc_interface.hh"
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namespace
tlm
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{
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template
<
typename
T>
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class
tlm_write_if :
public
virtual
sc_core::sc_interface
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{
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public
:
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virtual
void
write
(
const
T &
t
) = 0;
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};
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template
<
typename
T>
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class
tlm_delayed_write_if :
public
virtual
sc_core::sc_interface
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{
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public
:
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virtual
void
write
(
const
T &
t
,
const
sc_core::sc_time
&time) = 0;
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};
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}
// namespace tlm
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#endif
/* __SYSTEMC_EXT_TLM_CORE_1_ANALYSIS_WRITE_IF_HH__ */
tlm::tlm_write_if::write
virtual void write(const T &t)=0
sc_core::sc_interface
Definition:
sc_interface.hh:37
sc_core::sc_time
Definition:
sc_time.hh:49
tlm
Definition:
analysis_fifo.hh:27
tlm::tlm_delayed_write_if::write
virtual void write(const T &t, const sc_core::sc_time &time)=0
ArmISA::t
Bitfield< 5 > t
Definition:
miscregs_types.hh:67
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