| _drainManager | Drainable | private |
| _drainState | Drainable | mutableprivate |
| _params | SimObject | protected |
| _system | AbstractMemory | protected |
| AbstractMemory(const AbstractMemory &) | AbstractMemory | private |
| AbstractMemory(const Params *p) | AbstractMemory | |
| access(PacketPtr pkt) | AbstractMemory | |
| accessLatency() const override | DRAMInterface | inlinevirtual |
| activateBank(Rank &rank_ref, Bank &bank_ref, Tick act_tick, uint32_t row) | DRAMInterface | private |
| activationLimit | DRAMInterface | private |
| activeRank | DRAMInterface | private |
| addLockedAddr(LockedAddr addr) | AbstractMemory | inline |
| addRankToRankDelay(Tick cmd_at) override | DRAMInterface | virtual |
| addrMapping | MemInterface | protected |
| addStat(Stats::Info *info) | Stats::Group | |
| addStatGroup(const char *name, Group *block) | Stats::Group | |
| allRanksDrained() const override | DRAMInterface | virtual |
| backdoor | AbstractMemory | protected |
| bankGroupArch | DRAMInterface | private |
| bankGroupsPerRank | DRAMInterface | private |
| banksPerRank | MemInterface | protected |
| burstDelay() const | DRAMInterface | inlineprivate |
| burstInterleave | DRAMInterface | private |
| burstReady(MemPacket *pkt) const override | DRAMInterface | inlinevirtual |
| burstSize | MemInterface | protected |
| burstsPerRowBuffer | MemInterface | protected |
| burstsPerStripe | MemInterface | protected |
| bytesPerBurst() const | MemInterface | inline |
| checkLockedAddrList(PacketPtr pkt) | AbstractMemory | protected |
| checkRefreshState(uint8_t rank) | DRAMInterface | |
| chooseNextFRFCFS(MemPacketQueue &queue, Tick min_col_at) const override | DRAMInterface | virtual |
| clkResyncDelay | DRAMInterface | private |
| clockDomain | Clocked | private |
| Clocked(ClockDomain &clk_domain) | Clocked | inlineprotected |
| Clocked(Clocked &)=delete | Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | Clocked | inline |
| ClockedObject(const ClockedObjectParams *p) | ClockedObject | |
| clockPeriod() const | Clocked | inline |
| clockPeriodUpdated() | Clocked | inlineprotectedvirtual |
| commandOffset() const override | DRAMInterface | inlinevirtual |
| confTableReported | AbstractMemory | protected |
| ctrl | MemInterface | protected |
| curCycle() const | Clocked | inline |
| currentSection() | Serializable | static |
| cycle | Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | Clocked | inline |
| dataClockSync | DRAMInterface | private |
| decodePacket(const PacketPtr pkt, Addr pkt_addr, unsigned int size, bool is_read, bool is_dram) | MemInterface | |
| deschedule(Event &event) | EventManager | inline |
| deschedule(Event *event) | EventManager | inline |
| deviceRowBufferSize | MemInterface | protected |
| deviceSize | MemInterface | protected |
| devicesPerRank | MemInterface | protected |
| dmDrain() | Drainable | private |
| dmDrainResume() | Drainable | private |
| doBurstAccess(MemPacket *mem_pkt, Tick next_burst_at, const std::vector< MemPacketQueue > &queue) | DRAMInterface | |
| drain() override | SimObject | inlinevirtual |
| Drainable() | Drainable | protected |
| drainRanks() | DRAMInterface | |
| drainResume() | Drainable | inlineprotectedvirtual |
| drainState() const | Drainable | inline |
| DRAMInterface(const DRAMInterfaceParams *_p) | DRAMInterface | |
| enableDRAMPowerdown | DRAMInterface | private |
| EventManager(EventManager &em) | EventManager | inline |
| EventManager(EventManager *em) | EventManager | inline |
| EventManager(EventQueue *eq) | EventManager | inline |
| eventq | EventManager | protected |
| eventQueue() const | EventManager | inline |
| find(const char *name) | SimObject | static |
| frequency() const | Clocked | inline |
| functionalAccess(PacketPtr pkt) | AbstractMemory | |
| getAddrRange() const | AbstractMemory | |
| getCtrlAddr(Addr addr) | MemInterface | inline |
| getLockedAddrList() const | AbstractMemory | inline |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) | SimObject | virtual |
| getProbeManager() | SimObject | |
| getStatGroups() const | Stats::Group | |
| getStats() const | Stats::Group | |
| Group()=delete | Stats::Group | |
| Group(const Group &)=delete | Stats::Group | |
| Group(Group *parent, const char *name=nullptr) | Stats::Group | |
| inAddrMap | AbstractMemory | protected |
| init() override | DRAMInterface | virtual |
| initState() override | AbstractMemory | virtual |
| isBusy() | DRAMInterface | |
| isConfReported() const | AbstractMemory | inline |
| isInAddrMap() const | AbstractMemory | inline |
| isKvmMap() const | AbstractMemory | inline |
| isNull() const | AbstractMemory | inline |
| kvmMap | AbstractMemory | protected |
| lastStatsResetTick | DRAMInterface | private |
| loadState(CheckpointIn &cp) | SimObject | virtual |
| lockedAddrList | AbstractMemory | protected |
| maxAccessesPerRow | DRAMInterface | private |
| maxCommandsPerWindow | MemInterface | protected |
| MemInterface(const Params *_p) | MemInterface | |
| memInvalidate() | SimObject | inlinevirtual |
| memWriteback() | SimObject | inlinevirtual |
| mergedParent | Stats::Group | private |
| mergedStatGroups | Stats::Group | private |
| mergeStatGroup(Group *block) | Stats::Group | private |
| minBankPrep(const MemPacketQueue &queue, Tick min_col_at) const | DRAMInterface | private |
| minReadToWriteDataGap() const | MemInterface | inline |
| minWriteToReadDataGap() const | MemInterface | inline |
| name() const | SimObject | inlinevirtual |
| nextCycle() const | Clocked | inline |
| notifyFork() | Drainable | inlinevirtual |
| operator=(const AbstractMemory &) | AbstractMemory | private |
| ClockedObject::operator=(const Group &)=delete | Stats::Group | |
| ClockedObject::operator=(Clocked &)=delete | Clocked | protected |
| pageMgmt | DRAMInterface | private |
| Params typedef | MemInterface | |
| params() const | AbstractMemory | inline |
| path | Serializable | privatestatic |
| pmemAddr | AbstractMemory | protected |
| powerState | ClockedObject | |
| PowerState enum name | DRAMInterface | private |
| prechargeBank(Rank &rank_ref, Bank &bank_ref, Tick pre_tick, bool auto_or_preall=false, bool trace=true) | DRAMInterface | private |
| preDumpStats() | Stats::Group | virtual |
| probeManager | SimObject | private |
| PWR_ACT enum value | DRAMInterface | private |
| PWR_ACT_PDN enum value | DRAMInterface | private |
| PWR_IDLE enum value | DRAMInterface | private |
| PWR_PRE_PDN enum value | DRAMInterface | private |
| PWR_REF enum value | DRAMInterface | private |
| PWR_SREF enum value | DRAMInterface | private |
| range | AbstractMemory | protected |
| rankDelay() const | MemInterface | inline |
| ranks | DRAMInterface | private |
| ranksPerChannel | MemInterface | protected |
| rankToRankDelay() const | MemInterface | inlineprotected |
| rdToWrDlySameBG | DRAMInterface | private |
| readBufferSize | MemInterface | |
| readToWriteDelay() const | MemInterface | inlineprotected |
| REF_DRAIN enum value | DRAMInterface | private |
| REF_IDLE enum value | DRAMInterface | private |
| REF_PD_EXIT enum value | DRAMInterface | private |
| REF_PRE enum value | DRAMInterface | private |
| REF_RUN enum value | DRAMInterface | private |
| REF_SREF_EXIT enum value | DRAMInterface | private |
| REF_START enum value | DRAMInterface | private |
| RefreshState enum name | DRAMInterface | private |
| regProbeListeners() | SimObject | virtual |
| regProbePoints() | SimObject | virtual |
| regStats() | Stats::Group | virtual |
| reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
| resetClock() const | Clocked | inlineprotected |
| resetStats() | Stats::Group | virtual |
| resolveStat(std::string name) const | Stats::Group | |
| respondEvent(uint8_t rank) | DRAMInterface | |
| rowBufferSize | MemInterface | protected |
| rowsPerBank | MemInterface | protected |
| schedule(Event &event, Tick when) | EventManager | inline |
| schedule(Event *event, Tick when) | EventManager | inline |
| Serializable() | Serializable | |
| serialize(CheckpointOut &cp) const override | ClockedObject | virtual |
| serializeAll(CheckpointOut &cp) | SimObject | static |
| Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
| serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
| setBackingStore(uint8_t *pmem_addr) | AbstractMemory | |
| setCtrl(MemCtrl *_ctrl, unsigned int command_window) | MemInterface | |
| setCurTick(Tick newVal) | EventManager | inline |
| setupRank(const uint8_t rank, const bool is_read) override | DRAMInterface | virtual |
| signalDrainDone() const | Drainable | inlineprotected |
| SimObject(const Params *_params) | SimObject | |
| SimObjectList typedef | SimObject | private |
| simObjectList | SimObject | privatestatic |
| size() const | AbstractMemory | inline |
| sortTime(const Command &cmd, const Command &cmd_next) | DRAMInterface | inlineprivatestatic |
| start() const | AbstractMemory | inline |
| startup() override | DRAMInterface | virtual |
| statGroups | Stats::Group | private |
| stats | DRAMInterface | private |
| suspend() | DRAMInterface | |
| system() const | AbstractMemory | inline |
| system(System *sys) | AbstractMemory | inline |
| tAAD | DRAMInterface | private |
| tBURST | MemInterface | protected |
| tBURST_MAX | DRAMInterface | private |
| tBURST_MIN | DRAMInterface | private |
| tCCD_L | DRAMInterface | private |
| tCCD_L_WR | DRAMInterface | private |
| tCK | MemInterface | protected |
| tCL | DRAMInterface | private |
| tCS | MemInterface | protected |
| tick | Clocked | mutableprivate |
| ticksToCycles(Tick t) const | Clocked | inline |
| timeStampOffset | DRAMInterface | private |
| toHostAddr(Addr addr) const | AbstractMemory | inline |
| tPPD | DRAMInterface | private |
| trackLoadLocked(PacketPtr pkt) | AbstractMemory | protected |
| tRAS | DRAMInterface | private |
| tRCD | DRAMInterface | private |
| tREFI | DRAMInterface | private |
| tRFC | DRAMInterface | private |
| tRP | DRAMInterface | private |
| tRRD | DRAMInterface | private |
| tRRD_L | DRAMInterface | private |
| tRTP | DRAMInterface | private |
| tRTW | MemInterface | protected |
| twoCycleActivate | DRAMInterface | private |
| tWR | DRAMInterface | private |
| tWTR | MemInterface | protected |
| tXAW | DRAMInterface | private |
| tXP | DRAMInterface | private |
| tXS | DRAMInterface | private |
| unserialize(CheckpointIn &cp) override | ClockedObject | virtual |
| unserializeGlobals(CheckpointIn &cp) | Serializable | static |
| unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
| update() const | Clocked | inlineprivate |
| updateClockPeriod() | Clocked | inline |
| voltage() const | Clocked | inline |
| wakeupEventQueue(Tick when=(Tick) -1) | EventManager | inline |
| writeBufferSize | MemInterface | |
| writeOK(PacketPtr pkt) | AbstractMemory | inlineprotected |
| writeToReadDelay() const override | DRAMInterface | inlineprivatevirtual |
| wrToRdDlySameBG | DRAMInterface | private |
| ~AbstractMemory() | AbstractMemory | inlinevirtual |
| ~Clocked() | Clocked | inlineprotectedvirtual |
| ~Drainable() | Drainable | protectedvirtual |
| ~Group() | Stats::Group | virtual |
| ~Serializable() | Serializable | virtual |
| ~SimObject() | SimObject | virtual |
