- r -

RateGen : Intel8254Timer
RawISR : PL031 , Sp804::Timer
Read : BaseTLB
read : PipeFDEntry
READ : QoS::MemCtrl
Readable : MemBackdoor
ReadCleanReq : MemCmd
ReadControllerRamBase : X86ISA::I8042
ReadExReq : MemCmd
ReadExResp : MemCmd
ReadInputPort : X86ISA::I8042
ReadOnly : EmulationPageTable
ReadOutputPort : X86ISA::I8042
ReadReq : MemCmd
ReadResp : MemCmd
ReadRespWithInvalidate : MemCmd
ReadSharedReq : MemCmd
ReadTestInputs : X86ISA::I8042
Ready : RiscvISA::Walker::WalkerState , X86ISA::Walker::WalkerState
RECEIVING_ADDR : I2CBus
RECEIVING_DATA : I2CBus
RecordResult : BaseDynInst< Impl >
RecoverInst : BaseDynInst< Impl >
Red_Select : HDLcd
REF_DRAIN : DRAMInterface
REF_IDLE : DRAMInterface
REF_PD_EXIT : DRAMInterface
REF_PRE : DRAMInterface
REF_RUN : DRAMInterface
REF_SREF_EXIT : DRAMInterface
REF_START : DRAMInterface
REG_D : Trace::TarmacBaseRecord
REG_MISC : Trace::TarmacBaseRecord
REG_P : Trace::TarmacBaseRecord
REG_Q : Trace::TarmacBaseRecord
REG_R : Trace::TarmacBaseRecord
REG_S : Trace::TarmacBaseRecord
REG_X : Trace::TarmacBaseRecord
REG_Z : Trace::TarmacBaseRecord
regControllerCapabilities : UFSHostDevice
regControllerDEVID : UFSHostDevice
regControllerEnable : UFSHostDevice
regControllerPRODID : UFSHostDevice
regControllerStatus : UFSHostDevice
regInterruptEnable : UFSHostDevice
regInterruptStatus : UFSHostDevice
regUFSVersion : UFSHostDevice
regUICCommand : UFSHostDevice
regUICCommandArg1 : UFSHostDevice
regUICCommandArg2 : UFSHostDevice
regUICCommandArg3 : UFSHostDevice
regUICErrorCodeDataLinkLayer : UFSHostDevice
regUICErrorCodeDME : UFSHostDevice
regUICErrorCodeNetworkLayer : UFSHostDevice
regUICErrorCodePHYAdapterLayer : UFSHostDevice
regUICErrorCodeTransportLayer : UFSHostDevice
regUTPTaskREQDoorbell : UFSHostDevice
regUTPTaskREQListBaseH : UFSHostDevice
regUTPTaskREQListBaseL : UFSHostDevice
regUTPTaskREQListClear : UFSHostDevice
regUTPTaskREQListRunStop : UFSHostDevice
regUTPTransferREQDoorbell : UFSHostDevice
regUTPTransferREQINTAGGControl : UFSHostDevice
regUTPTransferREQListBaseH : UFSHostDevice
regUTPTransferREQListBaseL : UFSHostDevice
regUTPTransferREQListClear : UFSHostDevice
regUTPTransferREQListRunStop : UFSHostDevice
RELEASE : Request
RenameIdx : FullO3CPU< Impl >
ReqMade : BaseDynInst< Impl >
RequestIssuing : Minor::Fetch1::FetchRequest , Minor::LSQ::LSQRequest
RequestNeedsRetry : Minor::LSQ::LSQRequest
Reserved : ArmISA::TableWalker::L1Descriptor , Iob
ReservedGrain : ArmISA::TableWalker
Reset : Iob
ResetCtl : RealViewCtrl
ResetState : X86ISA::Decoder
RESPONDER_FLAGS : Packet
RESPONDER_HAD_WRITABLE : Packet
ResultReady : BaseDynInst< Impl >
Resume : Iob
RETRY : BaseXBar::Layer< SrcType, DstType >
Retry : LSQ< Impl >::LSQRequest
RFBUSY : ScheduleStage
RFREADY : ScheduleStage
Right : Prefetcher::BOP
ROB : DefaultRename< Impl >
RobEntry : BaseDynInst< Impl >
ROBSquashing : DefaultCommit< Impl > , ROB< Impl >
RRRR : Compressor::FPCD
Running : BaseKvmCPU , BaseSimpleCPU , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl > , ROB< Impl >
RunningMMIOPending : BaseKvmCPU
RunningService : BaseKvmCPU
RunningServiceCompletion : BaseKvmCPU
rxAdvance : NSGigE
rxBeginCopy : Sinic::Device
rxCopy : Sinic::Device
rxCopyDone : Sinic::Device
rxDescRead : NSGigE
rxDescRefr : NSGigE
rxDescWrite : NSGigE
rxFifoBlock : NSGigE , Sinic::Device
rxFragWrite : NSGigE
rxIdle : NSGigE , Sinic::Device