- o -

• obj : RequestorInfo
• object : EventWrapper< T, F > , ProbeListenerArg< T, Arg > , ProbeManager , Stats::MethodProxy< T, V > , Ticked
• objectParamsByName : CxxConfigManager
• objectsByName : CxxConfigManager
• objectsInOrder : CxxConfigManager
• objFile : Process
• objName : DistEtherLink::Link , EtherLink::Link , EtherSwitch::Interface::PortFifo , EventQueue
• objNameResolver : CheckpointIn
• objs : sc_core::sc_vector_base
• occupancies : BaseTags::BaseTagStats
• occupanciesTaskId : BaseTags::BaseTagStats
• occupancy : BaseXBar::Layer< SrcType, DstType > , Minor::SelfStallingPipeline< ElemType, ReportTraits, BubbleTraits > , MultiperspectivePerceptron::ThreadData
• oemID : X86ISA::ACPI::RSDP , X86ISA::ACPI::SysDescTable , X86ISA::IntelMP::ConfigTable
• oemRevision : X86ISA::ACPI::SysDescTable
• oemTableAddr : X86ISA::IntelMP::ConfigTable
• oemTableID : X86ISA::ACPI::SysDescTable
• oemTableSize : X86ISA::IntelMP::ConfigTable
• oeSet : PowerISA::IntOp
• OFF_DEVICE_FEATURES : PciVirtIO
• OFF_DEVICE_STATUS : PciVirtIO
• OFF_GUEST_FEATURES : PciVirtIO
• OFF_ISR_STATUS : PciVirtIO
• OFF_QUEUE_ADDRESS : PciVirtIO
• OFF_QUEUE_NOTIFY : PciVirtIO
• OFF_QUEUE_SELECT : PciVirtIO
• OFF_QUEUE_SIZE : PciVirtIO
• OFF_VIO_DEVICE : PciVirtIO
• offChipMemoryLatency : Prefetcher::AccessMapPatternMatching
• OFFEN : Gcn3ISA::InFmt_MTBUF , Gcn3ISA::InFmt_MUBUF
• offlg : Net::ip6_opt_fragment
• offset : ArmISA::ArmFault::FaultVals , ArmISA::Decoder , ArmISA::MemoryReg64 , ArmISA::SveContigMemSS , ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType > , ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType > , ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType > , BmpWriter::FileHeader
• OFFSET : Gcn3ISA::InFmt_MTBUF , Gcn3ISA::InFmt_MUBUF , Gcn3ISA::InFmt_SMEM_1
• offset : GenericWatchdog , Gicv3Its , HDLcd , Intel8254Timer::Counter , MC146818::RTCEvent , MC146818::RTCTickEvent , MipsISA::MipsFaultBase::FaultVals , PixelConverter::Channel , Prefetcher::STeMS::ActiveGenerationTableEntry::SequenceEntry , RiscvISA::MemInst , SparcISA::BlockMemMicro , Stats::VectorProxy< Stat > , UFSHostDevice::SCSIReply , UFSHostDevice::transferInfo , X86ISA::Decoder
• OFFSET0 : Gcn3ISA::InFmt_DS
• OFFSET1 : Gcn3ISA::InFmt_DS
• offsetBits : BloomFilter::Base , StoreSet
• offsetFormat : ArmISA::SveAdrOp
• offsetIs32 : ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >
• offsetIsScaled : ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >
• offsetIsSigned : ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >
• offsetMask : EmulationPageTable
• OffsetMask : MipsISA::PTE , PowerISA::PTE
• offsets : WalkCache
• offsetsList : Prefetcher::BOP
• offsetsListIterator : Prefetcher::BOP
• old_eq : EventQueue::ScopedMigration
• oldData : BaseCache::DataUpdate
• oldDgpr : Wavefront
• oldDgprId : Wavefront
• oldDgprTcnt : Wavefront
• oldestInFlightRobNum : TraceCPU::ElasticDataGen::HardwareResource
• oldestInst : InstructionQueue< Impl >::ListOrderEntry
• oldR11Val : Trace::X86NativeTrace
• oldRcxVal : Trace::X86NativeTrace
• oldRealR11Val : Trace::X86NativeTrace
• oldRealRcxVal : Trace::X86NativeTrace
• oldStamp : sc_gem5::TraceVal<::sc_core::sc_event, Base >
• oldState : Trace::ArmNativeTrace::ThreadState
• oldVal : sc_gem5::TraceVal< T, Base > , sc_gem5::TraceVal<::sc_core::sc_signal_in_if< T >, Base > , sc_gem5::TraceValFxnumBase< T, Base >
• oldVgpr : Wavefront
• oldVgprId : Wavefront
• oldVgprTcnt : Wavefront
• OMOD : Gcn3ISA::InFmt_VOP3_1
• once : GenericISA::M5DebugOnceFault< Flavor >
• onData : Prefetcher::Base
• oneTraceComplete : TraceCPU
• ongoingTranslation : Prefetcher::Queued::DeferredPacket
• onInst : Prefetcher::Base
• onMiss : Prefetcher::Base
• onRead : Prefetcher::Base
• onUse : ArmISA::BrkPoint
• onWrite : Prefetcher::Base
• oobMask : Gcn3ISA::Inst_MUBUF
• op : AtomicGeneric2Op< T > , AtomicGeneric3Op< T > , AtomicGenericPair3Op< T >
• OP : Gcn3ISA::InFmt_DS , Gcn3ISA::InFmt_FLAT , Gcn3ISA::InFmt_MIMG , Gcn3ISA::InFmt_MTBUF , Gcn3ISA::InFmt_MUBUF , Gcn3ISA::InFmt_SMEM , Gcn3ISA::InFmt_SOP1 , Gcn3ISA::InFmt_SOP2 , Gcn3ISA::InFmt_SOPC , Gcn3ISA::InFmt_SOPK , Gcn3ISA::InFmt_SOPP , Gcn3ISA::InFmt_VINTRP , Gcn3ISA::InFmt_VOP1 , Gcn3ISA::InFmt_VOP2 , Gcn3ISA::InFmt_VOP3 , Gcn3ISA::InFmt_VOP3_SDST_ENC , Gcn3ISA::InFmt_VOPC
• op : MathExpr::Node , MathExpr::OpSearch , RiscvISA::AtomicGenericOp< T > , TimingExprBin , TimingExprUn , X86ISA::ExtMachInst
• op1 : ArmISA::BranchEretA64 , ArmISA::BranchImmImmReg64 , ArmISA::BranchImmReg64 , ArmISA::BranchImmReg , ArmISA::BranchReg64 , ArmISA::BranchReg , ArmISA::BranchRegReg64 , ArmISA::BranchRegReg , ArmISA::DataImmOp , ArmISA::DataRegOp , ArmISA::DataRegRegOp , ArmISA::DataX1Reg2ImmOp , ArmISA::DataX1RegImmOp , ArmISA::DataX1RegOp , ArmISA::DataX2RegImmOp , ArmISA::DataX2RegOp , ArmISA::DataX3RegOp , ArmISA::DataXCondCompImmOp , ArmISA::DataXCondCompRegOp , ArmISA::DataXCondSelOp , ArmISA::DataXERegOp , ArmISA::DataXImmOp , ArmISA::DataXSRegOp , ArmISA::FpCondCompRegOp , ArmISA::FpCondSelOp , ArmISA::FpRegRegImmOp , ArmISA::FpRegRegOp , ArmISA::FpRegRegRegCondOp , ArmISA::FpRegRegRegImmOp , ArmISA::FpRegRegRegOp , ArmISA::FpRegRegRegRegOp , ArmISA::MicroNeonMixLaneOp64 , ArmISA::MicroNeonMixOp64 , ArmISA::MicroNeonMixOp , ArmISA::SveAdrOp , ArmISA::SveBinConstrPredOp , ArmISA::SveBinIdxUnpredOp , ArmISA::SveBinImmIdxUnpredOp , ArmISA::SveBinImmUnpredConstrOp , ArmISA::SveBinImmUnpredDestrOp , ArmISA::SveBinUnpredOp , ArmISA::SveCmpImmOp , ArmISA::SveCmpOp , ArmISA::SveComplexIdxOp , ArmISA::SveComplexOp , ArmISA::SveCompTermOp , ArmISA::SveDotProdIdxOp , ArmISA::SveDotProdOp , ArmISA::SveIndexRIOp , ArmISA::SveIndexRROp , ArmISA::SveIntCmpImmOp , ArmISA::SveIntCmpOp , ArmISA::SveOrdReducOp , ArmISA::SvePartBrkOp , ArmISA::SvePartBrkPropOp , ArmISA::SvePredBinPermOp , ArmISA::SvePredCountPredOp , ArmISA::SvePredLogicalOp , ArmISA::SvePredTestOp , ArmISA::SvePredUnaryWImplicitDstOp , ArmISA::SveReducOp , ArmISA::SveSelectOp , ArmISA::SveTblOp , ArmISA::SveTerPredOp , ArmISA::SveUnaryPredOp , ArmISA::SveUnaryPredPredOp , ArmISA::SveUnarySca2VecUnpredOp , ArmISA::SveUnaryUnpredOp , ArmISA::SveUnpackOp , ArmISA::SveWhileOp , McrrOp , MiscRegRegImmOp64 , MiscRegRegImmOp , MrrcOp , MsrRegOp , RegImmRegOp , RegImmRegShiftOp , RegMiscRegImmOp64 , RegMiscRegImmOp , RegRegImmImmOp64 , RegRegImmImmOp , RegRegImmOp , RegRegOp , RegRegRegImmOp64 , RegRegRegImmOp , RegRegRegOp , RegRegRegRegOp
• op2 : ArmISA::BranchRegReg64 , ArmISA::BranchRegReg , ArmISA::DataRegOp , ArmISA::DataRegRegOp , ArmISA::DataX2RegImmOp , ArmISA::DataX2RegOp , ArmISA::DataX3RegOp , ArmISA::DataXCondCompRegOp , ArmISA::DataXCondSelOp , ArmISA::DataXERegOp , ArmISA::DataXSRegOp , ArmISA::FpCondCompRegOp , ArmISA::FpCondSelOp , ArmISA::FpRegRegRegCondOp , ArmISA::FpRegRegRegImmOp , ArmISA::FpRegRegRegOp , ArmISA::FpRegRegRegRegOp , ArmISA::SveAdrOp , ArmISA::SveBinConstrPredOp , ArmISA::SveBinDestrPredOp , ArmISA::SveBinIdxUnpredOp , ArmISA::SveBinUnpredOp , ArmISA::SveCmpOp , ArmISA::SveComplexIdxOp , ArmISA::SveComplexOp , ArmISA::SveCompTermOp , ArmISA::SveDotProdIdxOp , ArmISA::SveDotProdOp , ArmISA::SveIndexIROp , ArmISA::SveIndexRROp , ArmISA::SveIntCmpOp , ArmISA::SvePartBrkPropOp , ArmISA::SvePredBinPermOp , ArmISA::SvePredLogicalOp , ArmISA::SveTblOp , ArmISA::SveTerImmUnpredOp , ArmISA::SveTerPredOp , ArmISA::SveWhileOp , McrrOp , RegRegRegImmOp64 , RegRegRegImmOp , RegRegRegOp , RegRegRegRegOp
• op2IsWide : ArmISA::SveIntCmpOp
• op3 : ArmISA::DataX3RegOp , ArmISA::FpRegRegRegRegOp , RegRegRegRegOp
• opClass : MinorOpClass , OpDesc
• opClasses : MinorFU , MinorFUTiming , MinorOpClassSet
• opcode : Trace::TarmacBaseRecord::InstEntry , X86ISA::ExtMachInst
• opDescList : FUDesc
• opdNrdyStalls : ScheduleStage::ScheduleStageStats
• openFlagTable : ArmFreebsd32 , ArmFreebsd64 , ArmLinux32 , ArmLinux64 , MipsLinux , PowerLinux , RiscvLinux32 , RiscvLinux64 , SparcLinux , SparcSolaris , X86Linux32 , X86Linux64
• openRow : MemInterface::Bank
• operandNetworkLength : ComputeUnit
• opLat : MinorFU , OpDesc
• opLatencies : FuncUnit
• ops : MathExpr
• opsCommitted : DefaultCommit< Impl >::CommitStats
• opSize : X86ISA::ExtMachInst , X86ISA::X86MicroopBase
• opSys : Loader::ObjectFile
• optionalAgeReset : LoopPredictor
• or0 : ContextDescriptor
• or1 : ContextDescriptor
• or_table : sc_dt::sc_logic
• order : BaseCache , QueueEntry , QueueEntry::Target
• ORHostControllerEnable : UFSHostDevice::HCIMem
• ORHostControllerStatus : UFSHostDevice::HCIMem
• origAddr : AddrMapper::AddrMapperSenderState
• originalPacket : SimpleCache
• originalPort : PendingWriteInst
• originalRanges : RangeAddrMapper
• origLength : TAGEBase::FoldedHistory
• origLoc : TesterThread::OutstandingReq
• origPC : X86ISA::Decoder
• ORInterruptEnable : UFSHostDevice::HCIMem
• ORInterruptStatus : UFSHostDevice::HCIMem
• ORUECDL : UFSHostDevice::HCIMem
• ORUECDME : UFSHostDevice::HCIMem
• ORUECN : UFSHostDevice::HCIMem
• ORUECPA : UFSHostDevice::HCIMem
• ORUECT : UFSHostDevice::HCIMem
• ORUTRIACR : UFSHostDevice::HCIMem
• os : Packet::PrintReqState
• oslk : ArmISA::SelfDebug
• out : m5::stl_helpers::ContainerPrint< T > , Minor::Decode , Minor::Execute , Minor::Fetch1 , Minor::Fetch2 , tlm_utils::peq_with_cb_and_phase< OWNER, TYPES >::delta_list , writer< T >
• out_a0 : fun
• out_a1 : fun
• out_clk2_neg : testbench
• out_clk2_pos : testbench
• out_clk_neg : testbench
• out_clk_pos : testbench
• out_valid1 : memory
• out_value1 : b_new_struct
• out_value2 : b_new_struct
• outBuffer : OutputUnit , PS2Device
• outcome : X86ISA::GpuTLB::TLBEvent
• outerAttrs : ArmISA::TlbEntry
• outerCache : Gicv3Its
• outerShareable : ArmISA::TlbEntry
• outfile : Terminal
• outNode_ptr : NetworkInterface
• outOfBytes : ArmISA::Decoder , X86ISA::Decoder
• outpoint : TAGEBase::FoldedHistory
• outPorts : NetworkInterface
• output : Plic , X86ISA::I8259
• output_high : Intel8254Timer::Counter
• outputChar : MipsAccess
• outputFifo : EtherSwitch::Interface
• outputFull : X86ISA::I8042
• outputQueue : Plic
• outputWidth : Minor::Decode , Minor::Fetch2
• outputWire : Minor::Latch< Data >::Output
• outstanding : LSQ< Impl >::LSQSenderState , TimingSimpleCPU::SplitMainSenderState , WholeTranslationState
• outstandingAddrs : MemTest
• outstandingAtomics : TesterThread
• outstandingCMO : CoherentXBar
• outstandingEvents : DRAMInterface::Rank
• outstandingLoads : TesterThread
• outstandingReadReqs : CommMonitor::MonitorStats
• outstandingReads : DRAMSim2 , DRAMsim3 , MemChecker::ByteTracker
• outstandingReadsHist : CommMonitor::MonitorStats
• outstandingReqs : Wavefront , X86ISA::GpuTLB
• outstandingReqsRdGm : Wavefront
• outstandingReqsRdLm : Wavefront
• outstandingReqsWrGm : Wavefront
• outstandingReqsWrLm : Wavefront
• outstandingResponses : Bridge::BridgeResponsePort , SerialLink::SerialLinkResponsePort
• outstandingSnoop : Cache , CoherentXBar
• outstandingStores : TesterThread
• outstandingWriteReqs : CommMonitor::MonitorStats
• outstandingWrites : DRAMSim2 , DRAMsim3
• outstandingWritesHist : CommMonitor::MonitorStats
• outTransLatHist : AbstractController::ControllerStats
• outTransLatHistRetries : AbstractController::ControllerStats
• outVcState : NetworkInterface , OutputUnit
• OVAddr : ArmISA::AbortFault< T >
• oVAddr : ArmISA::Stage2MMU::Stage2Translation
• overallAccesses : BaseCache::CacheStats
• overallAvgMissLatency : BaseCache::CacheStats
• overallAvgMshrMissLatency : BaseCache::CacheStats
• overallAvgMshrUncacheableLatency : BaseCache::CacheStats
• overallHits : BaseCache::CacheStats
• overallMisses : BaseCache::CacheStats
• overallMissLatency : BaseCache::CacheStats
• overallMissRate : BaseCache::CacheStats
• overallMshrHits : BaseCache::CacheStats
• overallMshrMisses : BaseCache::CacheStats
• overallMshrMissLatency : BaseCache::CacheStats
• overallMshrMissRate : BaseCache::CacheStats
• overallMshrUncacheable : BaseCache::CacheStats
• overallMshrUncacheableLatency : BaseCache::CacheStats
• overflow : Stats::DistData , Stats::DistStor
• overflow64 : ArmISA::PMU::CounterState
• overrideEc : ArmISA::HypervisorTrap , ArmISA::SecureMonitorTrap , ArmISA::SupervisorCall , ArmISA::SupervisorTrap , ArmISA::UndefinedInstruction
• overrunError : Uart8250
• owner : ExternalMaster::ExternalPort , ExternalSlave::ExternalPort , Prefetcher::Queued::DeferredPacket , RequestPort , ResponsePort , SimpleCache::CPUSidePort , SimpleCache::MemSidePort , SimpleMemobj::CPUSidePort , SimpleMemobj::MemSidePort , TraceCPU::DcachePort , TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen , TraceCPU::IcachePort
• ownerLds : LdsState::CuSidePort