#include <compute_unit.hh>

Inheritance diagram for ComputeUnit:

Classes
struct	ComputeUnitStats

class	DataPort
	Data access Port. More...

class	DTLBPort
	Data TLB port. More...

class	GMTokenPort

class	ITLBPort

class	LDSPort
	the port intended to communicate between the CU and its LDS More...

class	ScalarDataPort

class	ScalarDTLBPort

class	SQCPort

Public Types
typedef ComputeUnitParams	Params

typedef std::unordered_map< Addr, std::pair< int, int > >	pageDataStruct

Public Types inherited from ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject. More...

Public Types inherited from SimObject
typedef SimObjectParams	Params

Public Member Functions
int	numExeUnits () const

int	firstMemUnit () const

int	lastMemUnit () const

int	mapWaveToScalarAlu (Wavefront *w) const

int	mapWaveToScalarAluGlobalIdx (Wavefront *w) const

int	mapWaveToGlobalMem (Wavefront *w) const

int	mapWaveToLocalMem (Wavefront *w) const

int	mapWaveToScalarMem (Wavefront *w) const

void	insertInPipeMap (Wavefront *w)

void	deleteFromPipeMap (Wavefront *w)

	ComputeUnit (const Params &p)

	~ComputeUnit ()

int	oprNetPipeLength () const

int	simdUnitWidth () const

int	spBypassLength () const

int	dpBypassLength () const

int	scalarPipeLength () const

int	storeBusLength () const

int	loadBusLength () const

int	wfSize () const

void	exec ()

void	initiateFetch (Wavefront *wavefront)

void	fetch (PacketPtr pkt, Wavefront *wavefront)

void	fillKernelState (Wavefront w, HSAQueueEntry task)

void	startWavefront (Wavefront w, int waveId, LdsChunk ldsChunk, HSAQueueEntry *task, int bar_id, bool fetchContext=false)

void	doInvalidate (RequestPtr req, int kernId)
	trigger invalidate operation in the cu More...

void	doFlush (GPUDynInstPtr gpuDynInst)
	trigger flush operation in the cu More...

void	dispWorkgroup (HSAQueueEntry *task, int num_wfs_in_wg)

bool	hasDispResources (HSAQueueEntry *task, int &num_wfs_in_wg)

int	cacheLineSize () const

int	getCacheLineBits () const

void	resetRegisterPool ()

int	numYetToReachBarrier (int bar_id)

bool	allAtBarrier (int bar_id)

void	incNumAtBarrier (int bar_id)

int	numAtBarrier (int bar_id)

int	maxBarrierCnt (int bar_id)

void	resetBarrier (int bar_id)

void	decMaxBarrierCnt (int bar_id)

void	releaseBarrier (int bar_id)

void	releaseWFsFromBarrier (int bar_id)

int	numBarrierSlots () const

template<typename c0 , typename c1 >
void	doSmReturn (GPUDynInstPtr gpuDynInst)

virtual void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

void	sendRequest (GPUDynInstPtr gpuDynInst, PortID index, PacketPtr pkt)

void	sendScalarRequest (GPUDynInstPtr gpuDynInst, PacketPtr pkt)

void	injectGlobalMemFence (GPUDynInstPtr gpuDynInst, bool kernelMemSync, RequestPtr req=nullptr)

void	handleMemPacket (PacketPtr pkt, int memport_index)

bool	processTimingPacket (PacketPtr pkt)

void	processFetchReturn (PacketPtr pkt)

void	updatePageDivergenceDist (Addr addr)

RequestorID	requestorId ()

bool	isDone () const

bool	isVectorAluIdle (uint32_t simdId) const

LdsState &	getLds () const

int32_t	getRefCounter (const uint32_t dispatchId, const uint32_t wgId) const

M5_NODISCARD bool	sendToLds (GPUDynInstPtr gpuDynInst)
	send a general request to the LDS make sure to look at the return value here as your request might be NACK'd and returning false means that you have to have some backup plan More...

void	exitCallback ()

TokenManager *	getTokenManager ()

Port &	getPort (const std::string &if_name, PortID idx) override
	Get a port with a given name and index. More...

InstSeqNum	getAndIncSeqNum ()

void	updateInstStats (GPUDynInstPtr gpuDynInst)

Public Member Functions inherited from ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual const std::string	name () const

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbePoints ()
	Register probe points for this object. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

virtual void	startup ()
	startup() is the final initialization call before simulation. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue. More...

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from Stats::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	regStats ()
	Callback to set stat parameters. More...

virtual void	resetStats ()
	Callback to reset stats. More...

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (Stats::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block. More...

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from Clocked
void	updateClockPeriod ()
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Public Attributes
int	numVectorGlobalMemUnits

WaitClass	glbMemToVrfBus

WaitClass	vrfToGlobalMemPipeBus

WaitClass	vectorGlobalMemUnit

int	numVectorSharedMemUnits

WaitClass	locMemToVrfBus

WaitClass	vrfToLocalMemPipeBus

WaitClass	vectorSharedMemUnit

int	numScalarMemUnits

WaitClass	scalarMemToSrfBus

WaitClass	srfToScalarMemPipeBus

WaitClass	scalarMemUnit

int	numVectorALUs

std::vector< WaitClass >	vectorALUs

int	numScalarALUs

std::vector< WaitClass >	scalarALUs

int	vrfToCoalescerBusWidth

int	coalescerToVrfBusWidth

int	numCyclesPerStoreTransfer

int	numCyclesPerLoadTransfer

std::unordered_set< uint64_t >	pipeMap

RegisterManager *	registerManager

FetchStage	fetchStage

ScoreboardCheckStage	scoreboardCheckStage

ScheduleStage	scheduleStage

ExecStage	execStage

GlobalMemPipeline	globalMemoryPipe

LocalMemPipeline	localMemoryPipe

ScalarMemPipeline	scalarMemoryPipe

EventFunctionWrapper	tickEvent

std::vector< std::vector< Wavefront * > >	wfList

int	cu_id

std::vector< VectorRegisterFile * >	vrf

std::vector< ScalarRegisterFile * >	srf

int	simdWidth

int	spBypassPipeLength

int	dpBypassPipeLength

int	scalarPipeStages

int	operandNetworkLength

Cycles	issuePeriod

Cycles	vrf_gm_bus_latency

Cycles	srf_scm_bus_latency

Cycles	vrf_lm_bus_latency

std::vector< uint64_t >	lastExecCycle

std::vector< uint64_t >	instExecPerSimd

bool	perLaneTLB

int	prefetchDepth

int	prefetchStride

std::vector< Addr >	lastVaddrCU

std::vector< std::vector< Addr > >	lastVaddrSimd

std::vector< std::vector< std::vector< Addr > > >	lastVaddrWF

Enums::PrefetchType	prefetchType

EXEC_POLICY	exec_policy

bool	debugSegFault

Tick	idleCUTimeout

int	idleWfs

bool	functionalTLB

bool	localMemBarrier

bool	countPages

Shader *	shader

Tick	req_tick_latency

Tick	resp_tick_latency

std::vector< int >	numWfsToSched
	Number of WFs to schedule to each SIMD. More...

std::vector< int >	vectorRegsReserved

std::vector< int >	scalarRegsReserved

int	numVecRegsPerSimd

int	numScalarRegsPerSimd

std::map< Addr, int >	pagesTouched

pageDataStruct	pageAccesses

TokenManager *	memPortTokens

GMTokenPort	gmTokenPort

LDSPort	ldsPort
	The port to access the Local Data Store Can be connected to a LDS object. More...

std::vector< DataPort >	memPort
	The memory port for SIMD data accesses. More...

std::vector< DTLBPort >	tlbPort

ScalarDataPort	scalarDataPort

ScalarDTLBPort	scalarDTLBPort

SQCPort	sqcPort

ITLBPort	sqcTLBPort

int	activeWaves

ComputeUnit::ComputeUnitStats	stats

Public Attributes inherited from ClockedObject
PowerState *	powerState

Protected Attributes
RequestorID	_requestorId

LdsState &	lds

Protected Attributes inherited from SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Private Member Functions
WFBarrier &	barrierSlot (int bar_id)

int	getFreeBarrierId ()

Private Attributes
const int	_cacheLineSize

const int	_numBarrierSlots

int	cacheLineBits

InstSeqNum	globalSeqNum

int	wavefrontSize

ScoreboardCheckToSchedule	scoreboardCheckToSchedule
	TODO: Update these comments once the pipe stage interface has been fully refactored. More...

ScheduleToExecute	scheduleToExecute

std::vector< WFBarrier >	wfBarrierSlots
	The barrier slots for this CU. More...

std::unordered_set< int >	freeBarrierIds
	A set used to easily retrieve a free barrier ID. More...

std::unordered_map< GPUDynInstPtr, Tick >	headTailMap

Additional Inherited Members
Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	serializeAll (const std::string &cpt_dir)
	Serializes all the SimObjects. More...

static void	unserializeGlobals (CheckpointIn &cp)

Protected Member Functions inherited from Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...

Detailed Description

Definition at line 200 of file compute_unit.hh.

Member Typedef Documentation

◆ pageDataStruct

typedef std::unordered_map<Addr, std::pair<int, int> > ComputeUnit::pageDataStruct

Definition at line 481 of file compute_unit.hh.

◆ Params

typedef ComputeUnitParams ComputeUnit::Params

Definition at line 289 of file compute_unit.hh.

Constructor & Destructor Documentation

◆ ComputeUnit()

ComputeUnit::ComputeUnit ( const Params & p )

This check is necessary because std::bitset only provides conversion to unsigned long or unsigned long long via to_ulong() or to_ullong(). there are a few places in the code where to_ullong() is used, however if wavefrontSize is larger than a value the host can support then bitset will throw a runtime exception. We should remove all use of to_long() or to_ullong() so we can have wavefrontSize greater than 64b, however until that is done this assert is required.

Definition at line 62 of file compute_unit.cc.

References exec().

◆ ~ComputeUnit()

ComputeUnit::~ComputeUnit ( )

Definition at line 216 of file compute_unit.cc.

References ArmISA::i, ArmISA::j, lastVaddrCU, lastVaddrSimd, Shader::n_wf, numVectorALUs, shader, and wfList.

Member Function Documentation

◆ allAtBarrier()

bool ComputeUnit::allAtBarrier ( int bar_id )

Definition at line 652 of file compute_unit.cc.

References barrierSlot().

Referenced by ScoreboardCheckStage::ready().

◆ barrierSlot()

WFBarrier& ComputeUnit::barrierSlot ( int bar_id )

inlineprivate

Definition at line 417 of file compute_unit.hh.

References WFBarrier::InvalidID, and wfBarrierSlots.

Referenced by allAtBarrier(), decMaxBarrierCnt(), dispWorkgroup(), incNumAtBarrier(), maxBarrierCnt(), numAtBarrier(), numYetToReachBarrier(), releaseBarrier(), and resetBarrier().

◆ cacheLineSize()

int ComputeUnit::cacheLineSize ( ) const

inline

Definition at line 410 of file compute_unit.hh.

References _cacheLineSize.

Referenced by FetchUnit::init(), and FetchUnit::initiateFetch().

◆ decMaxBarrierCnt()

void ComputeUnit::decMaxBarrierCnt ( int bar_id )

Definition at line 687 of file compute_unit.cc.

References barrierSlot().

Referenced by Gcn3ISA::Inst_SOPP__S_ENDPGM::execute().

◆ deleteFromPipeMap()

void ComputeUnit::deleteFromPipeMap ( Wavefront * w )

Definition at line 505 of file compute_unit.cc.

References panic_if, pipeMap, and MipsISA::w.

Referenced by Wavefront::exec().

◆ dispWorkgroup()

void ComputeUnit::dispWorkgroup	(	HSAQueueEntry *	task,
		int	num_wfs_in_wg
	)

If this WG only has one WF it will not consume any barrier resources because it has no need of them.

Find a free barrier slot for this WG. Each WF in the WG will receive the same barrier ID.

Definition at line 418 of file compute_unit.cc.

References RegisterManager::allocateRegisters(), barrierSlot(), cu_id, HSAQueueEntry::dispatchId(), DPRINTF, fillKernelState(), getFreeBarrierId(), HSAQueueEntry::globalWgId(), ArmISA::i, WFBarrier::InvalidID, HSAQueueEntry::isInvDone(), ArmISA::j, lds, HSAQueueEntry::ldsSize(), Shader::n_wf, Clocked::nextCycle(), HSAQueueEntry::numScalarRegs(), numVectorALUs, HSAQueueEntry::numVectorRegs(), numWfsToSched, panic_if, registerManager, LdsState::reserveSpace(), Wavefront::S_STOPPED, EventManager::schedule(), Event::scheduled(), shader, startWavefront(), tickEvent, MipsISA::w, and wfList.

◆ doFlush()

void ComputeUnit::doFlush ( GPUDynInstPtr gpuDynInst )

trigger flush operation in the cu

gpuDynInst: inst passed to the request

Definition at line 400 of file compute_unit.cc.

References injectGlobalMemFence().

◆ doInvalidate()

void ComputeUnit::doInvalidate	(	RequestPtr	req,
		int	kernId
	)

trigger invalidate operation in the cu

req: request initialized in shader, carrying the invlidate flags

Definition at line 381 of file compute_unit.cc.

References getAndIncSeqNum(), and injectGlobalMemFence().

◆ doSmReturn()

template<typename c0 , typename c1 >

void ComputeUnit::doSmReturn ( GPUDynInstPtr gpuDynInst )

◆ dpBypassLength()

int ComputeUnit::dpBypassLength ( ) const

inline

Definition at line 389 of file compute_unit.hh.

References dpBypassPipeLength.

Referenced by VectorRegisterFile::waveExecuteInst().

◆ exec()

void ComputeUnit::exec ( )

Definition at line 717 of file compute_unit.cc.

References cu_id, DPRINTF, FetchStage::exec(), LocalMemPipeline::exec(), ScalarMemPipeline::exec(), GlobalMemPipeline::exec(), ScheduleStage::exec(), ExecStage::exec(), ScoreboardCheckStage::exec(), execStage, fetchStage, globalMemoryPipe, isDone(), localMemoryPipe, Clocked::nextCycle(), Shader::notifyCuSleep(), scalarMemoryPipe, EventManager::schedule(), scheduleStage, scoreboardCheckStage, shader, srf, stats, tickEvent, ComputeUnit::ComputeUnitStats::totalCycles, and vrf.

Referenced by ComputeUnit().

◆ exitCallback()

void ComputeUnit::exitCallback ( )

Definition at line 1910 of file compute_unit.cc.

References countPages, OutputDirectory::create(), SimObject::name(), pageAccesses, simout, and OutputStream::stream().

◆ fetch()

void ComputeUnit::fetch	(	PacketPtr	pkt,
		Wavefront *	wavefront
	)

◆ fillKernelState()

void ComputeUnit::fillKernelState	(	Wavefront *	w,
		HSAQueueEntry *	task
	)

Definition at line 293 of file compute_unit.cc.

References HSAQueueEntry::gridSize(), HSAQueueEntry::numScalarRegs(), HSAQueueEntry::numVectorRegs(), MipsISA::w, and HSAQueueEntry::wgSize().

Referenced by dispWorkgroup().

◆ firstMemUnit()

int ComputeUnit::firstMemUnit ( ) const

Definition at line 237 of file compute_unit.cc.

References numScalarALUs, and numVectorALUs.

Referenced by ScheduleStage::arbitrateVrfToLdsBus(), and ScheduleStage::exec().

◆ getAndIncSeqNum()

InstSeqNum ComputeUnit::getAndIncSeqNum ( )

inline

Definition at line 880 of file compute_unit.hh.

References globalSeqNum.

Referenced by doInvalidate().

◆ getCacheLineBits()

int ComputeUnit::getCacheLineBits ( ) const

inline

Definition at line 411 of file compute_unit.hh.

References cacheLineBits.

Referenced by FetchUnit::initiateFetch().

◆ getFreeBarrierId()

int ComputeUnit::getFreeBarrierId ( )

inlineprivate

Definition at line 424 of file compute_unit.hh.

References freeBarrierIds.

Referenced by dispWorkgroup().

◆ getLds()

LdsState& ComputeUnit::getLds ( ) const

inline

Definition at line 471 of file compute_unit.hh.

References lds.

Referenced by Gcn3ISA::Inst_SOPP__S_ENDPGM::execute().

◆ getPort()

Port& ComputeUnit::getPort	(	const std::string &	if_name,
		PortID	idx
	)

inlineoverridevirtual

Get a port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic port.

gem5 has a request and response port interface. All memory objects are connected together via ports. These ports provide a rigid interface between these memory objects. These ports implement three different memory system modes: timing, atomic, and functional. The most important mode is the timing mode and here timing mode is used for conducting cycle-level timing experiments. The other modes are only used in special circumstances and should not be used to conduct cycle-level timing experiments. The other modes are only used in special circumstances. These ports allow SimObjects to communicate with each other.

Parameters

if_name	Port name
idx	Index in the case of a VectorPort

Returns: A reference to the given port

Reimplemented from SimObject.

Definition at line 857 of file compute_unit.hh.

References SimObject::getPort(), gmTokenPort, ldsPort, memPort, scalarDataPort, scalarDTLBPort, sqcPort, sqcTLBPort, and tlbPort.

◆ getRefCounter()

int32_t ComputeUnit::getRefCounter	(	const uint32_t	dispatchId,
		const uint32_t	wgId
	)		const

Definition at line 1957 of file compute_unit.cc.

References LdsState::getRefCounter(), and lds.

◆ getTokenManager()

TokenManager* ComputeUnit::getTokenManager ( )

inline

Definition at line 836 of file compute_unit.hh.

References memPortTokens.

Referenced by GlobalMemPipeline::exec(), and Wavefront::exec().

◆ handleMemPacket()

void ComputeUnit::handleMemPacket	(	PacketPtr	pkt,
		int	memport_index
	)

◆ hasDispResources()

bool ComputeUnit::hasDispResources	(	HSAQueueEntry *	task,
		int &	num_wfs_in_wg
	)

◆ incNumAtBarrier()

void ComputeUnit::incNumAtBarrier ( int bar_id )

Definition at line 659 of file compute_unit.cc.

References barrierSlot().

Referenced by Gcn3ISA::Inst_SOPP__S_BARRIER::execute().

◆ init()

void ComputeUnit::init ( )

overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from SimObject.

Definition at line 750 of file compute_unit.cc.

References Clocked::clockPeriod(), execStage, fatal_if, fetchStage, glbMemToVrfBus, globalMemoryPipe, gmTokenPort, ArmISA::i, FetchStage::init(), GlobalMemPipeline::init(), ScheduleStage::init(), WaitClass::init(), ExecStage::init(), locMemToVrfBus, memPortTokens, numScalarALUs, numScalarMemUnits, numVectorALUs, numVectorGlobalMemUnits, numVectorSharedMemUnits, scalarALUs, scalarMemToSrfBus, scalarMemUnit, scalarRegsReserved, scheduleStage, TokenRequestPort::setTokenManager(), srfToScalarMemPipeBus, vectorALUs, vectorGlobalMemUnit, vectorRegsReserved, vectorSharedMemUnit, vrfToGlobalMemPipeBus, and vrfToLocalMemPipeBus.

◆ initiateFetch()

void ComputeUnit::initiateFetch ( Wavefront * wavefront )

◆ injectGlobalMemFence()

void ComputeUnit::injectGlobalMemFence	(	GPUDynInstPtr	gpuDynInst,
		bool	kernelMemSync,
		RequestPtr	req = `nullptr`
	)

Definition at line 1219 of file compute_unit.cc.

References cu_id, curTick(), DPRINTF, Request::FLUSH_L2, Shader::impl_kern_end_rel, Request::INV_L1, Request::KERNEL, memPort, MemCmd::MemSyncReq, Packet::pushSenderState(), Packet::req, req_tick_latency, requestorId(), EventManager::schedule(), and shader.

Referenced by doFlush(), and doInvalidate().

◆ insertInPipeMap()

void ComputeUnit::insertInPipeMap ( Wavefront * w )

Definition at line 496 of file compute_unit.cc.

References panic_if, pipeMap, and MipsISA::w.

Referenced by ScheduleStage::addToSchList().

◆ isDone()

bool ComputeUnit::isDone ( ) const

Definition at line 1927 of file compute_unit.cc.

References glbMemToVrfBus, globalMemoryPipe, ArmISA::i, GlobalMemPipeline::isGMReqFIFOWrRdy(), LocalMemPipeline::isLMReqFIFOWrRdy(), LocalMemPipeline::isLMRespFIFOWrRdy(), isVectorAluIdle(), localMemoryPipe, locMemToVrfBus, numVectorALUs, WaitClass::rdy(), scalarMemToSrfBus, srfToScalarMemPipeBus, vrfToGlobalMemPipeBus, and vrfToLocalMemPipeBus.

Referenced by exec().

◆ isVectorAluIdle()

bool ComputeUnit::isVectorAluIdle ( uint32_t simdId ) const

Definition at line 1964 of file compute_unit.cc.

References Shader::n_wf, numVectorALUs, Wavefront::S_STOPPED, shader, and wfList.

Referenced by isDone().

◆ lastMemUnit()

int ComputeUnit::lastMemUnit ( ) const

Definition at line 244 of file compute_unit.cc.

References numExeUnits().

Referenced by ScheduleStage::exec().

◆ loadBusLength()

int ComputeUnit::loadBusLength ( ) const

inline

Definition at line 392 of file compute_unit.hh.

References numCyclesPerLoadTransfer.

Referenced by LdsState::processPacket().

◆ mapWaveToGlobalMem()

int ComputeUnit::mapWaveToGlobalMem ( Wavefront * w ) const

Definition at line 269 of file compute_unit.cc.

References numScalarALUs, and numVectorALUs.

Referenced by Wavefront::init().

◆ mapWaveToLocalMem()

int ComputeUnit::mapWaveToLocalMem ( Wavefront * w ) const

Definition at line 277 of file compute_unit.cc.

References numScalarALUs, numVectorALUs, and numVectorGlobalMemUnits.

Referenced by Wavefront::init().

◆ mapWaveToScalarAlu()

int ComputeUnit::mapWaveToScalarAlu ( Wavefront * w ) const

Definition at line 251 of file compute_unit.cc.

References numScalarALUs, and MipsISA::w.

Referenced by Wavefront::init(), and mapWaveToScalarAluGlobalIdx().

◆ mapWaveToScalarAluGlobalIdx()

int ComputeUnit::mapWaveToScalarAluGlobalIdx ( Wavefront * w ) const

Definition at line 262 of file compute_unit.cc.

References mapWaveToScalarAlu(), numVectorALUs, and MipsISA::w.

Referenced by Wavefront::init().

◆ mapWaveToScalarMem()

int ComputeUnit::mapWaveToScalarMem ( Wavefront * w ) const

Definition at line 285 of file compute_unit.cc.

References numScalarALUs, numVectorALUs, numVectorGlobalMemUnits, and numVectorSharedMemUnits.

Referenced by Wavefront::init().

◆ maxBarrierCnt()

int ComputeUnit::maxBarrierCnt ( int bar_id )

Definition at line 673 of file compute_unit.cc.

References barrierSlot().

Referenced by Gcn3ISA::Inst_SOPP__S_ENDPGM::execute().

◆ numAtBarrier()

int ComputeUnit::numAtBarrier ( int bar_id )

Definition at line 666 of file compute_unit.cc.

References barrierSlot().

Referenced by Gcn3ISA::Inst_SOPP__S_BARRIER::execute().

◆ numBarrierSlots()

int ComputeUnit::numBarrierSlots ( ) const

inline

Definition at line 443 of file compute_unit.hh.

References _numBarrierSlots.

◆ numExeUnits()

int ComputeUnit::numExeUnits ( ) const

Definition at line 229 of file compute_unit.cc.

References numScalarALUs, numScalarMemUnits, numVectorALUs, numVectorGlobalMemUnits, and numVectorSharedMemUnits.

Referenced by ScheduleStage::checkRfOperandReadComplete(), ExecStage::dumpDispList(), ScheduleStage::exec(), ExecStage::exec(), ExecStage::ExecStageStats::ExecStageStats(), ScheduleStage::fillDispatchList(), ScheduleStage::init(), lastMemUnit(), ScoreboardCheckStage::mapWaveToExeUnit(), ScheduleStage::reserveResources(), ScheduleStage::scheduleRfDestOperands(), and ScheduleStage::ScheduleStage().

◆ numYetToReachBarrier()

int ComputeUnit::numYetToReachBarrier ( int bar_id )

Definition at line 645 of file compute_unit.cc.

References barrierSlot().

Referenced by Gcn3ISA::Inst_SOPP__S_BARRIER::execute().

◆ oprNetPipeLength()

int ComputeUnit::oprNetPipeLength ( ) const

inline

Definition at line 386 of file compute_unit.hh.

References operandNetworkLength.

◆ processFetchReturn()

void ComputeUnit::processFetchReturn ( PacketPtr pkt )

◆ processTimingPacket()

bool ComputeUnit::processTimingPacket ( PacketPtr pkt )

◆ releaseBarrier()

void ComputeUnit::releaseBarrier ( int bar_id )

Definition at line 694 of file compute_unit.cc.

References barrierSlot(), and freeBarrierIds.

Referenced by Gcn3ISA::Inst_SOPP__S_ENDPGM::execute().

◆ releaseWFsFromBarrier()

void ComputeUnit::releaseWFsFromBarrier ( int bar_id )

Definition at line 702 of file compute_unit.cc.

References Wavefront::barrierId(), Wavefront::getStatus(), ArmISA::i, ArmISA::j, Shader::n_wf, numVectorALUs, Wavefront::S_BARRIER, Wavefront::S_RUNNING, Wavefront::setStatus(), shader, and wfList.

Referenced by ScoreboardCheckStage::ready().

◆ requestorId()

RequestorID ComputeUnit::requestorId ( )

inline

Definition at line 459 of file compute_unit.hh.

References _requestorId.

Referenced by FetchUnit::initiateFetch(), and injectGlobalMemFence().

◆ resetBarrier()

void ComputeUnit::resetBarrier ( int bar_id )

Definition at line 680 of file compute_unit.cc.

References barrierSlot().

Referenced by ScoreboardCheckStage::ready().

◆ resetRegisterPool()

void ComputeUnit::resetRegisterPool ( )

Definition at line 408 of file compute_unit.cc.

References ArmISA::i, numScalarRegsPerSimd, numVecRegsPerSimd, numVectorALUs, registerManager, RegisterManager::srfPoolMgrs, and RegisterManager::vrfPoolMgrs.

◆ scalarPipeLength()

int ComputeUnit::scalarPipeLength ( ) const

inline

Definition at line 390 of file compute_unit.hh.

References scalarPipeStages.

Referenced by ScalarRegisterFile::waveExecuteInst().

◆ sendRequest()

void ComputeUnit::sendRequest	(	GPUDynInstPtr	gpuDynInst,
		PortID	index,
		PacketPtr	pkt
	)

Definition at line 1007 of file compute_unit.cc.

References Packet::cmd, cu_id, curTick(), Packet::dataStatic(), debugSegFault, DPRINTF, fatal, functionalTLB, Packet::getAddr(), ThreadContext::getProcessPtr(), Packet::getPtr(), Packet::getSize(), Shader::gpuTc, X86ISA::GpuTLB::TranslationState::hitLevel, ComputeUnit::ComputeUnitStats::hitsPerTLBLevel, MipsISA::index, Packet::isRead(), Packet::isWrite(), memPort, MemCmd::MemSyncReq, MipsISA::p, panic, perLaneTLB, BaseTLB::Read, Packet::req, req_tick_latency, X86ISA::GpuTLB::TranslationState::saved, EventManager::schedule(), Packet::senderState, shader, stats, Shader::timingSim, ComputeUnit::ComputeUnitStats::tlbCycles, X86ISA::GpuTLB::TranslationState::tlbEntry, tlbPort, ComputeUnit::ComputeUnitStats::tlbRequests, updatePageDivergenceDist(), MipsISA::vaddr, and BaseTLB::Write.

◆ sendScalarRequest()

void ComputeUnit::sendScalarRequest	(	GPUDynInstPtr	gpuDynInst,
		PacketPtr	pkt
	)

Definition at line 1192 of file compute_unit.cc.

References DPRINTF, Shader::gpuTc, Packet::isRead(), ComputeUnit::ScalarDTLBPort::isStalled(), Packet::isWrite(), BaseTLB::Read, Packet::req, ComputeUnit::ScalarDTLBPort::retries, scalarDTLBPort, Packet::senderState, RequestPort::sendTimingReq(), shader, ComputeUnit::ScalarDTLBPort::stallPort(), and BaseTLB::Write.

◆ sendToLds()

bool ComputeUnit::sendToLds ( GPUDynInstPtr gpuDynInst )

send a general request to the LDS make sure to look at the return value here as your request might be NACK'd and returning false means that you have to have some backup plan

Definition at line 1983 of file compute_unit.cc.

References ldsPort, MemCmd::ReadReq, Packet::senderState, and ComputeUnit::LDSPort::sendTimingReq().

Referenced by LocalMemPipeline::exec().

◆ simdUnitWidth()

int ComputeUnit::simdUnitWidth ( ) const

inline

Definition at line 387 of file compute_unit.hh.

References simdWidth.

◆ spBypassLength()

int ComputeUnit::spBypassLength ( ) const

inline

Definition at line 388 of file compute_unit.hh.

References spBypassPipeLength.

◆ startWavefront()

void ComputeUnit::startWavefront	(	Wavefront *	w,
		int	waveId,
		LdsChunk *	ldsChunk,
		HSAQueueEntry *	task,
		int	bar_id,
		bool	fetchContext = `false`
	)

Definition at line 307 of file compute_unit.cc.

References activeWaves, HSAQueueEntry::codeAddr(), cu_id, HSAQueueEntry::dispatchId(), DPRINTF, HSAQueueEntry::globalWgId(), LdsState::increaseRefCounter(), WFBarrier::InvalidID, MipsISA::k, lds, HSAQueueEntry::numWg(), Stats::DistBase< Derived, Stor >::sample(), stats, MipsISA::w, ComputeUnit::ComputeUnitStats::waveLevelParallelism, and wfSize().

Referenced by dispWorkgroup().

◆ storeBusLength()

int ComputeUnit::storeBusLength ( ) const

inline

Definition at line 391 of file compute_unit.hh.

References numCyclesPerStoreTransfer.

Referenced by LdsState::processPacket().

◆ updateInstStats()

void ComputeUnit::updateInstStats ( GPUDynInstPtr gpuDynInst )

this case can occur for flat mem insts who execute with EXEC = 0

Definition at line 1793 of file compute_unit.cc.

Referenced by Wavefront::exec().

◆ updatePageDivergenceDist()

void ComputeUnit::updatePageDivergenceDist ( Addr addr )

Definition at line 1899 of file compute_unit.cc.

References X86ISA::addr, X86ISA::PageBytes, pagesTouched, and roundDown().

Referenced by sendRequest().

◆ wfSize()

int ComputeUnit::wfSize ( ) const

inline

Definition at line 393 of file compute_unit.hh.

References wavefrontSize.

Referenced by ComputeUnit::ComputeUnitStats::ComputeUnitStats(), LdsState::countBankConflicts(), GPUDynInst::doApertureCheck(), GPUDynInst::GPUDynInst(), hasDispResources(), Wavefront::initRegState(), GPUDynInst::resolveFlatSegment(), and startWavefront().

Member Data Documentation

◆ _cacheLineSize

const int ComputeUnit::_cacheLineSize

private

Definition at line 883 of file compute_unit.hh.

Referenced by cacheLineSize().

◆ _numBarrierSlots

const int ComputeUnit::_numBarrierSlots

private

Definition at line 884 of file compute_unit.hh.

Referenced by numBarrierSlots().

◆ _requestorId

RequestorID ComputeUnit::_requestorId

protected

Definition at line 465 of file compute_unit.hh.

Referenced by requestorId().

◆ activeWaves

int ComputeUnit::activeWaves

Definition at line 940 of file compute_unit.hh.

Referenced by Gcn3ISA::Inst_SOPP__S_ENDPGM::execute(), and startWavefront().

◆ cacheLineBits

int ComputeUnit::cacheLineBits

private

Definition at line 885 of file compute_unit.hh.

Referenced by getCacheLineBits().

◆ coalescerToVrfBusWidth

int ComputeUnit::coalescerToVrfBusWidth

Definition at line 268 of file compute_unit.hh.

◆ countPages

bool ComputeUnit::countPages

Definition at line 350 of file compute_unit.hh.

Referenced by exitCallback().

◆ cu_id

◆ debugSegFault

bool ComputeUnit::debugSegFault

Definition at line 340 of file compute_unit.hh.

Referenced by sendRequest().

◆ dpBypassPipeLength

int ComputeUnit::dpBypassPipeLength

Definition at line 306 of file compute_unit.hh.

Referenced by dpBypassLength().

◆ exec_policy

EXEC_POLICY ComputeUnit::exec_policy

Definition at line 338 of file compute_unit.hh.

◆ execStage

ExecStage ComputeUnit::execStage

Definition at line 282 of file compute_unit.hh.

Referenced by exec(), and init().

◆ fetchStage

FetchStage ComputeUnit::fetchStage

Definition at line 279 of file compute_unit.hh.

Referenced by Wavefront::discardFetch(), exec(), Gcn3ISA::Inst_SOPP__S_ENDPGM::execute(), and init().

◆ freeBarrierIds

std::unordered_set<int> ComputeUnit::freeBarrierIds

private

A set used to easily retrieve a free barrier ID.

Definition at line 931 of file compute_unit.hh.

Referenced by getFreeBarrierId(), hasDispResources(), and releaseBarrier().

◆ functionalTLB

bool ComputeUnit::functionalTLB

Definition at line 344 of file compute_unit.hh.

Referenced by sendRequest().

◆ glbMemToVrfBus

WaitClass ComputeUnit::glbMemToVrfBus

Definition at line 220 of file compute_unit.hh.

Referenced by GlobalMemPipeline::exec(), init(), and isDone().

◆ globalMemoryPipe

GlobalMemPipeline ComputeUnit::globalMemoryPipe

Definition at line 283 of file compute_unit.hh.

Referenced by ScheduleStage::dispatchReady(), exec(), ScheduleStage::fillDispatchList(), init(), isDone(), ComputeUnit::DataPort::processMemRespEvent(), and ComputeUnit::DataPort::recvTimingResp().

◆ globalSeqNum

InstSeqNum ComputeUnit::globalSeqNum

private

Definition at line 886 of file compute_unit.hh.

Referenced by getAndIncSeqNum().

◆ gmTokenPort

GMTokenPort ComputeUnit::gmTokenPort

Definition at line 504 of file compute_unit.hh.

Referenced by getPort(), and init().

◆ headTailMap

std::unordered_map<GPUDynInstPtr, Tick> ComputeUnit::headTailMap

private

Definition at line 936 of file compute_unit.hh.

Referenced by ComputeUnit::DataPort::processMemRespEvent().

◆ idleCUTimeout

Tick ComputeUnit::idleCUTimeout

Definition at line 342 of file compute_unit.hh.

Referenced by Wavefront::setStatus().

◆ idleWfs

int ComputeUnit::idleWfs

Definition at line 343 of file compute_unit.hh.

Referenced by Wavefront::setStatus().

◆ instExecPerSimd

std::vector<uint64_t> ComputeUnit::instExecPerSimd

Definition at line 325 of file compute_unit.hh.

Referenced by Wavefront::exec().

◆ issuePeriod

Cycles ComputeUnit::issuePeriod

Definition at line 312 of file compute_unit.hh.

Referenced by Wavefront::exec().

◆ lastExecCycle

std::vector<uint64_t> ComputeUnit::lastExecCycle

Definition at line 322 of file compute_unit.hh.

Referenced by Wavefront::exec().

◆ lastVaddrCU

std::vector<Addr> ComputeUnit::lastVaddrCU

Definition at line 334 of file compute_unit.hh.

Referenced by ~ComputeUnit().

◆ lastVaddrSimd

std::vector<std::vector<Addr> > ComputeUnit::lastVaddrSimd

Definition at line 335 of file compute_unit.hh.

Referenced by ~ComputeUnit().

◆ lastVaddrWF

std::vector<std::vector<std::vector<Addr> > > ComputeUnit::lastVaddrWF

Definition at line 336 of file compute_unit.hh.

◆ lds

LdsState& ComputeUnit::lds

protected

Definition at line 467 of file compute_unit.hh.

Referenced by dispWorkgroup(), getLds(), getRefCounter(), hasDispResources(), and startWavefront().

◆ ldsPort

LDSPort ComputeUnit::ldsPort

The port to access the Local Data Store Can be connected to a LDS object.

Definition at line 833 of file compute_unit.hh.

Referenced by getPort(), and sendToLds().

◆ localMemBarrier

bool ComputeUnit::localMemBarrier

Definition at line 345 of file compute_unit.hh.

◆ localMemoryPipe

LocalMemPipeline ComputeUnit::localMemoryPipe

Definition at line 284 of file compute_unit.hh.

Referenced by ScheduleStage::dispatchReady(), exec(), and isDone().

◆ locMemToVrfBus

WaitClass ComputeUnit::locMemToVrfBus

Definition at line 228 of file compute_unit.hh.

Referenced by LocalMemPipeline::exec(), init(), and isDone().

◆ memPort

std::vector<DataPort> ComputeUnit::memPort

The memory port for SIMD data accesses.

Can be connected to PhysMem for Ruby for timing simulations

Definition at line 844 of file compute_unit.hh.

Referenced by getPort(), injectGlobalMemFence(), ComputeUnit::DataPort::recvTimingResp(), and sendRequest().

◆ memPortTokens

TokenManager* ComputeUnit::memPortTokens

Definition at line 503 of file compute_unit.hh.

Referenced by getTokenManager(), and init().

◆ numCyclesPerLoadTransfer

int ComputeUnit::numCyclesPerLoadTransfer

Definition at line 270 of file compute_unit.hh.

Referenced by loadBusLength().

◆ numCyclesPerStoreTransfer

int ComputeUnit::numCyclesPerStoreTransfer

Definition at line 269 of file compute_unit.hh.

Referenced by storeBusLength().

◆ numScalarALUs

int ComputeUnit::numScalarALUs

Definition at line 247 of file compute_unit.hh.

Referenced by ExecStage::ExecStageStats::ExecStageStats(), firstMemUnit(), init(), mapWaveToGlobalMem(), mapWaveToLocalMem(), mapWaveToScalarAlu(), mapWaveToScalarMem(), and numExeUnits().

◆ numScalarMemUnits

int ComputeUnit::numScalarMemUnits

Definition at line 234 of file compute_unit.hh.

Referenced by init(), and numExeUnits().

◆ numScalarRegsPerSimd

int ComputeUnit::numScalarRegsPerSimd

Definition at line 372 of file compute_unit.hh.

Referenced by StaticRegisterManagerPolicy::allocateRegisters(), hasDispResources(), and resetRegisterPool().

◆ numVecRegsPerSimd

int ComputeUnit::numVecRegsPerSimd

Definition at line 370 of file compute_unit.hh.

Referenced by StaticRegisterManagerPolicy::allocateRegisters(), hasDispResources(), and resetRegisterPool().

◆ numVectorALUs

int ComputeUnit::numVectorALUs

◆ numVectorGlobalMemUnits

int ComputeUnit::numVectorGlobalMemUnits

Definition at line 218 of file compute_unit.hh.

Referenced by ScheduleStage::arbitrateVrfToLdsBus(), ScheduleStage::init(), init(), mapWaveToLocalMem(), mapWaveToScalarMem(), and numExeUnits().

◆ numVectorSharedMemUnits

int ComputeUnit::numVectorSharedMemUnits

Definition at line 226 of file compute_unit.hh.

Referenced by ScheduleStage::init(), init(), mapWaveToScalarMem(), and numExeUnits().

◆ numWfsToSched

std::vector<int> ComputeUnit::numWfsToSched

Number of WFs to schedule to each SIMD.

This vector is populated by hasDispResources(), and consumed by the subsequent call to dispWorkgroup(), to schedule the specified number of WFs to the SIMD units. Entry I provides the number of WFs to schedule to SIMD I.

Definition at line 363 of file compute_unit.hh.

Referenced by dispWorkgroup(), and hasDispResources().

◆ operandNetworkLength

int ComputeUnit::operandNetworkLength

Definition at line 310 of file compute_unit.hh.

Referenced by oprNetPipeLength().

◆ pageAccesses

pageDataStruct ComputeUnit::pageAccesses

Definition at line 482 of file compute_unit.hh.

Referenced by exitCallback(), and GPUDynInst::updateStats().

◆ pagesTouched

std::map<Addr, int> ComputeUnit::pagesTouched

Definition at line 377 of file compute_unit.hh.

Referenced by updatePageDivergenceDist(), and GPUDynInst::updateStats().

◆ perLaneTLB

bool ComputeUnit::perLaneTLB

Definition at line 328 of file compute_unit.hh.

Referenced by sendRequest().

◆ pipeMap

std::unordered_set<uint64_t> ComputeUnit::pipeMap

Definition at line 275 of file compute_unit.hh.

Referenced by deleteFromPipeMap(), insertInPipeMap(), and Wavefront::nextInstr().

◆ prefetchDepth

int ComputeUnit::prefetchDepth

Definition at line 330 of file compute_unit.hh.

◆ prefetchStride

int ComputeUnit::prefetchStride

Definition at line 332 of file compute_unit.hh.

◆ prefetchType

Enums::PrefetchType ComputeUnit::prefetchType

Definition at line 337 of file compute_unit.hh.

◆ registerManager

RegisterManager* ComputeUnit::registerManager

Definition at line 277 of file compute_unit.hh.

Referenced by StaticRegisterManagerPolicy::allocateRegisters(), StaticRegisterManagerPolicy::canAllocateSgprs(), StaticRegisterManagerPolicy::canAllocateVgprs(), dispWorkgroup(), Gcn3ISA::Inst_SOPP__S_ENDPGM::execute(), Wavefront::freeRegisterFile(), hasDispResources(), Wavefront::initRegState(), VectorRegisterFile::operandsReady(), ScalarRegisterFile::operandsReady(), Gcn3ISA::VecOperand< DataType, Const, NumDwords >::read(), Gcn3ISA::ScalarOperand< DataType, Const, sizeof(DataType)/sizeof(VecElemU32) >::regIdx(), resetRegisterPool(), GPUDynInst::resolveFlatSegment(), VectorRegisterFile::scheduleWriteOperands(), ScalarRegisterFile::scheduleWriteOperands(), VectorRegisterFile::scheduleWriteOperandsFromLoad(), ScalarRegisterFile::scheduleWriteOperandsFromLoad(), VectorRegisterFile::waveExecuteInst(), ScalarRegisterFile::waveExecuteInst(), and Gcn3ISA::VecOperand< DataType, Const, NumDwords >::write().

◆ req_tick_latency

Tick ComputeUnit::req_tick_latency

Definition at line 354 of file compute_unit.hh.

Referenced by injectGlobalMemFence(), and sendRequest().

◆ resp_tick_latency

Tick ComputeUnit::resp_tick_latency

Definition at line 355 of file compute_unit.hh.

Referenced by ComputeUnit::DataPort::recvTimingResp().

◆ scalarALUs

std::vector<WaitClass> ComputeUnit::scalarALUs

Definition at line 248 of file compute_unit.hh.

Referenced by ScheduleStage::dispatchReady(), Wavefront::exec(), and init().

◆ scalarDataPort

ScalarDataPort ComputeUnit::scalarDataPort

Definition at line 848 of file compute_unit.hh.

Referenced by getPort(), and ComputeUnit::ScalarDataPort::MemReqEvent::process().

◆ scalarDTLBPort

ScalarDTLBPort ComputeUnit::scalarDTLBPort

Definition at line 850 of file compute_unit.hh.

Referenced by getPort(), and sendScalarRequest().

◆ scalarMemoryPipe

ScalarMemPipeline ComputeUnit::scalarMemoryPipe

Definition at line 285 of file compute_unit.hh.

Referenced by ScheduleStage::dispatchReady(), and exec().

◆ scalarMemToSrfBus

WaitClass ComputeUnit::scalarMemToSrfBus

Definition at line 236 of file compute_unit.hh.

Referenced by ScalarMemPipeline::exec(), init(), and isDone().

◆ scalarMemUnit

WaitClass ComputeUnit::scalarMemUnit

Definition at line 240 of file compute_unit.hh.

Referenced by ScheduleStage::checkMemResources(), ScalarMemPipeline::exec(), Wavefront::exec(), and init().

◆ scalarPipeStages

int ComputeUnit::scalarPipeStages

Definition at line 308 of file compute_unit.hh.

Referenced by scalarPipeLength().

◆ scalarRegsReserved

std::vector<int> ComputeUnit::scalarRegsReserved

Definition at line 368 of file compute_unit.hh.

Referenced by StaticRegisterManagerPolicy::allocateRegisters(), and init().

◆ scheduleStage

ScheduleStage ComputeUnit::scheduleStage

Definition at line 281 of file compute_unit.hh.

Referenced by ExecStage::exec(), exec(), and init().

◆ scheduleToExecute

ScheduleToExecute ComputeUnit::scheduleToExecute

private

Definition at line 922 of file compute_unit.hh.

◆ scoreboardCheckStage

ScoreboardCheckStage ComputeUnit::scoreboardCheckStage

Definition at line 280 of file compute_unit.hh.

Referenced by exec().

◆ scoreboardCheckToSchedule

ScoreboardCheckToSchedule ComputeUnit::scoreboardCheckToSchedule

private

TODO: Update these comments once the pipe stage interface has been fully refactored.

Pipeline stage interfaces.

Buffers used to communicate between various pipeline stages List of waves which will be dispatched to each execution resource. An EXREADY implies dispatch list is non-empty and execution unit has something to execute this cycle. Currently, the dispatch list of an execution resource can hold only one wave because an execution resource can execute only one wave in a cycle. dispatchList is used to communicate between schedule and exec stage

At a high level, the following intra-/inter-stage communication occurs: SCB to SCH: readyList provides per exec resource list of waves that passed dependency and readiness checks. If selected by scheduler, attempt to add wave to schList conditional on RF support. SCH: schList holds waves that are gathering operands or waiting for execution resource availability. Once ready, waves are placed on the dispatchList as candidates for execution. A wave may spend multiple cycles in SCH stage, on the schList due to RF access conflicts or execution resource contention. SCH to EX: dispatchList holds waves that are ready to be executed. LM/FLAT arbitration may remove an LM wave and place it back on the schList. RF model may also force a wave back to the schList if using the detailed model.

Definition at line 921 of file compute_unit.hh.

◆ shader

◆ simdWidth

int ComputeUnit::simdWidth

Definition at line 300 of file compute_unit.hh.

Referenced by simdUnitWidth().

◆ spBypassPipeLength

int ComputeUnit::spBypassPipeLength

Definition at line 303 of file compute_unit.hh.

Referenced by spBypassLength().

◆ sqcPort

SQCPort ComputeUnit::sqcPort

Definition at line 852 of file compute_unit.hh.

Referenced by FetchUnit::fetch(), and getPort().

◆ sqcTLBPort

ITLBPort ComputeUnit::sqcTLBPort

Definition at line 854 of file compute_unit.hh.

Referenced by getPort(), and FetchUnit::initiateFetch().

◆ srf

std::vector<ScalarRegisterFile*> ComputeUnit::srf

Definition at line 296 of file compute_unit.hh.

Referenced by ScheduleStage::addToSchList(), ScheduleStage::checkRfOperandReadComplete(), Wavefront::exec(), exec(), Wavefront::initRegState(), Gcn3ISA::ScalarOperand< DataType, Const, sizeof(DataType)/sizeof(VecElemU32) >::read(), ScoreboardCheckStage::ready(), ScheduleStage::reserveResources(), GPUDynInst::resolveFlatSegment(), ScheduleStage::schedRfWrites(), RegisterManager::setParent(), and Gcn3ISA::ScalarOperand< DataType, Const, sizeof(DataType)/sizeof(VecElemU32) >::write().

◆ srf_scm_bus_latency

Cycles ComputeUnit::srf_scm_bus_latency

Definition at line 317 of file compute_unit.hh.

Referenced by Wavefront::exec().

◆ srfToScalarMemPipeBus

WaitClass ComputeUnit::srfToScalarMemPipeBus

Definition at line 238 of file compute_unit.hh.

Referenced by ScheduleStage::checkMemResources(), Wavefront::exec(), init(), and isDone().

◆ stats

ComputeUnit::ComputeUnitStats ComputeUnit::stats

Referenced by Wavefront::exec(), exec(), AtomicOpCAS< T >::execute(), Gcn3ISA::Inst_SOPP__S_ENDPGM::execute(), hasDispResources(), ComputeUnit::DataPort::processMemRespEvent(), LdsState::processPacket(), sendRequest(), startWavefront(), updateInstStats(), and GPUDynInst::updateStats().

◆ tickEvent

EventFunctionWrapper ComputeUnit::tickEvent

Definition at line 287 of file compute_unit.hh.

Referenced by dispWorkgroup(), and exec().

◆ tlbPort

std::vector<DTLBPort> ComputeUnit::tlbPort

Definition at line 846 of file compute_unit.hh.

Referenced by getPort(), and sendRequest().

◆ vectorALUs

std::vector<WaitClass> ComputeUnit::vectorALUs

Definition at line 244 of file compute_unit.hh.

Referenced by ScheduleStage::dispatchReady(), Wavefront::exec(), and init().

◆ vectorGlobalMemUnit

WaitClass ComputeUnit::vectorGlobalMemUnit

Definition at line 224 of file compute_unit.hh.

Referenced by ScheduleStage::checkMemResources(), GlobalMemPipeline::exec(), Wavefront::exec(), and init().

◆ vectorRegsReserved

std::vector<int> ComputeUnit::vectorRegsReserved

Definition at line 366 of file compute_unit.hh.

Referenced by StaticRegisterManagerPolicy::allocateRegisters(), and init().

◆ vectorSharedMemUnit

WaitClass ComputeUnit::vectorSharedMemUnit

Definition at line 232 of file compute_unit.hh.

Referenced by ScheduleStage::checkMemResources(), LocalMemPipeline::exec(), Wavefront::exec(), and init().

◆ vrf

std::vector<VectorRegisterFile*> ComputeUnit::vrf

Definition at line 294 of file compute_unit.hh.

◆ vrf_gm_bus_latency

Cycles ComputeUnit::vrf_gm_bus_latency

Definition at line 315 of file compute_unit.hh.

Referenced by Wavefront::exec().

◆ vrf_lm_bus_latency

Cycles ComputeUnit::vrf_lm_bus_latency

Definition at line 319 of file compute_unit.hh.

Referenced by Wavefront::exec().

◆ vrfToCoalescerBusWidth

int ComputeUnit::vrfToCoalescerBusWidth

Definition at line 267 of file compute_unit.hh.

◆ vrfToGlobalMemPipeBus

WaitClass ComputeUnit::vrfToGlobalMemPipeBus

Definition at line 222 of file compute_unit.hh.

Referenced by ScheduleStage::checkMemResources(), Wavefront::exec(), init(), and isDone().

◆ vrfToLocalMemPipeBus

WaitClass ComputeUnit::vrfToLocalMemPipeBus

Definition at line 230 of file compute_unit.hh.

Referenced by ScheduleStage::checkMemResources(), Wavefront::exec(), init(), and isDone().

◆ wavefrontSize

int ComputeUnit::wavefrontSize

private

Definition at line 887 of file compute_unit.hh.

Referenced by wfSize().

◆ wfBarrierSlots

std::vector<WFBarrier> ComputeUnit::wfBarrierSlots

private

The barrier slots for this CU.

Definition at line 927 of file compute_unit.hh.

Referenced by barrierSlot().

◆ wfList

std::vector<std::vector<Wavefront*> > ComputeUnit::wfList

Definition at line 290 of file compute_unit.hh.

Referenced by dispWorkgroup(), ScoreboardCheckStage::exec(), hasDispResources(), FetchStage::init(), isVectorAluIdle(), ComputeUnit::DataPort::recvTimingResp(), releaseWFsFromBarrier(), and ~ComputeUnit().

The documentation for this class was generated from the following files:

gpu-compute/compute_unit.hh
gpu-compute/compute_unit.cc

Classes

Public Types

Public Member Functions

Public Attributes

Protected Attributes

Private Member Functions

Private Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ pageDataStruct

◆ Params

Constructor & Destructor Documentation

◆ ComputeUnit()

◆ ~ComputeUnit()

Member Function Documentation

◆ allAtBarrier()

◆ barrierSlot()

◆ cacheLineSize()

◆ decMaxBarrierCnt()

◆ deleteFromPipeMap()

◆ dispWorkgroup()

◆ doFlush()

◆ doInvalidate()

◆ doSmReturn()

◆ dpBypassLength()

◆ exec()

◆ exitCallback()

◆ fetch()

◆ fillKernelState()

◆ firstMemUnit()

◆ getAndIncSeqNum()

◆ getCacheLineBits()

◆ getFreeBarrierId()

◆ getLds()

◆ getPort()

◆ getRefCounter()

◆ getTokenManager()

◆ handleMemPacket()

◆ hasDispResources()

◆ incNumAtBarrier()

◆ init()

◆ initiateFetch()

◆ injectGlobalMemFence()

◆ insertInPipeMap()

◆ isDone()

◆ isVectorAluIdle()

◆ lastMemUnit()

◆ loadBusLength()

◆ mapWaveToGlobalMem()

◆ mapWaveToLocalMem()

◆ mapWaveToScalarAlu()

◆ mapWaveToScalarAluGlobalIdx()

◆ mapWaveToScalarMem()

◆ maxBarrierCnt()

◆ numAtBarrier()

◆ numBarrierSlots()

◆ numExeUnits()

◆ numYetToReachBarrier()

◆ oprNetPipeLength()

◆ processFetchReturn()

◆ processTimingPacket()

◆ releaseBarrier()

◆ releaseWFsFromBarrier()

◆ requestorId()

◆ resetBarrier()

◆ resetRegisterPool()

◆ scalarPipeLength()

◆ sendRequest()

◆ sendScalarRequest()

◆ sendToLds()

◆ simdUnitWidth()

◆ spBypassLength()

◆ startWavefront()

◆ storeBusLength()

◆ updateInstStats()

◆ updatePageDivergenceDist()

◆ wfSize()

Member Data Documentation

◆ _cacheLineSize