gem5::Gcn3ISA::GPUISA Class Reference

#include <gpu_isa.hh>

Public Member Functions
	GPUISA (Wavefront &wf)
template<typename T >
T	readConstVal (int opIdx) const
ScalarRegU32	readMiscReg (int opIdx) const
void	writeMiscReg (int opIdx, ScalarRegU32 operandVal)
bool	hasScalarUnit () const
void	advancePC (GPUDynInstPtr gpuDynInst)

Private Member Functions
ScalarRegU32	readPosConstReg (int opIdx) const
ScalarRegI32	readNegConstReg (int opIdx) const

Private Attributes
Wavefront &	wavefront
StatusReg	statusReg
ScalarRegU32	m0

Static Private Attributes
static const std::array< const ScalarRegU32, NumPosConstRegs >	posConstRegs
static const std::array< const ScalarRegI32, NumNegConstRegs >	negConstRegs

Detailed Description

Definition at line 52 of file gpu_isa.hh.

Constructor & Destructor Documentation

GPUISA()

gem5::Gcn3ISA::GPUISA::GPUISA

(

Wavefront &

wf

)

Definition at line 46 of file isa.cc.

Member Function Documentation

advancePC()

void gem5::Gcn3ISA::GPUISA::advancePC

(

GPUDynInstPtr

gpuDynInst

)

Definition at line 85 of file isa.cc.

References gem5::Wavefront::pc(), and wavefront.

hasScalarUnit()

bool gem5::Gcn3ISA::GPUISA::hasScalarUnit ( ) const

inline

Definition at line 77 of file gpu_isa.hh.

readConstVal()

template<typename T >

T gem5::Gcn3ISA::GPUISA::readConstVal ( int  opIdx ) const

inline

Definition at line 58 of file gpu_isa.hh.

References gem5::Gcn3ISA::isNegConstVal(), gem5::Gcn3ISA::isPosConstVal(), panic_if, readNegConstReg(), readPosConstReg(), and gem5::X86ISA::val.

readMiscReg()

ScalarRegU32 gem5::Gcn3ISA::GPUISA::readMiscReg

(

int

opIdx

)

const

Definition at line 51 of file isa.cc.

References fatal, m0, gem5::Gcn3ISA::REG_M0, gem5::Gcn3ISA::REG_SCC, gem5::Gcn3ISA::REG_ZERO, gem5::Gcn3ISA::StatusReg::SCC, and statusReg.

readNegConstReg()

ScalarRegI32 gem5::Gcn3ISA::GPUISA::readNegConstReg ( int  opIdx ) const

inlineprivate

Definition at line 86 of file gpu_isa.hh.

References negConstRegs, and gem5::Gcn3ISA::REG_INT_CONST_NEG_MIN.

Referenced by readConstVal().

readPosConstReg()

ScalarRegU32 gem5::Gcn3ISA::GPUISA::readPosConstReg ( int  opIdx ) const

inlineprivate

Definition at line 81 of file gpu_isa.hh.

References posConstRegs, and gem5::Gcn3ISA::REG_INT_CONST_POS_MIN.

Referenced by readConstVal().

writeMiscReg()

void gem5::Gcn3ISA::GPUISA::writeMiscReg	(	int	opIdx,
		ScalarRegU32	operandVal
	)

Definition at line 68 of file isa.cc.

References fatal, m0, gem5::Gcn3ISA::REG_M0, gem5::Gcn3ISA::REG_SCC, gem5::Gcn3ISA::StatusReg::SCC, and statusReg.

Member Data Documentation

m0

ScalarRegU32 gem5::Gcn3ISA::GPUISA::m0

private

Definition at line 102 of file gpu_isa.hh.

Referenced by readMiscReg(), and writeMiscReg().

negConstRegs

const std::array< const ScalarRegI32, NumNegConstRegs > gem5::Gcn3ISA::GPUISA::negConstRegs

staticprivate

Initial value:

= { {
            -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15,
            -16
        } }

Definition at line 94 of file gpu_isa.hh.

Referenced by readNegConstReg().

posConstRegs

const std::array< const ScalarRegU32, NumPosConstRegs > gem5::Gcn3ISA::GPUISA::posConstRegs

staticprivate

Initial value:

= { {
            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
            20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
            37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
            54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
        } }

Definition at line 92 of file gpu_isa.hh.

Referenced by readPosConstReg().

statusReg

StatusReg gem5::Gcn3ISA::GPUISA::statusReg

private

Definition at line 100 of file gpu_isa.hh.

Referenced by readMiscReg(), and writeMiscReg().

wavefront

Wavefront& gem5::Gcn3ISA::GPUISA::wavefront

private

Definition at line 97 of file gpu_isa.hh.

Referenced by advancePC().

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The documentation for this class was generated from the following files:

• arch/amdgpu/gcn3/gpu_isa.hh
• arch/amdgpu/gcn3/isa.cc