exec_context.hh

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#ifndef __CPU_EXEC_CONTEXT_HH__
#define __CPU_EXEC_CONTEXT_HH__
 
#include "arch/vecregs.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/reg_class.hh"
#include "cpu/static_inst_fwd.hh"
#include "cpu/translation.hh"
#include "mem/request.hh"
 
namespace gem5
{
 
class ExecContext
{
  public:
    virtual RegVal readIntRegOperand(const StaticInst *si, int idx) = 0;
 
    virtual void setIntRegOperand(const StaticInst *si,
                                  int idx, RegVal val) = 0;
 
    virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx) = 0;
 
    virtual void setFloatRegOperandBits(const StaticInst *si,
                                        int idx, RegVal val) = 0;
 
    virtual const TheISA::VecRegContainer& readVecRegOperand(
            const StaticInst *si, int idx) const = 0;
 
    virtual TheISA::VecRegContainer& getWritableVecRegOperand(
            const StaticInst *si, int idx) = 0;
 
    virtual void setVecRegOperand(const StaticInst *si, int idx,
            const TheISA::VecRegContainer& val) = 0;
    virtual TheISA::VecElem readVecElemOperand(
            const StaticInst *si, int idx) const = 0;
 
    virtual void setVecElemOperand(
            const StaticInst *si, int idx, const TheISA::VecElem val) = 0;
    virtual const TheISA::VecPredRegContainer& readVecPredRegOperand(
            const StaticInst *si, int idx) const = 0;
 
    virtual TheISA::VecPredRegContainer& getWritableVecPredRegOperand(
            const StaticInst *si, int idx) = 0;
 
    virtual void setVecPredRegOperand(
            const StaticInst *si, int idx,
            const TheISA::VecPredRegContainer& val) = 0;
    virtual RegVal readCCRegOperand(const StaticInst *si, int idx) = 0;
    virtual void setCCRegOperand(
            const StaticInst *si, int idx, RegVal val) = 0;
    virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
    virtual void setMiscRegOperand(const StaticInst *si,
                                   int idx, RegVal val) = 0;
 
    virtual RegVal readMiscReg(int misc_reg) = 0;
 
    virtual void setMiscReg(int misc_reg, RegVal val) = 0;
 
    virtual TheISA::PCState pcState() const = 0;
    virtual void pcState(const TheISA::PCState &val) = 0;
    virtual Fault
    readMem(Addr addr, uint8_t *data, unsigned int size,
            Request::Flags flags, const std::vector<bool>& byte_enable)
    {
        panic("ExecContext::readMem() should be overridden\n");
    }
 
    virtual Fault
    initiateMemRead(Addr addr, unsigned int size,
            Request::Flags flags, const std::vector<bool>& byte_enable)
    {
        panic("ExecContext::initiateMemRead() should be overridden\n");
    }
 
    virtual Fault initiateHtmCmd(Request::Flags flags) = 0;
    virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
                           Request::Flags flags, uint64_t *res,
                           const std::vector<bool>& byte_enable) = 0;
 
    virtual Fault
    amoMem(Addr addr, uint8_t *data, unsigned int size,
            Request::Flags flags, AtomicOpFunctorPtr amo_op)
    {
        panic("ExecContext::amoMem() should be overridden\n");
    }
 
    virtual Fault
    initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags,
            AtomicOpFunctorPtr amo_op)
    {
        panic("ExecContext::initiateMemAMO() should be overridden\n");
    }
 
    virtual void setStCondFailures(unsigned int sc_failures) = 0;
 
    virtual unsigned int readStCondFailures() const = 0;
 
    virtual ThreadContext *tcBase() const = 0;
 
    virtual bool readPredicate() const = 0;
    virtual void setPredicate(bool val) = 0;
    virtual bool readMemAccPredicate() const = 0;
    virtual void setMemAccPredicate(bool val) = 0;
 
    // hardware transactional memory
    virtual uint64_t newHtmTransactionUid() const = 0;
    virtual uint64_t getHtmTransactionUid() const = 0;
    virtual bool inHtmTransactionalState() const = 0;
    virtual uint64_t getHtmTransactionalDepth() const = 0;
 
    virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
    virtual void armMonitor(Addr address) = 0;
    virtual bool mwait(PacketPtr pkt) = 0;
    virtual void mwaitAtomic(ThreadContext *tc) = 0;
    virtual AddressMonitor *getAddrMonitor() = 0;
 
};
 
} // namespace gem5
 
#endif // __CPU_EXEC_CONTEXT_HH__