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gpu_exec_context.cc
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33 
35 #include "gpu-compute/wavefront.hh"
36 
37 namespace gem5
38 {
39 
41  : cu(_cu), wf(_wf), gpuISA(_wf ? &_wf->gpuISA() : nullptr)
42 {
43 }
44 
47 {
48  return cu;
49 }
50 
51 Wavefront*
53 {
54  return wf;
55 }
56 
57 RegVal
59 {
60  assert(gpuISA);
61  return gpuISA->readMiscReg(opIdx);
62 }
63 
64 void
66 {
67  assert(gpuISA);
68  gpuISA->writeMiscReg(opIdx, val);
69 }
70 
71 } // namespace gem5
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::GPUExecContext::writeMiscReg
void writeMiscReg(int opIdx, RegVal operandVal)
Definition: gpu_exec_context.cc:65
gem5::Wavefront
Definition: wavefront.hh:62
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::GPUExecContext::wf
Wavefront * wf
Definition: gpu_exec_context.hh:65
gem5::GPUExecContext::gpuISA
TheGpuISA::GPUISA * gpuISA
Definition: gpu_exec_context.hh:66
wavefront.hh
gem5::GPUExecContext::computeUnit
ComputeUnit * computeUnit()
Definition: gpu_exec_context.cc:46
gem5::ComputeUnit
Definition: compute_unit.hh:203
gem5::GPUExecContext::GPUExecContext
GPUExecContext(ComputeUnit *_cu, Wavefront *_wf)
Definition: gpu_exec_context.cc:40
gem5::GPUExecContext::readMiscReg
RegVal readMiscReg(int opIdx) const
Definition: gpu_exec_context.cc:58
gem5::GPUExecContext::wavefront
Wavefront * wavefront()
Definition: gpu_exec_context.cc:52
gpu_exec_context.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::GPUExecContext::cu
ComputeUnit * cu
Definition: gpu_exec_context.hh:64

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