pipe_data.hh

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/*
 * Copyright (c) 2013-2014 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __CPU_MINOR_PIPE_DATA_HH__
#define __CPU_MINOR_PIPE_DATA_HH__
 
#include "cpu/minor/buffers.hh"
#include "cpu/minor/dyn_inst.hh"
#include "cpu/base.hh"
 
namespace gem5
{
 
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
 
class BranchData /* : public ReportIF, public BubbleIF */
{
  public:
    enum Reason
    {
        /* *** No change of stream (information to branch prediction) */
 
        /* Don't branch at all (bubble) */
        NoBranch,
        /* Don't branch, but here's the details of a correct prediction
         * that was executed */
        CorrectlyPredictedBranch,
 
        /* *** Change of stream */
 
        /* Take an unpredicted branch */
        UnpredictedBranch,
        /* Take a branch on branch prediction data (from Fetch2) */
        BranchPrediction,
        /* Prediction of wrong target PC */
        BadlyPredictedBranchTarget,
        /* Bad branch prediction (didn't actually branch).  Need to branch
         *  back to correct stream.  If the target is wrong, use
         *  BadlyPredictedBranchTarget */
        BadlyPredictedBranch,
        /* Suspend fetching for this thread (inst->id.threadId).
         * This will be woken up by another stream changing branch so
         * count it as stream changing itself and expect pc to be the PC
         * of the next instruction */
        SuspendThread,
        /* Branch from an interrupt (no instruction) */
        Interrupt,
        /* Stop fetching in anticipation of of draining */
        HaltFetch
    };
 
    static bool isStreamChange(const BranchData::Reason reason);
 
    static bool isBranch(const BranchData::Reason reason);
 
  public:
    Reason reason;
 
    ThreadID threadId;
 
    InstSeqNum newStreamSeqNum;
    InstSeqNum newPredictionSeqNum;
 
    TheISA::PCState target;
 
    MinorDynInstPtr inst;
 
  public:
    BranchData() :
        reason(NoBranch), threadId(InvalidThreadID), newStreamSeqNum(0),
        newPredictionSeqNum(0), target(TheISA::PCState(0)),
        inst(MinorDynInst::bubble())
    { }
 
    BranchData(
        Reason reason_,
        ThreadID thread_id,
        InstSeqNum new_stream_seq_num,
        InstSeqNum new_prediction_seq_num,
        TheISA::PCState target,
        MinorDynInstPtr inst_) :
        reason(reason_),
        threadId(thread_id),
        newStreamSeqNum(new_stream_seq_num),
        newPredictionSeqNum(new_prediction_seq_num),
        target(target),
        inst(inst_)
    { }
 
    static BranchData bubble() { return BranchData(); }
    bool isBubble() const { return reason == NoBranch; }
 
    bool isStreamChange() const { return isStreamChange(reason); }
 
    bool isBranch() const { return isBranch(reason); }
 
    void reportData(std::ostream &os) const;
};
 
std::ostream &operator <<(std::ostream &os, BranchData::Reason reason);
 
std::ostream &operator <<(std::ostream &os, const BranchData &branch);
 
class ForwardLineData /* : public ReportIF, public BubbleIF */
{
  private:
    bool bubbleFlag;
 
  public:
    Addr lineBaseAddr;
 
    TheISA::PCState pc;
 
    unsigned int lineWidth;
 
  public:
    Fault fault;
 
    InstId id;
 
    uint8_t *line;
 
    Packet *packet;
 
  public:
    ForwardLineData() :
        bubbleFlag(true),
        lineBaseAddr(0),
        lineWidth(0),
        fault(NoFault),
        line(NULL),
        packet(NULL)
    {
        /* Make lines bubbles by default */
    }
 
    ~ForwardLineData() { line = NULL; }
 
  public:
    bool isFault() const { return fault != NoFault; }
 
    void setFault(Fault fault_);
 
    void allocateLine(unsigned int width_);
 
    void adoptPacketData(Packet *packet);
 
    void freeLine();
 
    static ForwardLineData bubble() { return ForwardLineData(); }
    bool isBubble() const { return bubbleFlag; }
 
    void reportData(std::ostream &os) const;
};
 
const unsigned int MAX_FORWARD_INSTS = 16;
 
class ForwardInstData /* : public ReportIF, public BubbleIF */
{
  public:
    MinorDynInstPtr insts[MAX_FORWARD_INSTS];
 
    unsigned int numInsts;
 
    ThreadID threadId;
 
  public:
    explicit ForwardInstData(unsigned int width = 0,
                             ThreadID tid = InvalidThreadID);
 
    ForwardInstData(const ForwardInstData &src);
 
  public:
    unsigned int width() const { return numInsts; }
 
    ForwardInstData &operator =(const ForwardInstData &src);
 
    void resize(unsigned int width);
 
    void bubbleFill();
 
    bool isBubble() const;
 
    void reportData(std::ostream &os) const;
};
 
} // namespace minor
} // namespace gem5
 
#endif /* __CPU_MINOR_PIPE_DATA_HH__ */