rename_map.cc

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#include "cpu/o3/rename_map.hh"
 
#include <vector>
 
#include "arch/vecregs.hh"
#include "cpu/reg_class.hh"
#include "debug/Rename.hh"
 
namespace gem5
{
 
namespace o3
{
 
SimpleRenameMap::SimpleRenameMap()
    : freeList(NULL), zeroReg(IntRegClass, 0)
{
}
 
 
void
SimpleRenameMap::init(const RegClassInfo &reg_class_info,
        SimpleFreeList *_freeList)
{
    assert(freeList == NULL);
    assert(map.empty());
 
    map.resize(reg_class_info.size());
    freeList = _freeList;
    zeroReg = RegId(IntRegClass, reg_class_info.zeroReg());
}
 
SimpleRenameMap::RenameInfo
SimpleRenameMap::rename(const RegId& arch_reg)
{
    PhysRegIdPtr renamed_reg;
    // Record the current physical register that is renamed to the
    // requested architected register.
    PhysRegIdPtr prev_reg = map[arch_reg.flatIndex()];
 
    if (arch_reg == zeroReg) {
        assert(prev_reg->index() == zeroReg.index());
        renamed_reg = prev_reg;
    } else if (prev_reg->getNumPinnedWrites() > 0) {
        // Do not rename if the register is pinned
        assert(arch_reg.getNumPinnedWrites() == 0);  // Prevent pinning the
                                                     // same register twice
        DPRINTF(Rename, "Renaming pinned reg, numPinnedWrites %d\n",
                prev_reg->getNumPinnedWrites());
        renamed_reg = prev_reg;
        renamed_reg->decrNumPinnedWrites();
    } else {
        renamed_reg = freeList->getReg();
        map[arch_reg.flatIndex()] = renamed_reg;
        renamed_reg->setNumPinnedWrites(arch_reg.getNumPinnedWrites());
        renamed_reg->setNumPinnedWritesToComplete(
            arch_reg.getNumPinnedWrites() + 1);
    }
 
    DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was"
            " %d (%d)\n",
            arch_reg, renamed_reg->flatIndex(), renamed_reg->flatIndex(),
            prev_reg->flatIndex(), prev_reg->flatIndex());
 
    return RenameInfo(renamed_reg, prev_reg);
}
 
 
/**** UnifiedRenameMap methods ****/
 
void
UnifiedRenameMap::init(const BaseISA::RegClasses &regClasses,
        PhysRegFile *_regFile, UnifiedFreeList *freeList, VecMode _mode)
{
    regFile = _regFile;
    vecMode = _mode;
 
    intMap.init(regClasses.at(IntRegClass), &(freeList->intList));
    floatMap.init(regClasses.at(FloatRegClass), &(freeList->floatList));
    vecMap.init(regClasses.at(VecRegClass), &(freeList->vecList));
    vecElemMap.init(regClasses.at(VecElemClass), &(freeList->vecElemList));
    predMap.init(regClasses.at(VecPredRegClass), &(freeList->predList));
    ccMap.init(regClasses.at(CCRegClass), &(freeList->ccList));
 
}
 
void
UnifiedRenameMap::switchFreeList(UnifiedFreeList* freeList)
{
    if (vecMode == enums::Elem) {
 
        /* The free list should currently be tracking full registers. */
        panic_if(freeList->hasFreeVecElems(),
                "The free list is already tracking Vec elems");
        panic_if(freeList->numFreeVecRegs() !=
                regFile->numVecPhysRegs() - vecMap.numArchRegs(),
                "The free list has lost vector registers");
 
        /* Split the free regs. */
        while (freeList->hasFreeVecRegs()) {
            auto vr = freeList->getVecReg();
            auto range = this->regFile->getRegElemIds(vr);
            freeList->addRegs(range.first, range.second);
        }
 
    } else if (vecMode == enums::Full) {
 
        /* The free list should currently be tracking register elems. */
        panic_if(freeList->hasFreeVecRegs(),
                "The free list is already tracking full Vec");
        panic_if(freeList->numFreeVecElems() !=
                 regFile->numVecElemPhysRegs() - vecElemMap.numArchRegs(),
                 "The free list has lost vector register elements");
 
        auto range = regFile->getRegIds(VecRegClass);
        freeList->addRegs(range.first + vecMap.numArchRegs(), range.second);
 
        /* We remove the elems from the free list. */
        while (freeList->hasFreeVecElems())
            freeList->getVecElem();
    }
}
 
void
UnifiedRenameMap::switchMode(VecMode newVecMode)
{
    if (newVecMode == enums::Elem && vecMode == enums::Full) {
 
        /* Switch to vector element rename mode. */
        vecMode = enums::Elem;
 
        /* Split the mapping of each arch reg. */
        int vec_idx = 0;
        for (auto &vec: vecMap) {
            PhysRegFile::IdRange range = this->regFile->getRegElemIds(vec);
            auto idx = 0;
            for (auto phys_elem = range.first;
                 phys_elem < range.second; idx++, phys_elem++) {
 
                setEntry(RegId(VecElemClass, vec_idx, idx), &(*phys_elem));
            }
            vec_idx++;
        }
 
    } else if (newVecMode == enums::Full && vecMode == enums::Elem) {
 
        /* Switch to full vector register rename mode. */
        vecMode = enums::Full;
 
        /* To rebuild the arch regs we take the easy road:
         *  1.- Stitch the elems together into vectors.
         *  2.- Replace the contents of the register file with the vectors
         *  3.- Set the remaining registers as free
         */
        TheISA::VecRegContainer new_RF[vecMap.numArchRegs()];
        const size_t numVecs = vecMap.numArchRegs();
        const size_t numElems = vecElemMap.numArchRegs();
        const size_t elemsPerVec = numElems / numVecs;
        for (uint32_t i = 0; i < numVecs; i++) {
            TheISA::VecElem *dst = new_RF[i].as<TheISA::VecElem>();
            for (uint32_t l = 0; l < elemsPerVec; l++) {
                RegId s_rid(VecElemClass, i, l);
                PhysRegIdPtr s_prid = vecElemMap.lookup(s_rid);
                dst[l] = regFile->readVecElem(s_prid);
            }
        }
 
        for (uint32_t i = 0; i < numVecs; i++) {
            PhysRegId pregId(VecRegClass, i, 0);
            regFile->setVecReg(regFile->getTrueId(&pregId), new_RF[i]);
        }
 
        auto range = regFile->getRegIds(VecRegClass);
        for (uint32_t i = 0; i < numVecs; i++) {
            setEntry(RegId(VecRegClass, i), &(*(range.first + i)));
        }
 
    }
}
 
} // namespace o3
} // namespace gem5