tarmac_record_v8.hh

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/*
 * Copyright (c) 2017-2019 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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 * neither the name of the copyright holders nor the names of its
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 * this software without specific prior written permission.
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#ifndef __ARCH_ARM_TRACERS_TARMAC_RECORD_V8_HH__
#define __ARCH_ARM_TRACERS_TARMAC_RECORD_V8_HH__
 
#include "tarmac_record.hh"
 
namespace gem5
{
 
namespace Trace {
 
class TarmacTracerRecordV8 : public TarmacTracerRecord
{
  public:
 
    struct TraceEntryV8
    {
      public:
        TraceEntryV8(std::string _cpuName)
          : cpuName(_cpuName)
        {}
 
      protected:
        std::string cpuName;
    };
 
    struct TraceInstEntryV8: public TraceInstEntry, TraceEntryV8
    {
      public:
        TraceInstEntryV8(const TarmacContext& tarmCtx, bool predicate);
 
        virtual void print(std::ostream& outs,
                           int verbosity = 0,
                           const std::string &prefix = "") const override;
 
      protected:
        Addr paddr;
        bool paddrValid;
    };
 
    struct TraceRegEntryV8: public TraceRegEntry, TraceEntryV8
    {
      public:
        TraceRegEntryV8(const TarmacContext& tarmCtx, const RegId& reg);
 
        virtual void print(std::ostream& outs,
                           int verbosity = 0,
                           const std::string &prefix = "") const override;
 
      protected:
        void updateInt(const TarmacContext& tarmCtx,
                       RegIndex regRelIdx) override;
 
        void updateMisc(const TarmacContext& tarmCtx,
                        RegIndex regRelIdx) override;
 
        void updateVec(const TarmacContext& tarmCtx,
                       RegIndex regRelIdx) override;
 
        void updatePred(const TarmacContext& tarmCtx,
                        RegIndex regRelIdx) override;
 
        std::string formatReg() const;
 
        uint16_t regWidth;
    };
 
    struct TraceMemEntryV8: public TraceMemEntry, TraceEntryV8
    {
      public:
        TraceMemEntryV8(const TarmacContext& tarmCtx,
                        uint8_t _size, Addr _addr, uint64_t _data);
 
        virtual void print(std::ostream& outs,
                           int verbosity = 0,
                           const std::string &prefix = "") const override;
 
      protected:
        Addr paddr;
    };
 
  public:
    TarmacTracerRecordV8(Tick _when, ThreadContext *_thread,
                         const StaticInstPtr _staticInst, ArmISA::PCState _pc,
                         TarmacTracer& _parent,
                         const StaticInstPtr _macroStaticInst = NULL)
      : TarmacTracerRecord(_when, _thread, _staticInst, _pc,
                           _parent, _macroStaticInst)
    {}
 
  protected:
    void addInstEntry(std::vector<InstPtr>& queue, const TarmacContext& ptr);
 
    void addMemEntry(std::vector<MemPtr>& queue, const TarmacContext& ptr);
 
    void addRegEntry(std::vector<RegPtr>& queue, const TarmacContext& ptr);
};
 
} // namespace Trace
} // namespace gem5
 
#endif // __ARCH_ARM_TRACERS_TARMAC_RECORD_V8_HH__