tlb.hh

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#ifndef __ARCH_ARM_TLB_HH__
#define __ARCH_ARM_TLB_HH__
 
 
#include "arch/arm/faults.hh"
#include "arch/arm/pagetable.hh"
#include "arch/arm/utility.hh"
#include "arch/generic/tlb.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
#include "params/ArmTLB.hh"
#include "sim/probe/pmu.hh"
 
namespace gem5
{
 
class ThreadContext;
 
namespace ArmISA {
 
class TableWalker;
class Stage2LookUp;
class TLB;
 
class TLBIALL;
class TLBIALLEL;
class TLBIVMALL;
class TLBIALLN;
class TLBIMVA;
class TLBIASID;
class TLBIMVAA;
 
class TlbTestInterface
{
  public:
    TlbTestInterface() {}
    virtual ~TlbTestInterface() {}
 
    virtual Fault translationCheck(const RequestPtr &req, bool is_priv,
                                   BaseMMU::Mode mode,
                                   TlbEntry::DomainType domain) = 0;
 
    virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure,
                            Addr is_priv, BaseMMU::Mode mode,
                            TlbEntry::DomainType domain,
                            LookupLevel lookup_level) = 0;
};
 
class TLB : public BaseTLB
{
  public:
    enum ArmFlags
    {
        AlignmentMask = 0x7,
 
        AlignByte = 0x0,
        AlignHalfWord = 0x1,
        AlignWord = 0x2,
        AlignDoubleWord = 0x3,
        AlignQuadWord = 0x4,
        AlignOctWord = 0x5,
 
        AllowUnaligned = 0x8,
        // Priv code operating as if it wasn't
        UserMode = 0x10
    };
 
    enum ArmTranslationType
    {
        NormalTran = 0,
        S1CTran = 0x1,
        HypMode = 0x2,
        // Secure code operating as if it wasn't (required by some Address
        // Translate operations)
        S1S2NsTran = 0x4,
        // Address translation instructions (eg AT S1E0R_Xt) need to be handled
        // in special ways during translation because they could need to act
        // like a different EL than the current EL. The following flags are
        // for these instructions
        S1E0Tran = 0x8,
        S1E1Tran = 0x10,
        S1E2Tran = 0x20,
        S1E3Tran = 0x40,
        S12E0Tran = 0x80,
        S12E1Tran = 0x100
    };
 
    static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type);
 
  protected:
    TlbEntry* table;     // the Page Table
    int size;            // TLB Size
    bool isStage2;       // Indicates this TLB is part of the second stage MMU
    bool stage2Req;      // Indicates whether a stage 2 lookup is also required
    // Indicates whether a stage 2 lookup of the table descriptors is required.
    // Certain address translation instructions will intercept the IPA but the
    // table descriptors still need to be translated by the stage2.
    bool stage2DescReq;
    uint64_t _attr;      // Memory attributes for last accessed TLB entry
    bool directToStage2; // Indicates whether all translation requests should
                         // be routed directly to the stage 2 TLB
 
    TableWalker *tableWalker;
    TLB *stage2Tlb;
 
    TlbTestInterface *test;
 
    struct TlbStats : public statistics::Group
    {
        TlbStats(statistics::Group *parent);
        // Access Stats
        mutable statistics::Scalar instHits;
        mutable statistics::Scalar instMisses;
        mutable statistics::Scalar readHits;
        mutable statistics::Scalar readMisses;
        mutable statistics::Scalar writeHits;
        mutable statistics::Scalar writeMisses;
        mutable statistics::Scalar inserts;
        mutable statistics::Scalar flushTlb;
        mutable statistics::Scalar flushTlbMva;
        mutable statistics::Scalar flushTlbMvaAsid;
        mutable statistics::Scalar flushTlbAsid;
        mutable statistics::Scalar flushedEntries;
        mutable statistics::Scalar alignFaults;
        mutable statistics::Scalar prefetchFaults;
        mutable statistics::Scalar domainFaults;
        mutable statistics::Scalar permsFaults;
 
        statistics::Formula readAccesses;
        statistics::Formula writeAccesses;
        statistics::Formula instAccesses;
        statistics::Formula hits;
        statistics::Formula misses;
        statistics::Formula accesses;
    } stats;
 
    probing::PMUUPtr ppRefills;
 
    int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
 
  public:
    using Params = ArmTLBParams;
    TLB(const Params &p);
    TLB(const Params &p, int _size, TableWalker *_walker);
 
    TlbEntry *lookup(Addr vpn, uint16_t asn, vmid_t vmid, bool hyp,
                     bool secure, bool functional,
                     bool ignore_asn, ExceptionLevel target_el,
                     bool in_host, BaseMMU::Mode mode);
 
    virtual ~TLB();
 
    void takeOverFrom(BaseTLB *otlb) override;
 
    void setTestInterface(SimObject *ti);
 
    void setStage2Tlb(TLB *stage2_tlb) { stage2Tlb = stage2_tlb; }
 
    void setTableWalker(TableWalker *table_walker);
 
    TableWalker *getTableWalker() { return tableWalker; }
 
    int getsize() const { return size; }
 
    void insert(Addr vaddr, TlbEntry &pte);
 
    Fault getTE(TlbEntry **te, const RequestPtr &req,
                ThreadContext *tc, BaseMMU::Mode mode,
                BaseMMU::Translation *translation,
                bool timing, bool functional,
                bool is_secure, ArmTranslationType tranType);
 
    Fault getResultTe(TlbEntry **te, const RequestPtr &req,
                      ThreadContext *tc, BaseMMU::Mode mode,
                      BaseMMU::Translation *translation, bool timing,
                      bool functional, TlbEntry *mergeTe);
 
    Fault checkPermissions(TlbEntry *te, const RequestPtr &req,
                           BaseMMU::Mode mode);
    Fault checkPermissions64(TlbEntry *te, const RequestPtr &req,
                             BaseMMU::Mode mode, ThreadContext *tc);
    bool checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req,
                  BaseMMU::Mode mode, const bool is_priv);
 
    void flushAll() override;
 
 
    void flush(const TLBIALL &tlbi_op);
 
    void flush(const TLBIALLEL &tlbi_op);
 
    void flush(const TLBIVMALL &tlbi_op);
 
    void flush(const TLBIALLN &tlbi_op);
 
    void flush(const TLBIMVA &tlbi_op);
 
    void flush(const TLBIASID &tlbi_op);
 
    void flush(const TLBIMVAA &tlbi_op);
 
    Fault trickBoxCheck(const RequestPtr &req, BaseMMU::Mode mode,
                        TlbEntry::DomainType domain);
 
    Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz,
                            bool is_exec, bool is_write,
                            TlbEntry::DomainType domain,
                            LookupLevel lookup_level);
 
    void printTlb() const;
 
    void demapPage(Addr vaddr, uint64_t asn) override
    {
        // needed for x86 only
        panic("demapPage() is not implemented.\n");
    }
 
    bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
 
    Fault translateFunctional(const RequestPtr &req, ThreadContext *tc,
            BaseMMU::Mode mode, ArmTranslationType tranType);
    Fault
    translateFunctional(const RequestPtr &req,
                        ThreadContext *tc, BaseMMU::Mode mode) override
    {
        return translateFunctional(req, tc, mode, NormalTran);
    }
 
    void
    setAttr(uint64_t attr)
    {
        _attr = attr;
    }
 
    uint64_t
    getAttr() const
    {
        return _attr;
    }
 
    Fault translateMmuOff(ThreadContext *tc, const RequestPtr &req,
        BaseMMU::Mode mode, TLB::ArmTranslationType tranType,
        Addr vaddr, bool long_desc_format);
    Fault translateMmuOn(ThreadContext *tc, const RequestPtr &req,
        BaseMMU::Mode mode, BaseMMU::Translation *translation, bool &delay,
        bool timing, bool functional,
        Addr vaddr, ArmFault::TranMethod tranMethod);
 
    Fault translateFs(const RequestPtr &req, ThreadContext *tc,
        BaseMMU::Mode mode, BaseMMU::Translation *translation,
        bool &delay, bool timing, ArmTranslationType tranType,
        bool functional = false);
    Fault translateSe(const RequestPtr &req, ThreadContext *tc,
        BaseMMU::Mode mode, BaseMMU::Translation *translation,
        bool &delay, bool timing);
 
    Fault translateAtomic(const RequestPtr &req, ThreadContext *tc,
        BaseMMU::Mode mode, ArmTranslationType tranType);
 
    Fault
    translateAtomic(const RequestPtr &req,
                    ThreadContext *tc, BaseMMU::Mode mode) override
    {
        return translateAtomic(req, tc, mode, NormalTran);
    }
    void translateTiming(
            const RequestPtr &req, ThreadContext *tc,
            BaseMMU::Translation *translation, BaseMMU::Mode mode,
            ArmTranslationType tranType);
    void
    translateTiming(const RequestPtr &req, ThreadContext *tc,
                    BaseMMU::Translation *translation,
                    BaseMMU::Mode mode) override
    {
        translateTiming(req, tc, translation, mode, NormalTran);
    }
    Fault translateComplete(const RequestPtr &req, ThreadContext *tc,
        BaseMMU::Translation *translation, BaseMMU::Mode mode,
        ArmTranslationType tranType, bool callFromS2);
    Fault finalizePhysical(
        const RequestPtr &req,
        ThreadContext *tc, BaseMMU::Mode mode) const override;
 
    void drainResume() override;
 
    void regProbePoints() override;
 
    Port *getTableWalkerPort() override;
 
    // Caching misc register values here.
    // Writing to misc registers needs to invalidate them.
    // translateFunctional/translateSe/translateFs checks if they are
    // invalid and call updateMiscReg if necessary.
protected:
    CPSR cpsr;
    bool aarch64;
    ExceptionLevel aarch64EL;
    SCTLR sctlr;
    SCR scr;
    bool isPriv;
    bool isSecure;
    bool isHyp;
    TTBCR ttbcr;
    uint16_t asid;
    vmid_t vmid;
    PRRR prrr;
    NMRR nmrr;
    HCR hcr;
    uint32_t dacr;
    bool miscRegValid;
    ContextID miscRegContext;
    ArmTranslationType curTranType;
 
    // Cached copies of system-level properties
    bool haveLPAE;
    bool haveVirtualization;
    bool haveLargeAsid64;
    uint8_t physAddrRange;
 
    AddrRange m5opRange;
 
    void updateMiscReg(ThreadContext *tc,
                       ArmTranslationType tranType = NormalTran);
 
    vmid_t getVMID(ThreadContext *tc) const;
 
public:
    void invalidateMiscReg() { miscRegValid = false; }
 
private:
    void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
                   bool ignore_asn, ExceptionLevel target_el,
                   bool in_host);
 
  public: /* Testing */
    Fault testTranslation(const RequestPtr &req, BaseMMU::Mode mode,
        TlbEntry::DomainType domain);
 
    Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure,
        BaseMMU::Mode mode, TlbEntry::DomainType domain,
        LookupLevel lookup_level);
};
 
} // namespace ArmISA
} // namespace gem5
 
#endif // __ARCH_ARM_TLB_HH__