btb.cc

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/*
 * Copyright (c) 2004-2005 The Regents of The University of Michigan
 * All rights reserved.
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#include "cpu/pred/btb.hh"
 
#include "base/intmath.hh"
#include "base/trace.hh"
#include "debug/Fetch.hh"
 
namespace gem5
{
 
namespace branch_prediction
{
 
DefaultBTB::DefaultBTB(unsigned _numEntries,
                       unsigned _tagBits,
                       unsigned _instShiftAmt,
                       unsigned _num_threads)
    : numEntries(_numEntries),
      tagBits(_tagBits),
      instShiftAmt(_instShiftAmt),
      log2NumThreads(floorLog2(_num_threads))
{
    DPRINTF(Fetch, "BTB: Creating BTB object.\n");
 
    if (!isPowerOf2(numEntries)) {
        fatal("BTB entries is not a power of 2!");
    }
 
    btb.resize(numEntries);
 
    for (unsigned i = 0; i < numEntries; ++i) {
        btb[i].valid = false;
    }
 
    idxMask = numEntries - 1;
 
    tagMask = (1 << tagBits) - 1;
 
    tagShiftAmt = instShiftAmt + floorLog2(numEntries);
}
 
void
DefaultBTB::reset()
{
    for (unsigned i = 0; i < numEntries; ++i) {
        btb[i].valid = false;
    }
}
 
inline
unsigned
DefaultBTB::getIndex(Addr instPC, ThreadID tid)
{
    // Need to shift PC over by the word offset.
    return ((instPC >> instShiftAmt)
            ^ (tid << (tagShiftAmt - instShiftAmt - log2NumThreads)))
            & idxMask;
}
 
inline
Addr
DefaultBTB::getTag(Addr instPC)
{
    return (instPC >> tagShiftAmt) & tagMask;
}
 
bool
DefaultBTB::valid(Addr instPC, ThreadID tid)
{
    unsigned btb_idx = getIndex(instPC, tid);
 
    Addr inst_tag = getTag(instPC);
 
    assert(btb_idx < numEntries);
 
    if (btb[btb_idx].valid
        && inst_tag == btb[btb_idx].tag
        && btb[btb_idx].tid == tid) {
        return true;
    } else {
        return false;
    }
}
 
// @todo Create some sort of return struct that has both whether or not the
// address is valid, and also the address.  For now will just use addr = 0 to
// represent invalid entry.
TheISA::PCState
DefaultBTB::lookup(Addr instPC, ThreadID tid)
{
    unsigned btb_idx = getIndex(instPC, tid);
 
    Addr inst_tag = getTag(instPC);
 
    assert(btb_idx < numEntries);
 
    if (btb[btb_idx].valid
        && inst_tag == btb[btb_idx].tag
        && btb[btb_idx].tid == tid) {
        return btb[btb_idx].target;
    } else {
        return 0;
    }
}
 
void
DefaultBTB::update(Addr instPC, const TheISA::PCState &target, ThreadID tid)
{
    unsigned btb_idx = getIndex(instPC, tid);
 
    assert(btb_idx < numEntries);
 
    btb[btb_idx].tid = tid;
    btb[btb_idx].valid = true;
    btb[btb_idx].target = target;
    btb[btb_idx].tag = getTag(instPC);
}
 
} // namespace branch_prediction
} // namespace gem5