gem5  v21.1.0.1
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gem5::HSAQueueEntry Class Reference

#include <hsa_queue_entry.hh>

Public Member Functions

 HSAQueueEntry (std::string kernel_name, uint32_t queue_id, int dispatch_id, void *disp_pkt, AMDKernelCode *akc, Addr host_pkt_addr, Addr code_addr)
 
const std::string & kernelName () const
 
int wgSize (int dim) const
 
int gridSize (int dim) const
 
int numVectorRegs () const
 
int numScalarRegs () const
 
uint32_t queueId () const
 
int dispatchId () const
 
void * dispPktPtr ()
 
Addr hostDispPktAddr () const
 
Addr completionSignal () const
 
Addr codeAddr () const
 
Addr kernargAddr () const
 
int ldsSize () const
 
int privMemPerItem () const
 
int contextId () const
 
bool dispComplete () const
 
int wgId (int dim) const
 
void wgId (int dim, int val)
 
int globalWgId () const
 
void globalWgId (int val)
 
int numWg (int dim) const
 
void notifyWgCompleted ()
 
int numWgCompleted () const
 
int numWgTotal () const
 
void markWgDispatch ()
 
int numWgAtBarrier () const
 
bool vgprBitEnabled (int bit) const
 
bool sgprBitEnabled (int bit) const
 
int outstandingInvs ()
 
bool isInvStarted ()
 Whether invalidate has started or finished -1 is the initial value indicating inv has not started for the kernel. More...
 
void updateOutstandingInvs (int val)
 update the number of pending invalidate requests More...
 
void markInvDone ()
 Forcefully change the state to be inv done. More...
 
bool isInvDone () const
 Is invalidate done? More...
 
int outstandingWbs () const
 
void updateOutstandingWbs (int val)
 Update the number of pending writeback requests. More...
 

Public Attributes

Addr hostAMDQueueAddr
 Host-side addr of the amd_queue_t on which this task was queued. More...
 
_amd_queue_t amdQueue
 Keep a copy of the AMD HSA queue because we need info from some of its fields to initialize register state. More...
 

Static Public Attributes

const static int MAX_DIM = 3
 

Private Member Functions

void parseKernelCode (AMDKernelCode *akc)
 

Private Attributes

std::string kernName
 
std::array< int, MAX_DIM > _wgSize
 
std::array< int, MAX_DIM > _gridSize
 
int numVgprs
 
int numSgprs
 
uint32_t _queueId
 
int _dispatchId
 
void * dispPkt
 
Addr _hostDispPktAddr
 
Addr _completionSignal
 
Addr codeAddress
 
Addr kernargAddress
 
int _outstandingInvs
 Number of outstanding invs for the kernel. More...
 
int _outstandingWbs
 Number of outstanding wbs for the kernel values: 0: 1)initial value, flush has not started for the kernel 2)+1->0: all wb requests are finished, i.e., flush done ?: positive value, indicating the number of pending wb requests. More...
 
int _ldsSize
 
int _privMemPerItem
 
int _contextId
 
std::array< int, MAX_DIM > _wgId
 
std::array< int, MAX_DIM > _numWg
 
int _numWgTotal
 
int numWgArrivedAtBarrier
 
int _numWgCompleted
 
int _globalWgId
 
bool dispatchComplete
 
std::bitset< NumVectorInitFields > initialVgprState
 
std::bitset< NumScalarInitFields > initialSgprState
 

Detailed Description

Definition at line 61 of file hsa_queue_entry.hh.

Constructor & Destructor Documentation

◆ HSAQueueEntry()

gem5::HSAQueueEntry::HSAQueueEntry ( std::string  kernel_name,
uint32_t  queue_id,
int  dispatch_id,
void *  disp_pkt,
AMDKernelCode *  akc,
Addr  host_pkt_addr,
Addr  code_addr 
)
inline

Definition at line 64 of file hsa_queue_entry.hh.

Member Function Documentation

◆ codeAddr()

Addr gem5::HSAQueueEntry::codeAddr ( ) const
inline

Definition at line 179 of file hsa_queue_entry.hh.

References codeAddress.

Referenced by gem5::ComputeUnit::startWavefront(), and gem5::GPUCommandProcessor::submitDispatchPkt().

◆ completionSignal()

Addr gem5::HSAQueueEntry::completionSignal ( ) const
inline

Definition at line 173 of file hsa_queue_entry.hh.

References _completionSignal.

Referenced by gem5::GPUCommandProcessor::submitAgentDispatchPkt().

◆ contextId()

int gem5::HSAQueueEntry::contextId ( ) const
inline

Definition at line 199 of file hsa_queue_entry.hh.

References _contextId.

◆ dispatchId()

int gem5::HSAQueueEntry::dispatchId ( ) const
inline

Definition at line 155 of file hsa_queue_entry.hh.

References _dispatchId.

Referenced by gem5::GPUDispatcher::dispatch(), gem5::ComputeUnit::dispWorkgroup(), gem5::Shader::prepareInvalidate(), and gem5::ComputeUnit::startWavefront().

◆ dispComplete()

bool gem5::HSAQueueEntry::dispComplete ( ) const
inline

Definition at line 205 of file hsa_queue_entry.hh.

References dispatchComplete.

Referenced by gem5::Shader::dispatchWorkgroups().

◆ dispPktPtr()

void* gem5::HSAQueueEntry::dispPktPtr ( )
inline

Definition at line 161 of file hsa_queue_entry.hh.

References dispPkt.

◆ globalWgId() [1/2]

int gem5::HSAQueueEntry::globalWgId ( ) const
inline

Definition at line 225 of file hsa_queue_entry.hh.

References _globalWgId.

Referenced by gem5::Shader::dispatchWorkgroups(), gem5::ComputeUnit::dispWorkgroup(), and gem5::ComputeUnit::startWavefront().

◆ globalWgId() [2/2]

void gem5::HSAQueueEntry::globalWgId ( int  val)
inline

Definition at line 231 of file hsa_queue_entry.hh.

References _globalWgId, and gem5::X86ISA::val.

◆ gridSize()

int gem5::HSAQueueEntry::gridSize ( int  dim) const
inline

Definition at line 130 of file hsa_queue_entry.hh.

References _gridSize, and MAX_DIM.

Referenced by gem5::ComputeUnit::fillKernelState(), gem5::ComputeUnit::hasDispResources(), gem5::Wavefront::initRegState(), and markWgDispatch().

◆ hostDispPktAddr()

Addr gem5::HSAQueueEntry::hostDispPktAddr ( ) const
inline

Definition at line 167 of file hsa_queue_entry.hh.

References _hostDispPktAddr.

Referenced by gem5::Wavefront::initRegState().

◆ isInvDone()

bool gem5::HSAQueueEntry::isInvDone ( ) const
inline

Is invalidate done?

Definition at line 356 of file hsa_queue_entry.hh.

References _outstandingInvs.

Referenced by gem5::ComputeUnit::dispWorkgroup().

◆ isInvStarted()

bool gem5::HSAQueueEntry::isInvStarted ( )
inline

Whether invalidate has started or finished -1 is the initial value indicating inv has not started for the kernel.

Definition at line 326 of file hsa_queue_entry.hh.

References _outstandingInvs.

Referenced by gem5::Shader::prepareInvalidate().

◆ kernargAddr()

Addr gem5::HSAQueueEntry::kernargAddr ( ) const
inline

Definition at line 185 of file hsa_queue_entry.hh.

References kernargAddress.

Referenced by gem5::Wavefront::initRegState().

◆ kernelName()

const std::string& gem5::HSAQueueEntry::kernelName ( ) const
inline

Definition at line 117 of file hsa_queue_entry.hh.

References kernName.

Referenced by gem5::GPUDispatcher::dispatch().

◆ ldsSize()

int gem5::HSAQueueEntry::ldsSize ( ) const
inline

Definition at line 191 of file hsa_queue_entry.hh.

References _ldsSize.

Referenced by gem5::ComputeUnit::dispWorkgroup(), and gem5::ComputeUnit::hasDispResources().

◆ markInvDone()

void gem5::HSAQueueEntry::markInvDone ( )
inline

Forcefully change the state to be inv done.

Definition at line 347 of file hsa_queue_entry.hh.

References _outstandingInvs.

◆ markWgDispatch()

void gem5::HSAQueueEntry::markWgDispatch ( )
inline

Definition at line 262 of file hsa_queue_entry.hh.

References _globalWgId, _wgId, dispatchComplete, gridSize(), wgId(), and wgSize().

Referenced by gem5::Shader::dispatchWorkgroups().

◆ notifyWgCompleted()

void gem5::HSAQueueEntry::notifyWgCompleted ( )
inline

Definition at line 244 of file hsa_queue_entry.hh.

References _numWgCompleted.

◆ numScalarRegs()

int gem5::HSAQueueEntry::numScalarRegs ( ) const
inline

Definition at line 143 of file hsa_queue_entry.hh.

References numSgprs.

Referenced by gem5::ComputeUnit::dispWorkgroup(), gem5::ComputeUnit::fillKernelState(), gem5::ComputeUnit::hasDispResources(), and gem5::GPUCommandProcessor::submitDispatchPkt().

◆ numVectorRegs()

int gem5::HSAQueueEntry::numVectorRegs ( ) const
inline

Definition at line 137 of file hsa_queue_entry.hh.

References numVgprs.

Referenced by gem5::ComputeUnit::dispWorkgroup(), gem5::ComputeUnit::fillKernelState(), gem5::ComputeUnit::hasDispResources(), and gem5::GPUCommandProcessor::submitDispatchPkt().

◆ numWg()

int gem5::HSAQueueEntry::numWg ( int  dim) const
inline

Definition at line 237 of file hsa_queue_entry.hh.

References _numWg, and MAX_DIM.

Referenced by gem5::ComputeUnit::startWavefront().

◆ numWgAtBarrier()

int gem5::HSAQueueEntry::numWgAtBarrier ( ) const
inline

Definition at line 283 of file hsa_queue_entry.hh.

References numWgArrivedAtBarrier.

◆ numWgCompleted()

int gem5::HSAQueueEntry::numWgCompleted ( ) const
inline

Definition at line 250 of file hsa_queue_entry.hh.

References _numWgCompleted.

◆ numWgTotal()

int gem5::HSAQueueEntry::numWgTotal ( ) const
inline

Definition at line 256 of file hsa_queue_entry.hh.

References _numWgTotal.

◆ outstandingInvs()

int gem5::HSAQueueEntry::outstandingInvs ( )
inline

Definition at line 316 of file hsa_queue_entry.hh.

References _outstandingInvs.

Referenced by gem5::Shader::prepareInvalidate().

◆ outstandingWbs()

int gem5::HSAQueueEntry::outstandingWbs ( ) const
inline

Definition at line 363 of file hsa_queue_entry.hh.

References _outstandingWbs.

◆ parseKernelCode()

void gem5::HSAQueueEntry::parseKernelCode ( AMDKernelCode *  akc)
inlineprivate

set the enable bits for the initial SGPR state

set the enable bits for the initial VGPR state. the workitem Id in the X dimension is always initialized.

Definition at line 382 of file hsa_queue_entry.hh.

References gem5::DispatchId, gem5::DispatchPtr, gem5::AMDKernelCode::enable_sgpr_dispatch_id, gem5::AMDKernelCode::enable_sgpr_dispatch_ptr, gem5::AMDKernelCode::enable_sgpr_flat_scratch_init, gem5::AMDKernelCode::enable_sgpr_grid_workgroup_count_x, gem5::AMDKernelCode::enable_sgpr_grid_workgroup_count_y, gem5::AMDKernelCode::enable_sgpr_grid_workgroup_count_z, gem5::AMDKernelCode::enable_sgpr_kernarg_segment_ptr, gem5::AMDKernelCode::enable_sgpr_private_segment_buffer, gem5::AMDKernelCode::enable_sgpr_private_segment_size, gem5::AMDKernelCode::enable_sgpr_private_segment_wave_byte_offset, gem5::AMDKernelCode::enable_sgpr_queue_ptr, gem5::AMDKernelCode::enable_sgpr_workgroup_id_x, gem5::AMDKernelCode::enable_sgpr_workgroup_id_y, gem5::AMDKernelCode::enable_sgpr_workgroup_id_z, gem5::AMDKernelCode::enable_sgpr_workgroup_info, gem5::AMDKernelCode::enable_vgpr_workitem_id, gem5::FlatScratchInit, gem5::GridWorkgroupCountX, gem5::GridWorkgroupCountY, gem5::GridWorkgroupCountZ, initialSgprState, initialVgprState, gem5::KernargSegPtr, gem5::PrivateSegBuf, gem5::PrivateSegSize, gem5::PrivSegWaveByteOffset, gem5::QueuePtr, gem5::WorkgroupIdX, gem5::WorkgroupIdY, gem5::WorkgroupIdZ, gem5::WorkgroupInfo, gem5::WorkitemIdX, gem5::WorkitemIdY, and gem5::WorkitemIdZ.

◆ privMemPerItem()

int gem5::HSAQueueEntry::privMemPerItem ( ) const
inline

Definition at line 196 of file hsa_queue_entry.hh.

References _privMemPerItem.

Referenced by gem5::GPUCommandProcessor::MQDDmaEvent().

◆ queueId()

uint32_t gem5::HSAQueueEntry::queueId ( ) const
inline

Definition at line 149 of file hsa_queue_entry.hh.

References _queueId.

Referenced by gem5::GPUCommandProcessor::initABI(), gem5::GPUCommandProcessor::MQDDmaEvent(), and gem5::GPUCommandProcessor::ReadDispIdOffsetDmaEvent().

◆ sgprBitEnabled()

bool gem5::HSAQueueEntry::sgprBitEnabled ( int  bit) const
inline

Definition at line 293 of file hsa_queue_entry.hh.

References initialSgprState.

Referenced by gem5::Wavefront::initRegState().

◆ updateOutstandingInvs()

void gem5::HSAQueueEntry::updateOutstandingInvs ( int  val)
inline

update the number of pending invalidate requests

val: negative to decrement, positive to increment

Definition at line 337 of file hsa_queue_entry.hh.

References _outstandingInvs, and gem5::X86ISA::val.

◆ updateOutstandingWbs()

void gem5::HSAQueueEntry::updateOutstandingWbs ( int  val)
inline

Update the number of pending writeback requests.

val: negative to decrement, positive to increment

Definition at line 374 of file hsa_queue_entry.hh.

References _outstandingWbs, and gem5::X86ISA::val.

◆ vgprBitEnabled()

bool gem5::HSAQueueEntry::vgprBitEnabled ( int  bit) const
inline

Definition at line 288 of file hsa_queue_entry.hh.

References initialVgprState.

Referenced by gem5::Wavefront::initRegState().

◆ wgId() [1/2]

int gem5::HSAQueueEntry::wgId ( int  dim) const
inline

Definition at line 211 of file hsa_queue_entry.hh.

References _wgId, and MAX_DIM.

Referenced by gem5::Wavefront::computeActualWgSz(), gem5::ComputeUnit::hasDispResources(), and markWgDispatch().

◆ wgId() [2/2]

void gem5::HSAQueueEntry::wgId ( int  dim,
int  val 
)
inline

Definition at line 218 of file hsa_queue_entry.hh.

References _wgId, MAX_DIM, and gem5::X86ISA::val.

◆ wgSize()

int gem5::HSAQueueEntry::wgSize ( int  dim) const
inline

Definition at line 123 of file hsa_queue_entry.hh.

References _wgSize, and MAX_DIM.

Referenced by gem5::ComputeUnit::fillKernelState(), gem5::ComputeUnit::hasDispResources(), gem5::Wavefront::initRegState(), and markWgDispatch().

Member Data Documentation

◆ _completionSignal

Addr gem5::HSAQueueEntry::_completionSignal
private

Definition at line 443 of file hsa_queue_entry.hh.

Referenced by completionSignal().

◆ _contextId

int gem5::HSAQueueEntry::_contextId
private

Definition at line 467 of file hsa_queue_entry.hh.

Referenced by contextId().

◆ _dispatchId

int gem5::HSAQueueEntry::_dispatchId
private

Definition at line 437 of file hsa_queue_entry.hh.

Referenced by dispatchId().

◆ _globalWgId

int gem5::HSAQueueEntry::_globalWgId
private

Definition at line 474 of file hsa_queue_entry.hh.

Referenced by globalWgId(), and markWgDispatch().

◆ _gridSize

std::array<int, MAX_DIM> gem5::HSAQueueEntry::_gridSize
private

Definition at line 430 of file hsa_queue_entry.hh.

Referenced by gridSize().

◆ _hostDispPktAddr

Addr gem5::HSAQueueEntry::_hostDispPktAddr
private

Definition at line 441 of file hsa_queue_entry.hh.

Referenced by hostDispPktAddr().

◆ _ldsSize

int gem5::HSAQueueEntry::_ldsSize
private

Definition at line 465 of file hsa_queue_entry.hh.

Referenced by ldsSize().

◆ _numWg

std::array<int, MAX_DIM> gem5::HSAQueueEntry::_numWg
private

Definition at line 469 of file hsa_queue_entry.hh.

Referenced by numWg().

◆ _numWgCompleted

int gem5::HSAQueueEntry::_numWgCompleted
private

Definition at line 473 of file hsa_queue_entry.hh.

Referenced by notifyWgCompleted(), and numWgCompleted().

◆ _numWgTotal

int gem5::HSAQueueEntry::_numWgTotal
private

Definition at line 470 of file hsa_queue_entry.hh.

Referenced by numWgTotal().

◆ _outstandingInvs

int gem5::HSAQueueEntry::_outstandingInvs
private

Number of outstanding invs for the kernel.

values: -1: initial value, invalidate has not started for the kernel 0: 1)-1->0, about to start (a transient state, added in the same cycle) 2)+1->0, all inv requests are finished, i.e., invalidate done ?: positive value, indicating the number of pending inv requests

Definition at line 456 of file hsa_queue_entry.hh.

Referenced by isInvDone(), isInvStarted(), markInvDone(), outstandingInvs(), and updateOutstandingInvs().

◆ _outstandingWbs

int gem5::HSAQueueEntry::_outstandingWbs
private

Number of outstanding wbs for the kernel values: 0: 1)initial value, flush has not started for the kernel 2)+1->0: all wb requests are finished, i.e., flush done ?: positive value, indicating the number of pending wb requests.

Definition at line 464 of file hsa_queue_entry.hh.

Referenced by outstandingWbs(), and updateOutstandingWbs().

◆ _privMemPerItem

int gem5::HSAQueueEntry::_privMemPerItem
private

Definition at line 466 of file hsa_queue_entry.hh.

Referenced by privMemPerItem().

◆ _queueId

uint32_t gem5::HSAQueueEntry::_queueId
private

Definition at line 436 of file hsa_queue_entry.hh.

Referenced by queueId().

◆ _wgId

std::array<int, MAX_DIM> gem5::HSAQueueEntry::_wgId
private

Definition at line 468 of file hsa_queue_entry.hh.

Referenced by markWgDispatch(), and wgId().

◆ _wgSize

std::array<int, MAX_DIM> gem5::HSAQueueEntry::_wgSize
private

Definition at line 428 of file hsa_queue_entry.hh.

Referenced by wgSize().

◆ amdQueue

_amd_queue_t gem5::HSAQueueEntry::amdQueue

Keep a copy of the AMD HSA queue because we need info from some of its fields to initialize register state.

Definition at line 309 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::initRegState(), gem5::GPUCommandProcessor::MQDDmaEvent(), gem5::GPUCommandProcessor::ReadDispIdOffsetDmaEvent(), and gem5::GPUCommandProcessor::WaitScratchDmaEvent().

◆ codeAddress

Addr gem5::HSAQueueEntry::codeAddress
private

Definition at line 445 of file hsa_queue_entry.hh.

Referenced by codeAddr().

◆ dispatchComplete

bool gem5::HSAQueueEntry::dispatchComplete
private

Definition at line 475 of file hsa_queue_entry.hh.

Referenced by dispComplete(), and markWgDispatch().

◆ dispPkt

void* gem5::HSAQueueEntry::dispPkt
private

Definition at line 439 of file hsa_queue_entry.hh.

Referenced by dispPktPtr().

◆ hostAMDQueueAddr

Addr gem5::HSAQueueEntry::hostAMDQueueAddr

Host-side addr of the amd_queue_t on which this task was queued.

Definition at line 302 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::initRegState(), gem5::GPUCommandProcessor::ReadDispIdOffsetDmaEvent(), and gem5::GPUCommandProcessor::WaitScratchDmaEvent().

◆ initialSgprState

std::bitset<NumScalarInitFields> gem5::HSAQueueEntry::initialSgprState
private

Definition at line 478 of file hsa_queue_entry.hh.

Referenced by parseKernelCode(), and sgprBitEnabled().

◆ initialVgprState

std::bitset<NumVectorInitFields> gem5::HSAQueueEntry::initialVgprState
private

Definition at line 477 of file hsa_queue_entry.hh.

Referenced by parseKernelCode(), and vgprBitEnabled().

◆ kernargAddress

Addr gem5::HSAQueueEntry::kernargAddress
private

Definition at line 447 of file hsa_queue_entry.hh.

Referenced by kernargAddr().

◆ kernName

std::string gem5::HSAQueueEntry::kernName
private

Definition at line 426 of file hsa_queue_entry.hh.

Referenced by kernelName().

◆ MAX_DIM

const static int gem5::HSAQueueEntry::MAX_DIM = 3
static

Definition at line 312 of file hsa_queue_entry.hh.

Referenced by gem5::Wavefront::computeActualWgSz(), gridSize(), gem5::ComputeUnit::hasDispResources(), numWg(), wgId(), and wgSize().

◆ numSgprs

int gem5::HSAQueueEntry::numSgprs
private

Definition at line 434 of file hsa_queue_entry.hh.

Referenced by numScalarRegs().

◆ numVgprs

int gem5::HSAQueueEntry::numVgprs
private

Definition at line 432 of file hsa_queue_entry.hh.

Referenced by numVectorRegs().

◆ numWgArrivedAtBarrier

int gem5::HSAQueueEntry::numWgArrivedAtBarrier
private

Definition at line 471 of file hsa_queue_entry.hh.

Referenced by numWgAtBarrier().

The documentation for this class was generated from the following file:
Generated on Tue Sep 7 2021 14:54:00 for gem5 by doxygen 1.8.17