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compressed.hh
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1 /*
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29 
30 #ifndef __ARCH_RISCV_INSTS_COMPRESSED_HH__
31 #define __ARCH_RISCV_INSTS_COMPRESSED_HH__
32 
33 #include <string>
34 
35 #include "arch/riscv/insts/static_inst.hh"
36 #include "cpu/static_inst.hh"
37 
38 namespace gem5
39 {
40 
41 namespace RiscvISA
42 {
43 
47 class CompRegOp : public RiscvStaticInst
48 {
49  protected:
50  using RiscvStaticInst::RiscvStaticInst;
51 
52  std::string generateDisassembly(
53  Addr pc, const loader::SymbolTable *symtab) const override;
54 };
55 
56 } // namespace RiscvISA
57 } // namespace gem5
58 
59 #endif // __ARCH_RISCV_INSTS_COMPRESSED_HH__
gem5::RiscvISA::RiscvStaticInst
Base class for all RISC-V static instructions.
Definition: static_inst.hh:49
gem5::RiscvISA::RiscvStaticInst::RiscvStaticInst
RiscvStaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:52
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::RiscvISA::CompRegOp
Base class for compressed operations that work only on registers.
Definition: compressed.hh:47
static_inst.hh
static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RiscvISA::CompRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: compressed.cc:45
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