64 params().enable_trace_special_hlt_imm16);
67 params().l2cache_maintenance_latency);
70 params().l2cache_read_access_latency);
74 params().l2cache_snoop_data_transfer_latency);
76 params().l2cache_snoop_issue_latency);
78 params().l2cache_write_access_latency);
101 if (if_name ==
"redistributor")
110 for (
int i = 0;
i <
p.cores.size();
i++)
111 p.cores[
i]->setCluster(
this,
i);
114 panic_if(!
e,
"EVS should be of type Iris::BaseCpuEvs");
127 p.dcache_maintenance_latency);
130 p.dcache_prefetch_enabled);
132 p.dcache_read_access_latency);
135 p.dcache_snoop_data_transfer_latency);
136 set_evs_param(
"core.dcache-state_modelled",
p.dcache_state_modelled);
138 p.dcache_write_access_latency);
139 set_evs_param(
"core.dcache-write_latency",
p.dcache_write_latency);
142 set_evs_param(
"core.enable_simulation_performance_optimizations",
143 p.enable_simulation_performance_optimizations);
145 p.ext_abort_device_read_is_sync);
147 p.ext_abort_device_write_is_sync);
149 p.ext_abort_so_read_is_sync);
151 p.ext_abort_so_write_is_sync);
153 p.gicv3_cpuintf_mmap_access_level);
156 p.has_statistical_profiling);
159 p.icache_maintenance_latency);
162 p.icache_prefetch_enabled);
164 p.icache_read_access_latency);
166 set_evs_param(
"core.icache-state_modelled",
p.icache_state_modelled);
169 p.l3cache_maintenance_latency);
170 set_evs_param(
"core.l3cache-miss_latency",
p.l3cache_miss_latency);
172 p.l3cache_read_access_latency);
173 set_evs_param(
"core.l3cache-read_latency",
p.l3cache_read_latency);
176 p.l3cache_snoop_data_transfer_latency);
178 p.l3cache_snoop_issue_latency);
180 p.l3cache_write_access_latency);
181 set_evs_param(
"core.l3cache-write_latency",
p.l3cache_write_latency);
183 p.pchannel_treat_simreset_as_poreset);
185 set_evs_param(
"core.periph_address_start",
p.periph_address_start);
189 p.treat_dcache_cmos_to_pou_as_nop);
196 if (if_name ==
"amba") {