dramsim3_wrapper.cc

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/*
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 * to a hardware implementation of the functionality of the software
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#include <cassert>
 
#ifdef DEBUG
#undef DEBUG
#endif
 
#include "mem/dramsim3_wrapper.hh"
 
#include <fstream>
 
#include "DRAMsim3/src/dramsim3.h"
#include "base/compiler.hh"
#include "base/logging.hh"
 
namespace gem5
{
 
namespace memory
{
 
DRAMsim3Wrapper::DRAMsim3Wrapper(const std::string& config_file,
                                 const std::string& working_dir,
                                 std::function<void(uint64_t)> read_cb,
                                 std::function<void(uint64_t)> write_cb) :
    dramsim(dramsim3::GetMemorySystem(config_file, working_dir,
                                       read_cb, write_cb)),
    _clockPeriod(0.0), _queueSize(0), _burstSize(0)
{
    // there is no way of getting DRAMsim3 to tell us what frequency
    // it is assuming, so we have to extract it ourselves
    _clockPeriod = dramsim->GetTCK();
 
    if (!_clockPeriod)
        fatal("DRAMsim3 wrapper failed to get clock\n");
 
    // we also need to know what transaction queue size DRAMsim3 is
    // using so we can stall when responses are blocked
    _queueSize = dramsim->GetQueueSize();
 
    if (!_queueSize)
        fatal("DRAMsim3 wrapper failed to get queue size\n");
 
 
   // finally, get the data bus bits and burst length so we can add a
   // sanity check for the burst size
   unsigned int dataBusBits = dramsim->GetBusBits();
   unsigned int burstLength = dramsim->GetBurstLength();
 
   if (!dataBusBits || !burstLength)
       fatal("DRAMsim3 wrapper failed to get burst size\n");
 
   _burstSize = dataBusBits * burstLength / 8;
}
 
DRAMsim3Wrapper::~DRAMsim3Wrapper()
{
    delete dramsim;
}
 
 
void
DRAMsim3Wrapper::printStats()
{
    dramsim->PrintStats();
}
 
void
DRAMsim3Wrapper::resetStats()
{
    dramsim->ResetStats();
}
 
void
DRAMsim3Wrapper::setCallbacks(std::function<void(uint64_t)> read_complete,
                              std::function<void(uint64_t)> write_complete)
{
    dramsim->RegisterCallbacks(read_complete, write_complete);
}
 
bool
DRAMsim3Wrapper::canAccept(uint64_t addr, bool is_write) const
{
    return dramsim->WillAcceptTransaction(addr, is_write);
}
 
void
DRAMsim3Wrapper::enqueue(uint64_t addr, bool is_write)
{
    GEM5_VAR_USED bool success = dramsim->AddTransaction(addr, is_write);
    assert(success);
}
 
double
DRAMsim3Wrapper::clockPeriod() const
{
    return _clockPeriod;
}
 
unsigned int
DRAMsim3Wrapper::queueSize() const
{
    return _queueSize;
}
 
unsigned int
DRAMsim3Wrapper::burstSize() const
{
    return _burstSize;
}
 
void
DRAMsim3Wrapper::tick()
{
    dramsim->ClockTick();
}
 
} // namespace memory
} // namespace gem5