insttracer.hh

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#ifndef __INSTRECORD_HH__
#define __INSTRECORD_HH__
 
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "cpu/static_inst.hh"
#include "sim/sim_object.hh"
 
namespace gem5
{
 
class ThreadContext;
 
namespace Trace {
 
class InstRecord
{
  protected:
    Tick when;
 
    // The following fields are initialized by the constructor and
    // thus guaranteed to be valid.
    ThreadContext *thread;
    // need to make this ref-counted so it doesn't go away before we
    // dump the record
    StaticInstPtr staticInst;
    TheISA::PCState pc;
    StaticInstPtr macroStaticInst;
 
    // The remaining fields are only valid for particular instruction
    // types (e.g, addresses for memory ops) or when particular
    // options are enabled (e.g., tracing full register contents).
    // Each data field has an associated valid flag to indicate
    // whether the data field is valid.
 
    /*** @defgroup mem
     * @{
     * Memory request information in the instruction accessed memory.
     * @see mem_valid
     */
    Addr addr; 
    Addr size; 
    unsigned flags; 
 
    union
    {
        uint64_t as_int;
        double as_double;
        TheISA::VecRegContainer* as_vec;
        TheISA::VecPredRegContainer* as_pred;
    } data;
 
    InstSeqNum fetch_seq;
 
    InstSeqNum cp_seq;
 
    enum DataStatus
    {
        DataInvalid = 0,
        DataInt8 = 1,   // set to equal number of bytes
        DataInt16 = 2,
        DataInt32 = 4,
        DataInt64 = 8,
        DataDouble = 3,
        DataVec = 5,
        DataVecPred = 6
    } data_status;
 
    bool mem_valid;
 
    bool fetch_seq_valid;
    bool cp_seq_valid;
 
    bool predicate;
 
    bool faulting;
 
  public:
    InstRecord(Tick _when, ThreadContext *_thread,
               const StaticInstPtr _staticInst,
               TheISA::PCState _pc,
               const StaticInstPtr _macroStaticInst = NULL)
        : when(_when), thread(_thread), staticInst(_staticInst), pc(_pc),
        macroStaticInst(_macroStaticInst), addr(0), size(0), flags(0),
        fetch_seq(0), cp_seq(0), data_status(DataInvalid), mem_valid(false),
        fetch_seq_valid(false), cp_seq_valid(false), predicate(true),
        faulting(false)
    { }
 
    virtual ~InstRecord()
    {
        if (data_status == DataVec) {
            assert(data.as_vec);
            delete data.as_vec;
        } else if (data_status == DataVecPred) {
            assert(data.as_pred);
            delete data.as_pred;
        }
    }
 
    void setWhen(Tick new_when) { when = new_when; }
    void setMem(Addr a, Addr s, unsigned f)
    {
        addr = a; size = s; flags = f; mem_valid = true;
    }
 
    template <typename T, size_t N>
    void
    setData(std::array<T, N> d)
    {
        data.as_int = d[0];
        data_status = (DataStatus)sizeof(T);
        static_assert(sizeof(T) == DataInt8 || sizeof(T) == DataInt16 ||
                      sizeof(T) == DataInt32 || sizeof(T) == DataInt64,
                      "Type T has an unrecognized size.");
    }
 
    void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
    void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
    void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
    void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
 
    void setData(int64_t d) { setData((uint64_t)d); }
    void setData(int32_t d) { setData((uint32_t)d); }
    void setData(int16_t d) { setData((uint16_t)d); }
    void setData(int8_t d)  { setData((uint8_t)d); }
 
    void setData(double d) { data.as_double = d; data_status = DataDouble; }
 
    void
    setData(TheISA::VecRegContainer& d)
    {
        data.as_vec = new TheISA::VecRegContainer(d);
        data_status = DataVec;
    }
 
    void
    setData(TheISA::VecPredRegContainer& d)
    {
        data.as_pred = new TheISA::VecPredRegContainer(d);
        data_status = DataVecPred;
    }
 
    void setFetchSeq(InstSeqNum seq)
    { fetch_seq = seq; fetch_seq_valid = true; }
 
    void setCPSeq(InstSeqNum seq)
    { cp_seq = seq; cp_seq_valid = true; }
 
    void setPredicate(bool val) { predicate = val; }
 
    void setFaulting(bool val) { faulting = val; }
 
    virtual void dump() = 0;
 
  public:
    Tick getWhen() const { return when; }
    ThreadContext *getThread() const { return thread; }
    StaticInstPtr getStaticInst() const { return staticInst; }
    TheISA::PCState getPCState() const { return pc; }
    StaticInstPtr getMacroStaticInst() const { return macroStaticInst; }
 
    Addr getAddr() const { return addr; }
    Addr getSize() const { return size; }
    unsigned getFlags() const { return flags; }
    bool getMemValid() const { return mem_valid; }
 
    uint64_t getIntData() const { return data.as_int; }
    double getFloatData() const { return data.as_double; }
    int getDataStatus() const { return data_status; }
 
    InstSeqNum getFetchSeq() const { return fetch_seq; }
    bool getFetchSeqValid() const { return fetch_seq_valid; }
 
    InstSeqNum getCpSeq() const { return cp_seq; }
    bool getCpSeqValid() const { return cp_seq_valid; }
 
    bool getFaulting() const { return faulting; }
};
 
class InstTracer : public SimObject
{
  public:
    InstTracer(const Params &p) : SimObject(p)
    {}
 
    virtual ~InstTracer()
    {};
 
    virtual InstRecord *
        getInstRecord(Tick when, ThreadContext *tc,
                const StaticInstPtr staticInst, TheISA::PCState pc,
                const StaticInstPtr macroStaticInst = NULL) = 0;
};
 
} // namespace Trace
} // namespace gem5
 
#endif // __INSTRECORD_HH__