lsq_unit.hh

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#ifndef __CPU_O3_LSQ_UNIT_HH__
#define __CPU_O3_LSQ_UNIT_HH__
 
#include <algorithm>
#include <cstring>
#include <map>
#include <memory>
#include <queue>
 
#include "arch/generic/debugfaults.hh"
#include "arch/generic/vec_reg.hh"
#include "arch/locked_mem.hh"
#include "base/circular_queue.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/cpu.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/o3/lsq.hh"
#include "cpu/timebuf.hh"
#include "debug/HtmCpu.hh"
#include "debug/LSQUnit.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
 
namespace gem5
{
 
struct O3CPUParams;
 
namespace o3
{
 
class IEW;
 
class LSQUnit
{
  public:
    static constexpr auto MaxDataBytes = MaxVecRegLenInBytes;
 
    using LSQSenderState = LSQ::LSQSenderState;
    using LSQRequest = LSQ::LSQRequest;
  private:
    class LSQEntry
    {
      private:
        DynInstPtr inst;
        LSQRequest* req = nullptr;
        uint32_t _size = 0;
        bool _valid = false;
 
      public:
        ~LSQEntry()
        {
            if (req != nullptr) {
                req->freeLSQEntry();
                req = nullptr;
            }
        }
 
        void
        clear()
        {
            inst = nullptr;
            if (req != nullptr) {
                req->freeLSQEntry();
            }
            req = nullptr;
            _valid = false;
            _size = 0;
        }
 
        void
        set(const DynInstPtr& new_inst)
        {
            assert(!_valid);
            inst = new_inst;
            _valid = true;
            _size = 0;
        }
 
        LSQRequest* request() { return req; }
        void setRequest(LSQRequest* r) { req = r; }
        bool hasRequest() { return req != nullptr; }
        bool valid() const { return _valid; }
        uint32_t& size() { return _size; }
        const uint32_t& size() const { return _size; }
        const DynInstPtr& instruction() const { return inst; }
    };
 
    class SQEntry : public LSQEntry
    {
      private:
        char _data[MaxDataBytes];
        bool _canWB = false;
        bool _committed = false;
        bool _completed = false;
        bool _isAllZeros = false;
 
      public:
        static constexpr size_t DataSize = sizeof(_data);
        SQEntry()
        {
            std::memset(_data, 0, DataSize);
        }
 
        void set(const DynInstPtr& inst) { LSQEntry::set(inst); }
 
        void
        clear()
        {
            LSQEntry::clear();
            _canWB = _completed = _committed = _isAllZeros = false;
        }
 
        bool& canWB() { return _canWB; }
        const bool& canWB() const { return _canWB; }
        bool& completed() { return _completed; }
        const bool& completed() const { return _completed; }
        bool& committed() { return _committed; }
        const bool& committed() const { return _committed; }
        bool& isAllZeros() { return _isAllZeros; }
        const bool& isAllZeros() const { return _isAllZeros; }
        char* data() { return _data; }
        const char* data() const { return _data; }
    };
    using LQEntry = LSQEntry;
 
    enum class AddrRangeCoverage
    {
        PartialAddrRangeCoverage, /* Two ranges partly overlap */
        FullAddrRangeCoverage, /* One range fully covers another */
        NoAddrRangeCoverage /* Two ranges are disjoint */
    };
 
  public:
    using LoadQueue = CircularQueue<LQEntry>;
    using StoreQueue = CircularQueue<SQEntry>;
 
  public:
    LSQUnit(uint32_t lqEntries, uint32_t sqEntries);
 
    LSQUnit(const LSQUnit &l): stats(nullptr)
    {
        panic("LSQUnit is not copy-able");
    }
 
    void init(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams &params,
            LSQ *lsq_ptr, unsigned id);
 
    std::string name() const;
 
    void setDcachePort(RequestPort *dcache_port);
 
    void drainSanityCheck() const;
 
    void takeOverFrom();
 
    void insert(const DynInstPtr &inst);
    void insertLoad(const DynInstPtr &load_inst);
    void insertStore(const DynInstPtr &store_inst);
 
    Fault checkViolations(typename LoadQueue::iterator& loadIt,
            const DynInstPtr& inst);
 
    void checkSnoop(PacketPtr pkt);
 
    Fault executeLoad(const DynInstPtr &inst);
 
    Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
    Fault executeStore(const DynInstPtr &inst);
 
    void commitLoad();
    void commitLoads(InstSeqNum &youngest_inst);
 
    void commitStores(InstSeqNum &youngest_inst);
 
    void writebackStores();
 
    void completeDataAccess(PacketPtr pkt);
 
    void squash(const InstSeqNum &squashed_num);
 
    bool violation() { return memDepViolator; }
 
    DynInstPtr getMemDepViolator();
 
    unsigned numFreeLoadEntries();
 
    unsigned numFreeStoreEntries();
 
    int numLoads() { return loads; }
 
    int numStores() { return stores; }
 
    // hardware transactional memory
    int numHtmStarts() const { return htmStarts; }
    int numHtmStops() const { return htmStops; }
    void resetHtmStartsStops() { htmStarts = htmStops = 0; }
    uint64_t getLatestHtmUid() const;
    void
    setLastRetiredHtmUid(uint64_t htm_uid)
    {
        assert(htm_uid >= lastRetiredHtmUid);
        lastRetiredHtmUid = htm_uid;
    }
 
    bool isFull() { return lqFull() || sqFull(); }
 
    bool isEmpty() const { return lqEmpty() && sqEmpty(); }
 
    bool lqFull() { return loadQueue.full(); }
 
    bool sqFull() { return storeQueue.full(); }
 
    bool lqEmpty() const { return loads == 0; }
 
    bool sqEmpty() const { return stores == 0; }
 
    unsigned getCount() { return loads + stores; }
 
    bool hasStoresToWB() { return storesToWB; }
 
    int numStoresToWB() { return storesToWB; }
 
    bool
    willWB()
    {
        return storeWBIt.dereferenceable() &&
                        storeWBIt->valid() &&
                        storeWBIt->canWB() &&
                        !storeWBIt->completed() &&
                        !isStoreBlocked;
    }
 
    void recvRetry();
 
    unsigned int cacheLineSize();
  private:
    void resetState();
 
    void writeback(const DynInstPtr &inst, PacketPtr pkt);
 
    void writebackBlockedStore();
 
    void completeStore(typename StoreQueue::iterator store_idx);
 
    void storePostSend();
 
  public:
    bool trySendPacket(bool isLoad, PacketPtr data_pkt);
 
 
    void dumpInsts() const;
 
    void schedule(Event& ev, Tick when);
 
    BaseMMU *getMMUPtr();
 
  private:
    CPU *cpu;
 
    IEW *iewStage;
 
    LSQ *lsq;
 
    RequestPort *dcachePort;
 
    class LQSenderState : public LSQSenderState
    {
        using LSQSenderState::alive;
      public:
        LQSenderState(typename LoadQueue::iterator idx_)
            : LSQSenderState(idx_->request(), true), idx(idx_) { }
 
        typename LoadQueue::iterator idx;
        //virtual LSQRequest* request() { return idx->request(); }
        virtual void
        complete()
        {
            //if (alive())
            //  idx->request()->senderState(nullptr);
        }
    };
 
    class SQSenderState : public LSQSenderState
    {
        using LSQSenderState::alive;
      public:
        SQSenderState(typename StoreQueue::iterator idx_)
            : LSQSenderState(idx_->request(), false), idx(idx_) { }
        typename StoreQueue::iterator idx;
        //virtual LSQRequest* request() { return idx->request(); }
        virtual void
        complete()
        {
            //if (alive())
            //   idx->request()->senderState(nullptr);
        }
    };
 
    class WritebackEvent : public Event
    {
      public:
        WritebackEvent(const DynInstPtr &_inst, PacketPtr pkt,
                LSQUnit *lsq_ptr);
 
        void process();
 
        const char *description() const;
 
      private:
        DynInstPtr inst;
 
        PacketPtr pkt;
 
        LSQUnit *lsqPtr;
    };
 
  public:
    bool recvTimingResp(PacketPtr pkt);
 
  private:
    ThreadID lsqID;
  public:
    CircularQueue<SQEntry> storeQueue;
 
    LoadQueue loadQueue;
 
  private:
    unsigned depCheckShift;
 
    bool checkLoads;
 
    int loads;
    int stores;
    int storesToWB;
 
    // hardware transactional memory
    // nesting depth
    int htmStarts;
    int htmStops;
    // sanity checks and debugging
    uint64_t lastRetiredHtmUid;
 
    typename StoreQueue::iterator storeWBIt;
 
    Addr cacheBlockMask;
 
    typename TimeBuffer<IssueStruct>::wire fromIssue;
 
    bool stalled;
    InstSeqNum stallingStoreIsn;
    int stallingLoadIdx;
 
    PacketPtr retryPkt;
 
    bool isStoreBlocked;
 
    bool storeInFlight;
 
    DynInstPtr memDepViolator;
 
    bool needsTSO;
 
  protected:
    // Will also need how many read/write ports the Dcache has.  Or keep track
    // of that in stage that is one level up, and only call executeLoad/Store
    // the appropriate number of times.
    struct LSQUnitStats : public statistics::Group
    {
        LSQUnitStats(statistics::Group *parent);
 
        statistics::Scalar forwLoads;
 
        statistics::Scalar squashedLoads;
 
        statistics::Scalar ignoredResponses;
 
        statistics::Scalar memOrderViolation;
 
        statistics::Scalar squashedStores;
 
        statistics::Scalar rescheduledLoads;
 
        statistics::Scalar blockedByCache;
 
        statistics::Distribution loadToUse;
    } stats;
 
  public:
    Fault read(LSQRequest *req, int load_idx);
 
    Fault write(LSQRequest *req, uint8_t *data, int store_idx);
 
    int getLoadHead() { return loadQueue.head(); }
 
    InstSeqNum getLoadHeadSeqNum();
 
    int getStoreHead() { return storeQueue.head(); }
    InstSeqNum getStoreHeadSeqNum();
 
    bool isStalled()  { return stalled; }
  public:
    typedef typename CircularQueue<LQEntry>::iterator LQIterator;
    typedef typename CircularQueue<SQEntry>::iterator SQIterator;
    typedef CircularQueue<LQEntry> LQueue;
    typedef CircularQueue<SQEntry> SQueue;
};
 
} // namespace o3
} // namespace gem5
 
#endif // __CPU_O3_LSQ_UNIT_HH__