gem5  v21.1.0.1
•All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
mem0.h
Go to the documentation of this file.
1 /*****************************************************************************
2 
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements. See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License. You may obtain a copy of the License at
9 
10  http://www.apache.org/licenses/LICENSE-2.0
11 
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied. See the License for the specific language governing
16  permissions and limitations under the License.
17 
18  *****************************************************************************/
19 
20 /*****************************************************************************
21 
22  mem0.h --
23 
24  Original Author: Stan Liao, Synopsys, Inc., 2000-09-19
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 typedef sc_signal<sc_bv<8> > sc_signal_bool_vector;
39 
40 
41 SC_MODULE( mem0 )
42 {
43  SC_HAS_PROCESS( mem0 );
44 
45  sc_in_clk clk;
46 
47  //====================================================================
48  // [C] Always Needed Member Function
49  // -- constructor
50  // -- entry
51  //====================================================================
52 
53  const sc_signal<bool>& reset ;
54  const sc_signal_bool_vector& in_value1; // Input port
55  const sc_signal_bool_vector& in_value2 ; // Input port
56  const sc_signal<bool>& in_valid; // Input port
57  sc_signal_bool_vector& out_value1; // Output port
58  sc_signal_bool_vector& out_value2; // Output port
59  sc_signal<bool>& out_valid; // Output port
60  int* memory;
61 
62 int test;
63  //
64  // Constructor
65  //
66 
67  mem0 (
68  sc_module_name NAME, // referense name
69  sc_clock& CLK, // clock
70  const sc_signal<bool>& RESET,
71  const sc_signal_bool_vector& IN_VALUE1,
72  const sc_signal_bool_vector& IN_VALUE2,
73  const sc_signal<bool>& IN_VALID, // Input port
74  sc_signal_bool_vector& OUT_VALUE1,
75  sc_signal_bool_vector& OUT_VALUE2,
76  sc_signal<bool>& OUT_VALID, // Output port
77  int *MEMORY // Output port
78  )
79  :
80  reset (RESET),
81  in_value1 (IN_VALUE1),
82  in_value2 (IN_VALUE2),
83  in_valid (IN_VALID),
84  out_value1 (OUT_VALUE1),
85  out_value2 (OUT_VALUE2),
86  out_valid (OUT_VALID),
87  memory (MEMORY)
88 
89  {
90  clk (CLK);
91  SC_CTHREAD( entry, clk.pos() );
92  reset_signal_is(reset,true);
93  };
94 
95  //
96  void entry ();
97 };
98 
99 // EOF
SC_MODULE
SC_MODULE(mem0)
Definition: mem0.h:41
memory
Definition: mem.h:38
test
Definition: test.h:38
sc_signal_bool_vector
sc_signal< sc_bv< 8 > > sc_signal_bool_vector
Definition: common.h:43
gem5::statistics::reset
void reset()
Definition: statistics.cc:304
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
sc_signal_bool_vector
sc_signal< sc_bv< 8 > > sc_signal_bool_vector
Definition: mem0.h:38
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:298
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:320
Generated on Tue Sep 7 2021 14:53:52 for gem5 by doxygen 1.8.17