mem_ctrl.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2012-2020 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2013 Amin Farmahini-Farahani
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __MEM_CTRL_HH__
#define __MEM_CTRL_HH__
 
#include <deque>
#include <string>
#include <unordered_set>
#include <utility>
#include <vector>
 
#include "base/callback.hh"
#include "base/statistics.hh"
#include "enums/MemSched.hh"
#include "mem/qos/mem_ctrl.hh"
#include "mem/qport.hh"
#include "params/MemCtrl.hh"
#include "sim/eventq.hh"
 
namespace gem5
{
 
namespace memory
{
 
class DRAMInterface;
class NVMInterface;
 
class BurstHelper
{
  public:
 
    const unsigned int burstCount;
 
    unsigned int burstsServiced;
 
    BurstHelper(unsigned int _burstCount)
        : burstCount(_burstCount), burstsServiced(0)
    { }
};
 
class MemPacket
{
  public:
 
    const Tick entryTime;
 
    Tick readyTime;
 
    const PacketPtr pkt;
 
    const RequestorID _requestorId;
 
    const bool read;
 
    const bool dram;
 
    const uint8_t rank;
    const uint8_t bank;
    const uint32_t row;
 
    const uint16_t bankId;
 
    Addr addr;
 
    unsigned int size;
 
    BurstHelper* burstHelper;
 
    uint8_t _qosValue;
 
    inline void qosValue(const uint8_t qv) { _qosValue = qv; }
 
    inline uint8_t qosValue() const { return _qosValue; }
 
    inline RequestorID requestorId() const { return _requestorId; }
 
    inline unsigned int getSize() const { return size; }
 
    inline Addr getAddr() const { return addr; }
 
    inline bool isRead() const { return read; }
 
    inline bool isWrite() const { return !read; }
 
    inline bool isDram() const { return dram; }
 
    MemPacket(PacketPtr _pkt, bool is_read, bool is_dram, uint8_t _rank,
               uint8_t _bank, uint32_t _row, uint16_t bank_id, Addr _addr,
               unsigned int _size)
        : entryTime(curTick()), readyTime(curTick()), pkt(_pkt),
          _requestorId(pkt->requestorId()),
          read(is_read), dram(is_dram), rank(_rank), bank(_bank), row(_row),
          bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
          _qosValue(_pkt->qosValue())
    { }
 
};
 
// The memory packets are store in a multiple dequeue structure,
// based on their QoS priority
typedef std::deque<MemPacket*> MemPacketQueue;
 
 
class MemCtrl : public qos::MemCtrl
{
  private:
 
    // For now, make use of a queued response port to avoid dealing with
    // flow control for the responses being sent back
    class MemoryPort : public QueuedResponsePort
    {
 
        RespPacketQueue queue;
        MemCtrl& ctrl;
 
      public:
 
        MemoryPort(const std::string& name, MemCtrl& _ctrl);
 
      protected:
 
        Tick recvAtomic(PacketPtr pkt) override;
        Tick recvAtomicBackdoor(
                PacketPtr pkt, MemBackdoorPtr &backdoor) override;
 
        void recvFunctional(PacketPtr pkt) override;
 
        bool recvTimingReq(PacketPtr) override;
 
        AddrRangeList getAddrRanges() const override;
 
    };
 
    MemoryPort port;
 
    bool isTimingMode;
 
    bool retryRdReq;
    bool retryWrReq;
 
    void processNextReqEvent();
    EventFunctionWrapper nextReqEvent;
 
    void processRespondEvent();
    EventFunctionWrapper respondEvent;
 
    bool readQueueFull(unsigned int pkt_count) const;
 
    bool writeQueueFull(unsigned int pkt_count) const;
 
    void addToReadQueue(PacketPtr pkt, unsigned int pkt_count, bool is_dram);
 
    void addToWriteQueue(PacketPtr pkt, unsigned int pkt_count, bool is_dram);
 
    void doBurstAccess(MemPacket* mem_pkt);
 
    void accessAndRespond(PacketPtr pkt, Tick static_latency);
 
    bool packetReady(MemPacket* pkt);
 
    Tick minReadToWriteDataGap();
 
    Tick minWriteToReadDataGap();
 
    MemPacketQueue::iterator chooseNext(MemPacketQueue& queue,
        Tick extra_col_delay);
 
    MemPacketQueue::iterator chooseNextFRFCFS(MemPacketQueue& queue,
            Tick extra_col_delay);
 
    Tick getBurstWindow(Tick cmd_tick);
 
    void printQs() const;
 
    Addr burstAlign(Addr addr, bool is_dram) const;
 
    std::vector<MemPacketQueue> readQueue;
    std::vector<MemPacketQueue> writeQueue;
 
    std::unordered_set<Addr> isInWriteQueue;
 
    std::deque<MemPacket*> respQueue;
 
    std::unordered_multiset<Tick> burstTicks;
 
    DRAMInterface* const dram;
 
    NVMInterface* const nvm;
 
    const uint32_t readBufferSize;
    const uint32_t writeBufferSize;
    const uint32_t writeHighThreshold;
    const uint32_t writeLowThreshold;
    const uint32_t minWritesPerSwitch;
    uint32_t writesThisTime;
    uint32_t readsThisTime;
 
    enums::MemSched memSchedPolicy;
 
    const Tick frontendLatency;
 
    const Tick backendLatency;
 
    const Tick commandWindow;
 
    Tick nextBurstAt;
 
    Tick prevArrival;
 
    Tick nextReqTime;
 
    struct CtrlStats : public statistics::Group
    {
        CtrlStats(MemCtrl &ctrl);
 
        void regStats() override;
 
        MemCtrl &ctrl;
 
        // All statistics that the model needs to capture
        statistics::Scalar readReqs;
        statistics::Scalar writeReqs;
        statistics::Scalar readBursts;
        statistics::Scalar writeBursts;
        statistics::Scalar servicedByWrQ;
        statistics::Scalar mergedWrBursts;
        statistics::Scalar neitherReadNorWriteReqs;
        // Average queue lengths
        statistics::Average avgRdQLen;
        statistics::Average avgWrQLen;
 
        statistics::Scalar numRdRetry;
        statistics::Scalar numWrRetry;
        statistics::Vector readPktSize;
        statistics::Vector writePktSize;
        statistics::Vector rdQLenPdf;
        statistics::Vector wrQLenPdf;
        statistics::Histogram rdPerTurnAround;
        statistics::Histogram wrPerTurnAround;
 
        statistics::Scalar bytesReadWrQ;
        statistics::Scalar bytesReadSys;
        statistics::Scalar bytesWrittenSys;
        // Average bandwidth
        statistics::Formula avgRdBWSys;
        statistics::Formula avgWrBWSys;
 
        statistics::Scalar totGap;
        statistics::Formula avgGap;
 
        // per-requestor bytes read and written to memory
        statistics::Vector requestorReadBytes;
        statistics::Vector requestorWriteBytes;
 
        // per-requestor bytes read and written to memory rate
        statistics::Formula requestorReadRate;
        statistics::Formula requestorWriteRate;
 
        // per-requestor read and write serviced memory accesses
        statistics::Vector requestorReadAccesses;
        statistics::Vector requestorWriteAccesses;
 
        // per-requestor read and write total memory access latency
        statistics::Vector requestorReadTotalLat;
        statistics::Vector requestorWriteTotalLat;
 
        // per-requestor raed and write average memory access latency
        statistics::Formula requestorReadAvgLat;
        statistics::Formula requestorWriteAvgLat;
    };
 
    CtrlStats stats;
 
    std::unique_ptr<Packet> pendingDelete;
 
    std::vector<MemPacketQueue>& selQueue(bool is_read)
    {
        return (is_read ? readQueue : writeQueue);
    };
 
    void pruneBurstTick();
 
  public:
 
    MemCtrl(const MemCtrlParams &p);
 
    bool allIntfDrained() const;
 
    DrainState drain() override;
 
    Tick verifySingleCmd(Tick cmd_tick, Tick max_cmds_per_burst);
 
    Tick verifyMultiCmd(Tick cmd_tick, Tick max_cmds_per_burst,
                        Tick max_multi_cmd_split = 0);
 
    bool respondEventScheduled() const { return respondEvent.scheduled(); }
 
    bool requestEventScheduled() const { return nextReqEvent.scheduled(); }
 
    void restartScheduler(Tick tick) { schedule(nextReqEvent, tick); }
 
    bool inReadBusState(bool next_state) const;
 
    bool inWriteBusState(bool next_state) const;
 
    Port &getPort(const std::string &if_name,
                  PortID idx=InvalidPortID) override;
 
    virtual void init() override;
    virtual void startup() override;
    virtual void drainResume() override;
 
  protected:
 
    Tick recvAtomic(PacketPtr pkt);
    Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor);
    void recvFunctional(PacketPtr pkt);
    bool recvTimingReq(PacketPtr pkt);
 
};
 
} // namespace memory
} // namespace gem5
 
#endif //__MEM_CTRL_HH__