pred_inst.cc

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/*
 * Copyright (c) 2010 ARM Limited
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 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2007-2008 The Florida State University
 * All rights reserved.
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
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#include "arch/arm/insts/pred_inst.hh"
 
namespace gem5
{
 
namespace ArmISA
{
std::string
PredIntOp::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    unsigned rotate = machInst.rotate * 2;
    uint32_t imm = machInst.imm;
    imm = (imm << (32 - rotate)) | (imm >> rotate);
    printDataInst(ss, false, machInst.opcode4 == 0, machInst.sField,
            (IntRegIndex)(uint32_t)machInst.rd,
            (IntRegIndex)(uint32_t)machInst.rn,
            (IntRegIndex)(uint32_t)machInst.rm,
            (IntRegIndex)(uint32_t)machInst.rs,
            machInst.shiftSize, (ArmShiftType)(uint32_t)machInst.shift,
            imm);
    return ss.str();
}
 
std::string
PredImmOp::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printDataInst(ss, true, machInst.opcode4 == 0, machInst.sField,
            (IntRegIndex)(uint32_t)machInst.rd,
            (IntRegIndex)(uint32_t)machInst.rn,
            (IntRegIndex)(uint32_t)machInst.rm,
            (IntRegIndex)(uint32_t)machInst.rs,
            machInst.shiftSize, (ArmShiftType)(uint32_t)machInst.shift,
            imm);
    return ss.str();
}
 
std::string
DataImmOp::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1,
                  INTREG_ZERO, INTREG_ZERO, 0, LSL, imm);
    return ss.str();
}
 
std::string
DataRegOp::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
                  op2, INTREG_ZERO, shiftAmt, shiftType, 0);
    return ss.str();
}
 
std::string
DataRegRegOp::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printDataInst(ss, false, false, /*XXX not really s*/ false, dest, op1,
                  op2, shift, 0, shiftType, 0);
    return ss.str();
}
 
std::string
PredMacroOp::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
 
    ccprintf(ss, "%-10s ", mnemonic);
 
    return ss.str();
}
 
} // namespace ArmISA
} // namespace gem5