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sinicreg.hh
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28 
29 #ifndef __DEV_NET_SINICREG_HH__
30 #define __DEV_NET_SINICREG_HH__
31 
32 #include <cstdint>
33 
34 #include "base/compiler.hh"
35 
36 #define __SINIC_REG32(NAME, VAL) static const uint32_t NAME = (VAL);
37 #define __SINIC_REG64(NAME, VAL) static const uint64_t NAME = (VAL);
38 
39 #define __SINIC_VAL32(NAME, OFFSET, WIDTH) \
40  static const uint32_t NAME##_width = WIDTH; \
41  static const uint32_t NAME##_offset = OFFSET; \
42  static const uint32_t NAME##_mask = (1 << WIDTH) - 1; \
43  static const uint32_t NAME = ((1 << WIDTH) - 1) << OFFSET; \
44  static inline uint32_t get_##NAME(uint32_t reg) \
45  { return (reg & NAME) >> OFFSET; } \
46  static inline uint32_t set_##NAME(uint32_t reg, uint32_t val) \
47  { return (reg & ~NAME) | ((val << OFFSET) & NAME); }
48 
49 #define __SINIC_VAL64(NAME, OFFSET, WIDTH) \
50  static const uint64_t NAME##_width = WIDTH; \
51  static const uint64_t NAME##_offset = OFFSET; \
52  static const uint64_t NAME##_mask = (1ULL << WIDTH) - 1; \
53  static const uint64_t NAME = ((1ULL << WIDTH) - 1) << OFFSET; \
54  static inline uint64_t get_##NAME(uint64_t reg) \
55  { return (reg & NAME) >> OFFSET; } \
56  static inline uint64_t set_##NAME(uint64_t reg, uint64_t val) \
57  { return (reg & ~NAME) | ((val << OFFSET) & NAME); }
58 
59 namespace gem5
60 {
61 
62 GEM5_DEPRECATED_NAMESPACE(Sinic, sinic);
63 namespace sinic
64 {
65 
66 GEM5_DEPRECATED_NAMESPACE(Regs, registers);
67 namespace registers
68 {
69 
70 static const int VirtualShift = 8;
71 static const int VirtualMask = 0xff;
72 
73 // Registers
74 __SINIC_REG32(Config, 0x00) // 32: configuration register
75 __SINIC_REG32(Command, 0x04) // 32: command register
76 __SINIC_REG32(IntrStatus, 0x08) // 32: interrupt status
77 __SINIC_REG32(IntrMask, 0x0c) // 32: interrupt mask
78 __SINIC_REG32(RxMaxCopy, 0x10) // 32: max bytes per rx copy
79 __SINIC_REG32(TxMaxCopy, 0x14) // 32: max bytes per tx copy
80 __SINIC_REG32(ZeroCopySize, 0x18) // 32: bytes to copy if below threshold
81 __SINIC_REG32(ZeroCopyMark, 0x1c) // 32: only zero-copy above this threshold
82 __SINIC_REG32(VirtualCount, 0x20) // 32: number of virutal NICs
83 __SINIC_REG32(RxMaxIntr, 0x24) // 32: max receives per interrupt
84 __SINIC_REG32(RxFifoSize, 0x28) // 32: rx fifo capacity in bytes
85 __SINIC_REG32(TxFifoSize, 0x2c) // 32: tx fifo capacity in bytes
86 __SINIC_REG32(RxFifoLow, 0x30) // 32: rx fifo low watermark
87 __SINIC_REG32(TxFifoLow, 0x34) // 32: tx fifo low watermark
88 __SINIC_REG32(RxFifoHigh, 0x38) // 32: rx fifo high watermark
89 __SINIC_REG32(TxFifoHigh, 0x3c) // 32: tx fifo high watermark
90 __SINIC_REG32(RxData, 0x40) // 64: receive data
91 __SINIC_REG32(RxDone, 0x48) // 64: receive done
92 __SINIC_REG32(RxWait, 0x50) // 64: receive done (busy wait)
93 __SINIC_REG32(TxData, 0x58) // 64: transmit data
94 __SINIC_REG32(TxDone, 0x60) // 64: transmit done
95 __SINIC_REG32(TxWait, 0x68) // 64: transmit done (busy wait)
96 __SINIC_REG32(HwAddr, 0x70) // 64: mac address
97 __SINIC_REG32(RxStatus, 0x78)
98 __SINIC_REG32(Size, 0x80) // register addres space size
99 
100 // Config register bits
101 __SINIC_VAL32(Config_ZeroCopy, 12, 1) // enable zero copy
102 __SINIC_VAL32(Config_DelayCopy,11, 1) // enable delayed copy
103 __SINIC_VAL32(Config_RSS, 10, 1) // enable receive side scaling
104 __SINIC_VAL32(Config_RxThread, 9, 1) // enable receive threads
105 __SINIC_VAL32(Config_TxThread, 8, 1) // enable transmit thread
106 __SINIC_VAL32(Config_Filter, 7, 1) // enable receive filter
107 __SINIC_VAL32(Config_Vlan, 6, 1) // enable vlan tagging
108 __SINIC_VAL32(Config_Vaddr, 5, 1) // enable virtual addressing
109 __SINIC_VAL32(Config_Desc, 4, 1) // enable tx/rx descriptors
110 __SINIC_VAL32(Config_Poll, 3, 1) // enable polling
111 __SINIC_VAL32(Config_IntEn, 2, 1) // enable interrupts
112 __SINIC_VAL32(Config_TxEn, 1, 1) // enable transmit
113 __SINIC_VAL32(Config_RxEn, 0, 1) // enable receive
114 
115 // Command register bits
116 __SINIC_VAL32(Command_Intr, 1, 1) // software interrupt
117 __SINIC_VAL32(Command_Reset, 0, 1) // reset chip
118 
119 // Interrupt register bits
120 __SINIC_VAL32(Intr_Soft, 8, 1) // software interrupt
121 __SINIC_VAL32(Intr_TxLow, 7, 1) // tx fifo dropped below watermark
122 __SINIC_VAL32(Intr_TxFull, 6, 1) // tx fifo full
123 __SINIC_VAL32(Intr_TxDMA, 5, 1) // tx dma completed w/ interrupt
124 __SINIC_VAL32(Intr_TxPacket, 4, 1) // packet transmitted
125 __SINIC_VAL32(Intr_RxHigh, 3, 1) // rx fifo above high watermark
126 __SINIC_VAL32(Intr_RxEmpty, 2, 1) // rx fifo empty
127 __SINIC_VAL32(Intr_RxDMA, 1, 1) // rx dma completed w/ interrupt
128 __SINIC_VAL32(Intr_RxPacket, 0, 1) // packet received
129 __SINIC_REG32(Intr_All, 0x01ff) // all valid interrupts
130 __SINIC_REG32(Intr_NoDelay, 0x01cc) // interrupts that aren't coalesced
131 __SINIC_REG32(Intr_Res, ~0x01ff) // reserved interrupt bits
132 
133 // RX Data Description
134 __SINIC_VAL64(RxData_NoDelay, 61, 1) // Don't Delay this copy
135 __SINIC_VAL64(RxData_Vaddr, 60, 1) // Addr is virtual
136 __SINIC_VAL64(RxData_Len, 40, 20) // 0 - 256k
137 __SINIC_VAL64(RxData_Addr, 0, 40) // Address 1TB
138 
139 // TX Data Description
140 __SINIC_VAL64(TxData_More, 63, 1) // Packet not complete (will dma more)
141 __SINIC_VAL64(TxData_Checksum, 62, 1) // do checksum
142 __SINIC_VAL64(TxData_Vaddr, 60, 1) // Addr is virtual
143 __SINIC_VAL64(TxData_Len, 40, 20) // 0 - 256k
144 __SINIC_VAL64(TxData_Addr, 0, 40) // Address 1TB
145 
146 // RX Done/Busy Information
147 __SINIC_VAL64(RxDone_Packets, 32, 16) // number of packets in rx fifo
148 __SINIC_VAL64(RxDone_Busy, 31, 1) // receive dma busy copying
149 __SINIC_VAL64(RxDone_Complete, 30, 1) // valid data (packet complete)
150 __SINIC_VAL64(RxDone_More, 29, 1) // Packet has more data (dma again)
151 __SINIC_VAL64(RxDone_Empty, 28, 1) // rx fifo is empty
152 __SINIC_VAL64(RxDone_High, 27, 1) // rx fifo is above the watermark
153 __SINIC_VAL64(RxDone_NotHigh, 26, 1) // rxfifo never hit the high watermark
154 __SINIC_VAL64(RxDone_TcpError, 25, 1) // TCP packet error (bad checksum)
155 __SINIC_VAL64(RxDone_UdpError, 24, 1) // UDP packet error (bad checksum)
156 __SINIC_VAL64(RxDone_IpError, 23, 1) // IP packet error (bad checksum)
157 __SINIC_VAL64(RxDone_TcpPacket, 22, 1) // this is a TCP packet
158 __SINIC_VAL64(RxDone_UdpPacket, 21, 1) // this is a UDP packet
159 __SINIC_VAL64(RxDone_IpPacket, 20, 1) // this is an IP packet
160 __SINIC_VAL64(RxDone_CopyLen, 0, 20) // up to 256k
161 
162 // TX Done/Busy Information
163 __SINIC_VAL64(TxDone_Packets, 32, 16) // number of packets in tx fifo
164 __SINIC_VAL64(TxDone_Busy, 31, 1) // transmit dma busy copying
165 __SINIC_VAL64(TxDone_Complete, 30, 1) // valid data (packet complete)
166 __SINIC_VAL64(TxDone_Full, 29, 1) // tx fifo is full
167 __SINIC_VAL64(TxDone_Low, 28, 1) // tx fifo is below the watermark
168 __SINIC_VAL64(TxDone_Res0, 27, 1) // reserved
169 __SINIC_VAL64(TxDone_Res1, 26, 1) // reserved
170 __SINIC_VAL64(TxDone_Res2, 25, 1) // reserved
171 __SINIC_VAL64(TxDone_Res3, 24, 1) // reserved
172 __SINIC_VAL64(TxDone_Res4, 23, 1) // reserved
173 __SINIC_VAL64(TxDone_Res5, 22, 1) // reserved
174 __SINIC_VAL64(TxDone_Res6, 21, 1) // reserved
175 __SINIC_VAL64(TxDone_Res7, 20, 1) // reserved
176 __SINIC_VAL64(TxDone_CopyLen, 0, 20) // up to 256k
177 
178 __SINIC_VAL64(RxStatus_Dirty, 48, 16)
179 __SINIC_VAL64(RxStatus_Mapped, 32, 16)
180 __SINIC_VAL64(RxStatus_Busy, 16, 16)
181 __SINIC_VAL64(RxStatus_Head, 0, 16)
182 
183 struct Info
184 {
185  uint8_t size;
186  bool read;
187  bool write;
188  const char *name;
189 };
190 
191 } // namespace registers
192 
193 inline const registers::Info&
194 regInfo(Addr daddr)
195 {
196  static registers::Info invalid = { 0, false, false, "invalid" };
197  static registers::Info info [] = {
198  { 4, true, true, "Config" },
199  { 4, false, true, "Command" },
200  { 4, true, true, "IntrStatus" },
201  { 4, true, true, "IntrMask" },
202  { 4, true, false, "RxMaxCopy" },
203  { 4, true, false, "TxMaxCopy" },
204  { 4, true, false, "ZeroCopySize" },
205  { 4, true, false, "ZeroCopyMark" },
206  { 4, true, false, "VirtualCount" },
207  { 4, true, false, "RxMaxIntr" },
208  { 4, true, false, "RxFifoSize" },
209  { 4, true, false, "TxFifoSize" },
210  { 4, true, false, "RxFifoLow" },
211  { 4, true, false, "TxFifoLow" },
212  { 4, true, false, "RxFifoHigh" },
213  { 4, true, false, "TxFifoHigh" },
214  { 8, true, true, "RxData" },
215  invalid,
216  { 8, true, false, "RxDone" },
217  invalid,
218  { 8, true, false, "RxWait" },
219  invalid,
220  { 8, true, true, "TxData" },
221  invalid,
222  { 8, true, false, "TxDone" },
223  invalid,
224  { 8, true, false, "TxWait" },
225  invalid,
226  { 8, true, false, "HwAddr" },
227  invalid,
228  { 8, true, false, "RxStatus" },
229  invalid,
230  };
231 
232  return info[daddr / 4];
233 }
234 
235 inline bool
236 regValid(Addr daddr)
237 {
238  if (daddr > registers::Size)
239  return false;
240 
241  if (regInfo(daddr).size == 0)
242  return false;
243 
244  return true;
245 }
246 
247 } // namespace sinic
248 
249 } // namespace gem5
250 
251 #endif // __DEV_NET_SINICREG_HH__
gem5::sinic::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(Regs, registers)
gem5::sinic::registers::__SINIC_VAL64
__SINIC_VAL64(RxData_Vaddr, 60, 1) __SINIC_VAL64(RxData_Len
gem5::sinic::registers::Info::write
bool write
Definition: sinicreg.hh:187
gem5::sinic::regValid
bool regValid(Addr daddr)
Definition: sinicreg.hh:236
gem5::sinic::registers::__SINIC_REG32
__SINIC_REG32(Config, 0x00) __SINIC_REG32(Command
gem5::sinic::registers::Info
Definition: sinicreg.hh:183
gem5::sinic::registers::__SINIC_VAL32
__SINIC_VAL32(Config_ZeroCopy, 12, 1) __SINIC_VAL32(Config_DelayCopy
gem5::sinic::registers::Info::name
const char * name
Definition: sinicreg.hh:188
compiler.hh
gem5::sinic::registers::VirtualMask
static const int VirtualMask
Definition: sinicreg.hh:71
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::sinic::registers::VirtualShift
static const int VirtualShift
Definition: sinicreg.hh:70
gem5::sinic::registers::Info::read
bool read
Definition: sinicreg.hh:186
gem5::sinic::regInfo
const registers::Info & regInfo(Addr daddr)
Definition: sinicreg.hh:194
gem5::sinic::registers::Info::size
uint8_t size
Definition: sinicreg.hh:185
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
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