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tlbi_op.cc
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37 
38 #include "arch/arm/tlbi_op.hh"
39 
40 #include "arch/arm/mmu.hh"
41 #include "cpu/checker/cpu.hh"
42 
43 namespace gem5
44 {
45 
46 namespace ArmISA {
47 
48 void
49 TLBIALL::operator()(ThreadContext* tc)
50 {
51  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
52  inHost = (hcr.tge == 1 && hcr.e2h == 1);
53  el2Enabled = EL2Enabled(tc);
54  currentEL = currEL(tc);
55 
56  getMMUPtr(tc)->flush(*this);
57 
58  // If CheckerCPU is connected, need to notify it of a flush
59  CheckerCPU *checker = tc->getCheckerCpuPtr();
60  if (checker) {
61  getMMUPtr(checker)->flush(*this);
62  }
63 }
64 
65 void
66 ITLBIALL::operator()(ThreadContext* tc)
67 {
68  el2Enabled = EL2Enabled(tc);
69  getMMUPtr(tc)->iflush(*this);
70 }
71 
72 void
73 DTLBIALL::operator()(ThreadContext* tc)
74 {
75  el2Enabled = EL2Enabled(tc);
76  getMMUPtr(tc)->dflush(*this);
77 }
78 
79 void
80 TLBIALLEL::operator()(ThreadContext* tc)
81 {
82  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
83  inHost = (hcr.tge == 1 && hcr.e2h == 1);
84  getMMUPtr(tc)->flush(*this);
85 
86  // If CheckerCPU is connected, need to notify it of a flush
87  CheckerCPU *checker = tc->getCheckerCpuPtr();
88  if (checker) {
89  getMMUPtr(checker)->flush(*this);
90  }
91 }
92 
93 void
94 TLBIVMALL::operator()(ThreadContext* tc)
95 {
96  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
97  inHost = (hcr.tge == 1 && hcr.e2h == 1);
98 
99  getMMUPtr(tc)->flush(*this);
100 
101  // If CheckerCPU is connected, need to notify it of a flush
102  CheckerCPU *checker = tc->getCheckerCpuPtr();
103  if (checker) {
104  getMMUPtr(checker)->flush(*this);
105  }
106 }
107 
108 void
109 TLBIASID::operator()(ThreadContext* tc)
110 {
111  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
112  inHost = (hcr.tge == 1 && hcr.e2h == 1);
113  el2Enabled = EL2Enabled(tc);
114 
115  getMMUPtr(tc)->flushStage1(*this);
116  CheckerCPU *checker = tc->getCheckerCpuPtr();
117  if (checker) {
118  getMMUPtr(checker)->flushStage1(*this);
119  }
120 }
121 
122 void
123 ITLBIASID::operator()(ThreadContext* tc)
124 {
125  el2Enabled = EL2Enabled(tc);
126  getMMUPtr(tc)->iflush(*this);
127 }
128 
129 void
130 DTLBIASID::operator()(ThreadContext* tc)
131 {
132  el2Enabled = EL2Enabled(tc);
133  getMMUPtr(tc)->dflush(*this);
134 }
135 
136 void
137 TLBIALLN::operator()(ThreadContext* tc)
138 {
139  getMMUPtr(tc)->flush(*this);
140 
141  CheckerCPU *checker = tc->getCheckerCpuPtr();
142  if (checker) {
143  getMMUPtr(checker)->flush(*this);
144  }
145 }
146 
147 void
148 TLBIMVAA::operator()(ThreadContext* tc)
149 {
150  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
151  inHost = (hcr.tge == 1 && hcr.e2h == 1);
152  getMMUPtr(tc)->flushStage1(*this);
153 
154  CheckerCPU *checker = tc->getCheckerCpuPtr();
155  if (checker) {
156  getMMUPtr(checker)->flushStage1(*this);
157  }
158 }
159 
160 void
161 TLBIMVA::operator()(ThreadContext* tc)
162 {
163  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
164  inHost = (hcr.tge == 1 && hcr.e2h == 1);
165  getMMUPtr(tc)->flushStage1(*this);
166 
167  CheckerCPU *checker = tc->getCheckerCpuPtr();
168  if (checker) {
169  getMMUPtr(checker)->flushStage1(*this);
170  }
171 }
172 
173 void
174 ITLBIMVA::operator()(ThreadContext* tc)
175 {
176  getMMUPtr(tc)->iflush(*this);
177 }
178 
179 void
180 DTLBIMVA::operator()(ThreadContext* tc)
181 {
182  getMMUPtr(tc)->dflush(*this);
183 }
184 
185 void
186 TLBIIPA::operator()(ThreadContext* tc)
187 {
188  getMMUPtr(tc)->flushStage2(makeStage2());
189 
190  CheckerCPU *checker = tc->getCheckerCpuPtr();
191  if (checker) {
192  getMMUPtr(checker)->flushStage2(makeStage2());
193  }
194 }
195 
196 } // namespace ArmISA
197 } // namespace gem5
gem5::ArmISA::TLBIIPA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:186
gem5::ArmISA::MMU::flush
void flush(const OP &tlbi_op)
Definition: mmu.hh:113
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmISA::DTLBIALL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:73
gem5::ArmISA::currEL
static ExceptionLevel currEL(const ThreadContext *tc)
Definition: utility.hh:119
gem5::ArmISA::DTLBIASID::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:130
gem5::ArmISA::ITLBIASID::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:123
gem5::ArmISA::TLBIALL::inHost
bool inHost
Definition: tlbi_op.hh:130
gem5::ArmISA::TLBIIPA::makeStage2
TLBIMVAA makeStage2() const
TLBIIPA is basically a TLBIMVAA for stage2 TLBs.
Definition: tlbi_op.hh:358
gem5::ArmISA::getMMUPtr
MMU * getMMUPtr(T *tc)
Definition: mmu.hh:171
gem5::ArmISA::ITLBIALL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:66
gem5::ArmISA::TLBIALLN::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:137
gem5::ArmISA::TLBIASID::el2Enabled
bool el2Enabled
Definition: tlbi_op.hh:228
mmu.hh
gem5::ArmISA::TLBIMVA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:161
gem5::ArmISA::TLBIALL::currentEL
ExceptionLevel currentEL
Definition: tlbi_op.hh:132
gem5::ArmISA::MMU::iflush
void iflush(const OP &tlbi_op)
Definition: mmu.hh:142
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::TLBIALLEL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:80
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
cpu.hh
gem5::ArmISA::MMU::flushStage2
void flushStage2(const OP &tlbi_op)
Definition: mmu.hh:134
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:274
tlbi_op.hh
gem5::ArmISA::MMU::dflush
void dflush(const OP &tlbi_op)
Definition: mmu.hh:149
gem5::ArmISA::TLBIASID::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:109
gem5::ArmISA::TLBIALL::el2Enabled
bool el2Enabled
Definition: tlbi_op.hh:131
gem5::ArmISA::TLBIASID::inHost
bool inHost
Definition: tlbi_op.hh:227
gem5::ArmISA::TLBIVMALL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:94
gem5::ArmISA::TLBIMVAA::inHost
bool inHost
Definition: tlbi_op.hh:292
gem5::ArmISA::TLBIMVA::inHost
bool inHost
Definition: tlbi_op.hh:309
gem5::ArmISA::TLBIALLEL::inHost
bool inHost
Definition: tlbi_op.hh:184
gem5::ArmISA::DTLBIMVA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:180
gem5::ArmISA::ITLBIMVA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:174
gem5::ArmISA::TLBIVMALL::inHost
bool inHost
Definition: tlbi_op.hh:210
gem5::ArmISA::MMU::flushStage1
void flushStage1(const OP &tlbi_op)
Definition: mmu.hh:126
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:586
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ThreadContext::getCheckerCpuPtr
virtual CheckerCPU * getCheckerCpuPtr()=0
gem5::ArmISA::TLBIMVAA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:148
gem5::ArmISA::TLBIALL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:49
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