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decoder.cc
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1 /*
2  * Copyright (c) 2015-2021 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * For use for simulation and test purposes only
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright notice,
11  * this list of conditions and the following disclaimer.
12  *
13  * 2. Redistributions in binary form must reproduce the above copyright notice,
14  * this list of conditions and the following disclaimer in the documentation
15  * and/or other materials provided with the distribution.
16  *
17  * 3. Neither the name of the copyright holder nor the names of its
18  * contributors may be used to endorse or promote products derived from this
19  * software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 #include <vector>
35 
39 
40 namespace gem5
41 {
42 
43 namespace Gcn3ISA
44 {
46  {
47  } // Decoder
48 
50  {
51  } // ~Decoder
52 
566  };
567 
1337  };
1338 
1596  };
1597 
1727  };
1728 
1858  };
1859 
1877  };
1878 
2008  };
2009 
2075  };
2076 
2334  };
2335 
2465  };
2466 
2596  };
2597 
2603  };
2604 
2862  };
2863 
3121  };
3122 
3123  GPUStaticInst*
3125  {
3126  InFmt_SOP1 *enc = &mach_inst->iFmt_SOP1;
3128  return (this->*method)(mach_inst);
3129  } // decode
3130 
3131  GPUStaticInst*
3133  {
3134  InFmt_VOPC *enc = &iFmt->iFmt_VOPC;
3135  IsaDecodeMethod method = tableSubDecode_OP_VOPC[enc->OP];
3136  return (this->*method)(iFmt);
3137  } // subDecode_OP_VOPC
3138 
3139  GPUStaticInst*
3141  {
3142  InFmt_VOP1 *enc = &iFmt->iFmt_VOP1;
3143  IsaDecodeMethod method = tableSubDecode_OP_VOP1[enc->OP];
3144  return (this->*method)(iFmt);
3145  } // subDecode_OP_VOP1
3146 
3147  GPUStaticInst*
3149  {
3150  InFmt_SOP1 *enc = &iFmt->iFmt_SOP1;
3151  IsaDecodeMethod method = tableSubDecode_OP_SOP1[enc->OP];
3152  return (this->*method)(iFmt);
3153  } // subDecode_OP_SOP1
3154 
3155  GPUStaticInst*
3157  {
3158  InFmt_SOPC *enc = &iFmt->iFmt_SOPC;
3159  IsaDecodeMethod method = tableSubDecode_OP_SOPC[enc->OP];
3160  return (this->*method)(iFmt);
3161  } // subDecode_OP_SOPC
3162 
3163  GPUStaticInst*
3165  {
3166  InFmt_SOPP *enc = &iFmt->iFmt_SOPP;
3167  IsaDecodeMethod method = tableSubDecode_OP_SOPP[enc->OP];
3168  return (this->*method)(iFmt);
3169  } // subDecode_OP_SOPP
3170 
3171  GPUStaticInst*
3173  {
3174  InFmt_SMEM *enc = &iFmt->iFmt_SMEM;
3175  IsaDecodeMethod method = tableSubDecode_OP_SMEM[enc->OP];
3176  return (this->*method)(iFmt);
3177  } // subDecode_OP_SMEM
3178 
3179  GPUStaticInst*
3181  {
3182  InFmt_VOP3 *enc = &iFmt->iFmt_VOP3;
3184  return (this->*method)(iFmt);
3185  } // subDecode_OPU_VOP3
3186 
3187  GPUStaticInst*
3189  {
3190  InFmt_VINTRP *enc = &iFmt->iFmt_VINTRP;
3192  return (this->*method)(iFmt);
3193  } // subDecode_OP_VINTRP
3194 
3195  GPUStaticInst*
3197  {
3198  InFmt_DS *enc = &iFmt->iFmt_DS;
3199  IsaDecodeMethod method = tableSubDecode_OP_DS[enc->OP];
3200  return (this->*method)(iFmt);
3201  } // subDecode_OP_DS
3202 
3203  GPUStaticInst*
3205  {
3206  InFmt_FLAT *enc = &iFmt->iFmt_FLAT;
3207  IsaDecodeMethod method = tableSubDecode_OP_FLAT[enc->OP];
3208  return (this->*method)(iFmt);
3209  } // subDecode_OP_FLAT
3210 
3211  GPUStaticInst*
3213  {
3214  InFmt_MUBUF *enc = &iFmt->iFmt_MUBUF;
3216  return (this->*method)(iFmt);
3217  } // subDecode_OP_MUBUF
3218 
3219  GPUStaticInst*
3221  {
3222  InFmt_MTBUF *enc = &iFmt->iFmt_MTBUF;
3224  return (this->*method)(iFmt);
3225  } // subDecode_OP_MTBUF
3226 
3227  GPUStaticInst*
3229  {
3230  InFmt_MIMG *enc = &iFmt->iFmt_MIMG;
3231  IsaDecodeMethod method = tableSubDecode_OP_MIMG[enc->OP];
3232  return (this->*method)(iFmt);
3233  } // subDecode_OP_MIMG
3234 
3235  GPUStaticInst*
3237  {
3238  return new Inst_VOP2__V_CNDMASK_B32(&iFmt->iFmt_VOP2);
3239  } // decode_OP_VOP2__V_CNDMASK_B32
3240 
3241  GPUStaticInst*
3243  {
3244  return new Inst_VOP2__V_ADD_F32(&iFmt->iFmt_VOP2);
3245  } // decode_OP_VOP2__V_ADD_F32
3246 
3247  GPUStaticInst*
3249  {
3250  return new Inst_VOP2__V_SUB_F32(&iFmt->iFmt_VOP2);
3251  } // decode_OP_VOP2__V_SUB_F32
3252 
3253  GPUStaticInst*
3255  {
3256  return new Inst_VOP2__V_SUBREV_F32(&iFmt->iFmt_VOP2);
3257  } // decode_OP_VOP2__V_SUBREV_F32
3258 
3259  GPUStaticInst*
3261  {
3262  return new Inst_VOP2__V_MUL_LEGACY_F32(&iFmt->iFmt_VOP2);
3263  } // decode_OP_VOP2__V_MUL_LEGACY_F32
3264 
3265  GPUStaticInst*
3267  {
3268  return new Inst_VOP2__V_MUL_F32(&iFmt->iFmt_VOP2);
3269  } // decode_OP_VOP2__V_MUL_F32
3270 
3271  GPUStaticInst*
3273  {
3274  return new Inst_VOP2__V_MUL_I32_I24(&iFmt->iFmt_VOP2);
3275  } // decode_OP_VOP2__V_MUL_I32_I24
3276 
3277  GPUStaticInst*
3279  {
3280  return new Inst_VOP2__V_MUL_HI_I32_I24(&iFmt->iFmt_VOP2);
3281  } // decode_OP_VOP2__V_MUL_HI_I32_I24
3282 
3283  GPUStaticInst*
3285  {
3286  return new Inst_VOP2__V_MUL_U32_U24(&iFmt->iFmt_VOP2);
3287  } // decode_OP_VOP2__V_MUL_U32_U24
3288 
3289  GPUStaticInst*
3291  {
3292  return new Inst_VOP2__V_MUL_HI_U32_U24(&iFmt->iFmt_VOP2);
3293  } // decode_OP_VOP2__V_MUL_HI_U32_U24
3294 
3295  GPUStaticInst*
3297  {
3298  return new Inst_VOP2__V_MIN_F32(&iFmt->iFmt_VOP2);
3299  } // decode_OP_VOP2__V_MIN_F32
3300 
3301  GPUStaticInst*
3303  {
3304  return new Inst_VOP2__V_MAX_F32(&iFmt->iFmt_VOP2);
3305  } // decode_OP_VOP2__V_MAX_F32
3306 
3307  GPUStaticInst*
3309  {
3310  return new Inst_VOP2__V_MIN_I32(&iFmt->iFmt_VOP2);
3311  } // decode_OP_VOP2__V_MIN_I32
3312 
3313  GPUStaticInst*
3315  {
3316  return new Inst_VOP2__V_MAX_I32(&iFmt->iFmt_VOP2);
3317  } // decode_OP_VOP2__V_MAX_I32
3318 
3319  GPUStaticInst*
3321  {
3322  return new Inst_VOP2__V_MIN_U32(&iFmt->iFmt_VOP2);
3323  } // decode_OP_VOP2__V_MIN_U32
3324 
3325  GPUStaticInst*
3327  {
3328  return new Inst_VOP2__V_MAX_U32(&iFmt->iFmt_VOP2);
3329  } // decode_OP_VOP2__V_MAX_U32
3330 
3331  GPUStaticInst*
3333  {
3334  return new Inst_VOP2__V_LSHRREV_B32(&iFmt->iFmt_VOP2);
3335  } // decode_OP_VOP2__V_LSHRREV_B32
3336 
3337  GPUStaticInst*
3339  {
3340  return new Inst_VOP2__V_ASHRREV_I32(&iFmt->iFmt_VOP2);
3341  } // decode_OP_VOP2__V_ASHRREV_I32
3342 
3343  GPUStaticInst*
3345  {
3346  return new Inst_VOP2__V_LSHLREV_B32(&iFmt->iFmt_VOP2);
3347  } // decode_OP_VOP2__V_LSHLREV_B32
3348 
3349  GPUStaticInst*
3351  {
3352  return new Inst_VOP2__V_AND_B32(&iFmt->iFmt_VOP2);
3353  } // decode_OP_VOP2__V_AND_B32
3354 
3355  GPUStaticInst*
3357  {
3358  return new Inst_VOP2__V_OR_B32(&iFmt->iFmt_VOP2);
3359  } // decode_OP_VOP2__V_OR_B32
3360 
3361  GPUStaticInst*
3363  {
3364  return new Inst_VOP2__V_XOR_B32(&iFmt->iFmt_VOP2);
3365  } // decode_OP_VOP2__V_XOR_B32
3366 
3367  GPUStaticInst*
3369  {
3370  return new Inst_VOP2__V_MAC_F32(&iFmt->iFmt_VOP2);
3371  } // decode_OP_VOP2__V_MAC_F32
3372 
3373  GPUStaticInst*
3375  {
3376  return new Inst_VOP2__V_MADMK_F32(&iFmt->iFmt_VOP2);
3377  } // decode_OP_VOP2__V_MADMK_F32
3378 
3379  GPUStaticInst*
3381  {
3382  return new Inst_VOP2__V_MADAK_F32(&iFmt->iFmt_VOP2);
3383  } // decode_OP_VOP2__V_MADAK_F32
3384 
3385  GPUStaticInst*
3387  {
3388  return new Inst_VOP2__V_ADD_U32(&iFmt->iFmt_VOP2);
3389  } // decode_OP_VOP2__V_ADD_U32
3390 
3391  GPUStaticInst*
3393  {
3394  return new Inst_VOP2__V_SUB_U32(&iFmt->iFmt_VOP2);
3395  } // decode_OP_VOP2__V_SUB_U32
3396 
3397  GPUStaticInst*
3399  {
3400  return new Inst_VOP2__V_SUBREV_U32(&iFmt->iFmt_VOP2);
3401  } // decode_OP_VOP2__V_SUBREV_U32
3402 
3403  GPUStaticInst*
3405  {
3406  return new Inst_VOP2__V_ADDC_U32(&iFmt->iFmt_VOP2);
3407  } // decode_OP_VOP2__V_ADDC_U32
3408 
3409  GPUStaticInst*
3411  {
3412  return new Inst_VOP2__V_SUBB_U32(&iFmt->iFmt_VOP2);
3413  } // decode_OP_VOP2__V_SUBB_U32
3414 
3415  GPUStaticInst*
3417  {
3418  return new Inst_VOP2__V_SUBBREV_U32(&iFmt->iFmt_VOP2);
3419  } // decode_OP_VOP2__V_SUBBREV_U32
3420 
3421  GPUStaticInst*
3423  {
3424  return new Inst_VOP2__V_ADD_F16(&iFmt->iFmt_VOP2);
3425  } // decode_OP_VOP2__V_ADD_F16
3426 
3427  GPUStaticInst*
3429  {
3430  return new Inst_VOP2__V_SUB_F16(&iFmt->iFmt_VOP2);
3431  } // decode_OP_VOP2__V_SUB_F16
3432 
3433  GPUStaticInst*
3435  {
3436  return new Inst_VOP2__V_SUBREV_F16(&iFmt->iFmt_VOP2);
3437  } // decode_OP_VOP2__V_SUBREV_F16
3438 
3439  GPUStaticInst*
3441  {
3442  return new Inst_VOP2__V_MUL_F16(&iFmt->iFmt_VOP2);
3443  } // decode_OP_VOP2__V_MUL_F16
3444 
3445  GPUStaticInst*
3447  {
3448  return new Inst_VOP2__V_MAC_F16(&iFmt->iFmt_VOP2);
3449  } // decode_OP_VOP2__V_MAC_F16
3450 
3451  GPUStaticInst*
3453  {
3454  return new Inst_VOP2__V_MADMK_F16(&iFmt->iFmt_VOP2);
3455  } // decode_OP_VOP2__V_MADMK_F16
3456 
3457  GPUStaticInst*
3459  {
3460  return new Inst_VOP2__V_MADAK_F16(&iFmt->iFmt_VOP2);
3461  } // decode_OP_VOP2__V_MADAK_F16
3462 
3463  GPUStaticInst*
3465  {
3466  return new Inst_VOP2__V_ADD_U16(&iFmt->iFmt_VOP2);
3467  } // decode_OP_VOP2__V_ADD_U16
3468 
3469  GPUStaticInst*
3471  {
3472  return new Inst_VOP2__V_SUB_U16(&iFmt->iFmt_VOP2);
3473  } // decode_OP_VOP2__V_SUB_U16
3474 
3475  GPUStaticInst*
3477  {
3478  return new Inst_VOP2__V_SUBREV_U16(&iFmt->iFmt_VOP2);
3479  } // decode_OP_VOP2__V_SUBREV_U16
3480 
3481  GPUStaticInst*
3483  {
3484  return new Inst_VOP2__V_MUL_LO_U16(&iFmt->iFmt_VOP2);
3485  } // decode_OP_VOP2__V_MUL_LO_U16
3486 
3487  GPUStaticInst*
3489  {
3490  return new Inst_VOP2__V_LSHLREV_B16(&iFmt->iFmt_VOP2);
3491  } // decode_OP_VOP2__V_LSHLREV_B16
3492 
3493  GPUStaticInst*
3495  {
3496  return new Inst_VOP2__V_LSHRREV_B16(&iFmt->iFmt_VOP2);
3497  } // decode_OP_VOP2__V_LSHRREV_B16
3498 
3499  GPUStaticInst*
3501  {
3502  return new Inst_VOP2__V_ASHRREV_I16(&iFmt->iFmt_VOP2);
3503  } // decode_OP_VOP2__V_ASHRREV_I16
3504 
3505  GPUStaticInst*
3507  {
3508  return new Inst_VOP2__V_MAX_F16(&iFmt->iFmt_VOP2);
3509  } // decode_OP_VOP2__V_MAX_F16
3510 
3511  GPUStaticInst*
3513  {
3514  return new Inst_VOP2__V_MIN_F16(&iFmt->iFmt_VOP2);
3515  } // decode_OP_VOP2__V_MIN_F16
3516 
3517  GPUStaticInst*
3519  {
3520  return new Inst_VOP2__V_MAX_U16(&iFmt->iFmt_VOP2);
3521  } // decode_OP_VOP2__V_MAX_U16
3522 
3523  GPUStaticInst*
3525  {
3526  return new Inst_VOP2__V_MAX_I16(&iFmt->iFmt_VOP2);
3527  } // decode_OP_VOP2__V_MAX_I16
3528 
3529  GPUStaticInst*
3531  {
3532  return new Inst_VOP2__V_MIN_U16(&iFmt->iFmt_VOP2);
3533  } // decode_OP_VOP2__V_MIN_U16
3534 
3535  GPUStaticInst*
3537  {
3538  return new Inst_VOP2__V_MIN_I16(&iFmt->iFmt_VOP2);
3539  } // decode_OP_VOP2__V_MIN_I16
3540 
3541  GPUStaticInst*
3543  {
3544  return new Inst_VOP2__V_LDEXP_F16(&iFmt->iFmt_VOP2);
3545  } // decode_OP_VOP2__V_LDEXP_F16
3546 
3547  GPUStaticInst*
3549  {
3550  return new Inst_SOP2__S_ADD_U32(&iFmt->iFmt_SOP2);
3551  } // decode_OP_SOP2__S_ADD_U32
3552 
3553  GPUStaticInst*
3555  {
3556  return new Inst_SOP2__S_SUB_U32(&iFmt->iFmt_SOP2);
3557  } // decode_OP_SOP2__S_SUB_U32
3558 
3559  GPUStaticInst*
3561  {
3562  return new Inst_SOP2__S_ADD_I32(&iFmt->iFmt_SOP2);
3563  } // decode_OP_SOP2__S_ADD_I32
3564 
3565  GPUStaticInst*
3567  {
3568  return new Inst_SOP2__S_SUB_I32(&iFmt->iFmt_SOP2);
3569  } // decode_OP_SOP2__S_SUB_I32
3570 
3571  GPUStaticInst*
3573  {
3574  return new Inst_SOP2__S_ADDC_U32(&iFmt->iFmt_SOP2);
3575  } // decode_OP_SOP2__S_ADDC_U32
3576 
3577  GPUStaticInst*
3579  {
3580  return new Inst_SOP2__S_SUBB_U32(&iFmt->iFmt_SOP2);
3581  } // decode_OP_SOP2__S_SUBB_U32
3582 
3583  GPUStaticInst*
3585  {
3586  return new Inst_SOP2__S_MIN_I32(&iFmt->iFmt_SOP2);
3587  } // decode_OP_SOP2__S_MIN_I32
3588 
3589  GPUStaticInst*
3591  {
3592  return new Inst_SOP2__S_MIN_U32(&iFmt->iFmt_SOP2);
3593  } // decode_OP_SOP2__S_MIN_U32
3594 
3595  GPUStaticInst*
3597  {
3598  return new Inst_SOP2__S_MAX_I32(&iFmt->iFmt_SOP2);
3599  } // decode_OP_SOP2__S_MAX_I32
3600 
3601  GPUStaticInst*
3603  {
3604  return new Inst_SOP2__S_MAX_U32(&iFmt->iFmt_SOP2);
3605  } // decode_OP_SOP2__S_MAX_U32
3606 
3607  GPUStaticInst*
3609  {
3610  return new Inst_SOP2__S_CSELECT_B32(&iFmt->iFmt_SOP2);
3611  } // decode_OP_SOP2__S_CSELECT_B32
3612 
3613  GPUStaticInst*
3615  {
3616  return new Inst_SOP2__S_CSELECT_B64(&iFmt->iFmt_SOP2);
3617  } // decode_OP_SOP2__S_CSELECT_B64
3618 
3619  GPUStaticInst*
3621  {
3622  return new Inst_SOP2__S_AND_B32(&iFmt->iFmt_SOP2);
3623  } // decode_OP_SOP2__S_AND_B32
3624 
3625  GPUStaticInst*
3627  {
3628  return new Inst_SOP2__S_AND_B64(&iFmt->iFmt_SOP2);
3629  } // decode_OP_SOP2__S_AND_B64
3630 
3631  GPUStaticInst*
3633  {
3634  return new Inst_SOP2__S_OR_B32(&iFmt->iFmt_SOP2);
3635  } // decode_OP_SOP2__S_OR_B32
3636 
3637  GPUStaticInst*
3639  {
3640  return new Inst_SOP2__S_OR_B64(&iFmt->iFmt_SOP2);
3641  } // decode_OP_SOP2__S_OR_B64
3642 
3643  GPUStaticInst*
3645  {
3646  return new Inst_SOP2__S_XOR_B32(&iFmt->iFmt_SOP2);
3647  } // decode_OP_SOP2__S_XOR_B32
3648 
3649  GPUStaticInst*
3651  {
3652  return new Inst_SOP2__S_XOR_B64(&iFmt->iFmt_SOP2);
3653  } // decode_OP_SOP2__S_XOR_B64
3654 
3655  GPUStaticInst*
3657  {
3658  return new Inst_SOP2__S_ANDN2_B32(&iFmt->iFmt_SOP2);
3659  } // decode_OP_SOP2__S_ANDN2_B32
3660 
3661  GPUStaticInst*
3663  {
3664  return new Inst_SOP2__S_ANDN2_B64(&iFmt->iFmt_SOP2);
3665  } // decode_OP_SOP2__S_ANDN2_B64
3666 
3667  GPUStaticInst*
3669  {
3670  return new Inst_SOP2__S_ORN2_B32(&iFmt->iFmt_SOP2);
3671  } // decode_OP_SOP2__S_ORN2_B32
3672 
3673  GPUStaticInst*
3675  {
3676  return new Inst_SOP2__S_ORN2_B64(&iFmt->iFmt_SOP2);
3677  } // decode_OP_SOP2__S_ORN2_B64
3678 
3679  GPUStaticInst*
3681  {
3682  return new Inst_SOP2__S_NAND_B32(&iFmt->iFmt_SOP2);
3683  } // decode_OP_SOP2__S_NAND_B32
3684 
3685  GPUStaticInst*
3687  {
3688  return new Inst_SOP2__S_NAND_B64(&iFmt->iFmt_SOP2);
3689  } // decode_OP_SOP2__S_NAND_B64
3690 
3691  GPUStaticInst*
3693  {
3694  return new Inst_SOP2__S_NOR_B32(&iFmt->iFmt_SOP2);
3695  } // decode_OP_SOP2__S_NOR_B32
3696 
3697  GPUStaticInst*
3699  {
3700  return new Inst_SOP2__S_NOR_B64(&iFmt->iFmt_SOP2);
3701  } // decode_OP_SOP2__S_NOR_B64
3702 
3703  GPUStaticInst*
3705  {
3706  return new Inst_SOP2__S_XNOR_B32(&iFmt->iFmt_SOP2);
3707  } // decode_OP_SOP2__S_XNOR_B32
3708 
3709  GPUStaticInst*
3711  {
3712  return new Inst_SOP2__S_XNOR_B64(&iFmt->iFmt_SOP2);
3713  } // decode_OP_SOP2__S_XNOR_B64
3714 
3715  GPUStaticInst*
3717  {
3718  return new Inst_SOP2__S_LSHL_B32(&iFmt->iFmt_SOP2);
3719  } // decode_OP_SOP2__S_LSHL_B32
3720 
3721  GPUStaticInst*
3723  {
3724  return new Inst_SOP2__S_LSHL_B64(&iFmt->iFmt_SOP2);
3725  } // decode_OP_SOP2__S_LSHL_B64
3726 
3727  GPUStaticInst*
3729  {
3730  return new Inst_SOP2__S_LSHR_B32(&iFmt->iFmt_SOP2);
3731  } // decode_OP_SOP2__S_LSHR_B32
3732 
3733  GPUStaticInst*
3735  {
3736  return new Inst_SOP2__S_LSHR_B64(&iFmt->iFmt_SOP2);
3737  } // decode_OP_SOP2__S_LSHR_B64
3738 
3739  GPUStaticInst*
3741  {
3742  return new Inst_SOP2__S_ASHR_I32(&iFmt->iFmt_SOP2);
3743  } // decode_OP_SOP2__S_ASHR_I32
3744 
3745  GPUStaticInst*
3747  {
3748  return new Inst_SOP2__S_ASHR_I64(&iFmt->iFmt_SOP2);
3749  } // decode_OP_SOP2__S_ASHR_I64
3750 
3751  GPUStaticInst*
3753  {
3754  return new Inst_SOP2__S_BFM_B32(&iFmt->iFmt_SOP2);
3755  } // decode_OP_SOP2__S_BFM_B32
3756 
3757  GPUStaticInst*
3759  {
3760  return new Inst_SOP2__S_BFM_B64(&iFmt->iFmt_SOP2);
3761  } // decode_OP_SOP2__S_BFM_B64
3762 
3763  GPUStaticInst*
3765  {
3766  return new Inst_SOP2__S_MUL_I32(&iFmt->iFmt_SOP2);
3767  } // decode_OP_SOP2__S_MUL_I32
3768 
3769  GPUStaticInst*
3771  {
3772  return new Inst_SOP2__S_BFE_U32(&iFmt->iFmt_SOP2);
3773  } // decode_OP_SOP2__S_BFE_U32
3774 
3775  GPUStaticInst*
3777  {
3778  return new Inst_SOP2__S_BFE_I32(&iFmt->iFmt_SOP2);
3779  } // decode_OP_SOP2__S_BFE_I32
3780 
3781  GPUStaticInst*
3783  {
3784  return new Inst_SOP2__S_BFE_U64(&iFmt->iFmt_SOP2);
3785  } // decode_OP_SOP2__S_BFE_U64
3786 
3787  GPUStaticInst*
3789  {
3790  return new Inst_SOP2__S_BFE_I64(&iFmt->iFmt_SOP2);
3791  } // decode_OP_SOP2__S_BFE_I64
3792 
3793  GPUStaticInst*
3795  {
3796  return new Inst_SOP2__S_CBRANCH_G_FORK(&iFmt->iFmt_SOP2);
3797  } // decode_OP_SOP2__S_CBRANCH_G_FORK
3798 
3799  GPUStaticInst*
3801  {
3802  return new Inst_SOP2__S_ABSDIFF_I32(&iFmt->iFmt_SOP2);
3803  } // decode_OP_SOP2__S_ABSDIFF_I32
3804 
3805  GPUStaticInst*
3807  {
3808  return new Inst_SOP2__S_RFE_RESTORE_B64(&iFmt->iFmt_SOP2);
3809  } // decode_OP_SOP2__S_RFE_RESTORE_B64
3810 
3811  GPUStaticInst*
3813  {
3814  return new Inst_SOPK__S_MOVK_I32(&iFmt->iFmt_SOPK);
3815  } // decode_OP_SOPK__S_MOVK_I32
3816 
3817  GPUStaticInst*
3819  {
3820  return new Inst_SOPK__S_CMOVK_I32(&iFmt->iFmt_SOPK);
3821  } // decode_OP_SOPK__S_CMOVK_I32
3822 
3823  GPUStaticInst*
3825  {
3826  return new Inst_SOPK__S_CMPK_EQ_I32(&iFmt->iFmt_SOPK);
3827  } // decode_OP_SOPK__S_CMPK_EQ_I32
3828 
3829  GPUStaticInst*
3831  {
3832  return new Inst_SOPK__S_CMPK_LG_I32(&iFmt->iFmt_SOPK);
3833  } // decode_OP_SOPK__S_CMPK_LG_I32
3834 
3835  GPUStaticInst*
3837  {
3838  return new Inst_SOPK__S_CMPK_GT_I32(&iFmt->iFmt_SOPK);
3839  } // decode_OP_SOPK__S_CMPK_GT_I32
3840 
3841  GPUStaticInst*
3843  {
3844  return new Inst_SOPK__S_CMPK_GE_I32(&iFmt->iFmt_SOPK);
3845  } // decode_OP_SOPK__S_CMPK_GE_I32
3846 
3847  GPUStaticInst*
3849  {
3850  return new Inst_SOPK__S_CMPK_LT_I32(&iFmt->iFmt_SOPK);
3851  } // decode_OP_SOPK__S_CMPK_LT_I32
3852 
3853  GPUStaticInst*
3855  {
3856  return new Inst_SOPK__S_CMPK_LE_I32(&iFmt->iFmt_SOPK);
3857  } // decode_OP_SOPK__S_CMPK_LE_I32
3858 
3859  GPUStaticInst*
3861  {
3862  return new Inst_SOPK__S_CMPK_EQ_U32(&iFmt->iFmt_SOPK);
3863  } // decode_OP_SOPK__S_CMPK_EQ_U32
3864 
3865  GPUStaticInst*
3867  {
3868  return new Inst_SOPK__S_CMPK_LG_U32(&iFmt->iFmt_SOPK);
3869  } // decode_OP_SOPK__S_CMPK_LG_U32
3870 
3871  GPUStaticInst*
3873  {
3874  return new Inst_SOPK__S_CMPK_GT_U32(&iFmt->iFmt_SOPK);
3875  } // decode_OP_SOPK__S_CMPK_GT_U32
3876 
3877  GPUStaticInst*
3879  {
3880  return new Inst_SOPK__S_CMPK_GE_U32(&iFmt->iFmt_SOPK);
3881  } // decode_OP_SOPK__S_CMPK_GE_U32
3882 
3883  GPUStaticInst*
3885  {
3886  return new Inst_SOPK__S_CMPK_LT_U32(&iFmt->iFmt_SOPK);
3887  } // decode_OP_SOPK__S_CMPK_LT_U32
3888 
3889  GPUStaticInst*
3891  {
3892  return new Inst_SOPK__S_CMPK_LE_U32(&iFmt->iFmt_SOPK);
3893  } // decode_OP_SOPK__S_CMPK_LE_U32
3894 
3895  GPUStaticInst*
3897  {
3898  return new Inst_SOPK__S_ADDK_I32(&iFmt->iFmt_SOPK);
3899  } // decode_OP_SOPK__S_ADDK_I32
3900 
3901  GPUStaticInst*
3903  {
3904  return new Inst_SOPK__S_MULK_I32(&iFmt->iFmt_SOPK);
3905  } // decode_OP_SOPK__S_MULK_I32
3906 
3907  GPUStaticInst*
3909  {
3910  return new Inst_SOPK__S_CBRANCH_I_FORK(&iFmt->iFmt_SOPK);
3911  } // decode_OP_SOPK__S_CBRANCH_I_FORK
3912 
3913  GPUStaticInst*
3915  {
3916  return new Inst_SOPK__S_GETREG_B32(&iFmt->iFmt_SOPK);
3917  } // decode_OP_SOPK__S_GETREG_B32
3918 
3919  GPUStaticInst*
3921  {
3922  return new Inst_SOPK__S_SETREG_B32(&iFmt->iFmt_SOPK);
3923  } // decode_OP_SOPK__S_SETREG_B32
3924 
3925  GPUStaticInst*
3927  {
3928  return new Inst_SOPK__S_SETREG_IMM32_B32(&iFmt->iFmt_SOPK);
3929  } // decode_OP_SOPK__S_SETREG_IMM32_B32
3930 
3931  GPUStaticInst*
3933  {
3934  return new Inst_EXP__EXP(&iFmt->iFmt_EXP);
3935  } // decode_OP_EXP
3936 
3937  GPUStaticInst*
3939  {
3940  return new Inst_VOP3__V_CMP_CLASS_F32(&iFmt->iFmt_VOP3);
3941  } // decode_OPU_VOP3__V_CMP_CLASS_F32
3942 
3943  GPUStaticInst*
3945  {
3946  return new Inst_VOP3__V_CMPX_CLASS_F32(&iFmt->iFmt_VOP3);
3947  } // decode_OPU_VOP3__V_CMPX_CLASS_F32
3948 
3949  GPUStaticInst*
3951  {
3952  return new Inst_VOP3__V_CMP_CLASS_F64(&iFmt->iFmt_VOP3);
3953  } // decode_OPU_VOP3__V_CMP_CLASS_F64
3954 
3955  GPUStaticInst*
3957  {
3958  return new Inst_VOP3__V_CMPX_CLASS_F64(&iFmt->iFmt_VOP3);
3959  } // decode_OPU_VOP3__V_CMPX_CLASS_F64
3960 
3961  GPUStaticInst*
3963  {
3964  return new Inst_VOP3__V_CMP_CLASS_F16(&iFmt->iFmt_VOP3);
3965  } // decode_OPU_VOP3__V_CMP_CLASS_F16
3966 
3967  GPUStaticInst*
3969  {
3970  return new Inst_VOP3__V_CMPX_CLASS_F16(&iFmt->iFmt_VOP3);
3971  } // decode_OPU_VOP3__V_CMPX_CLASS_F16
3972 
3973  GPUStaticInst*
3975  {
3976  return new Inst_VOP3__V_CMP_F_F16(&iFmt->iFmt_VOP3);
3977  } // decode_OPU_VOP3__V_CMP_F_F16
3978 
3979  GPUStaticInst*
3981  {
3982  return new Inst_VOP3__V_CMP_LT_F16(&iFmt->iFmt_VOP3);
3983  } // decode_OPU_VOP3__V_CMP_LT_F16
3984 
3985  GPUStaticInst*
3987  {
3988  return new Inst_VOP3__V_CMP_EQ_F16(&iFmt->iFmt_VOP3);
3989  } // decode_OPU_VOP3__V_CMP_EQ_F16
3990 
3991  GPUStaticInst*
3993  {
3994  return new Inst_VOP3__V_CMP_LE_F16(&iFmt->iFmt_VOP3);
3995  } // decode_OPU_VOP3__V_CMP_LE_F16
3996 
3997  GPUStaticInst*
3999  {
4000  return new Inst_VOP3__V_CMP_GT_F16(&iFmt->iFmt_VOP3);
4001  } // decode_OPU_VOP3__V_CMP_GT_F16
4002 
4003  GPUStaticInst*
4005  {
4006  return new Inst_VOP3__V_CMP_LG_F16(&iFmt->iFmt_VOP3);
4007  } // decode_OPU_VOP3__V_CMP_LG_F16
4008 
4009  GPUStaticInst*
4011  {
4012  return new Inst_VOP3__V_CMP_GE_F16(&iFmt->iFmt_VOP3);
4013  } // decode_OPU_VOP3__V_CMP_GE_F16
4014 
4015  GPUStaticInst*
4017  {
4018  return new Inst_VOP3__V_CMP_O_F16(&iFmt->iFmt_VOP3);
4019  } // decode_OPU_VOP3__V_CMP_O_F16
4020 
4021  GPUStaticInst*
4023  {
4024  return new Inst_VOP3__V_CMP_U_F16(&iFmt->iFmt_VOP3);
4025  } // decode_OPU_VOP3__V_CMP_U_F16
4026 
4027  GPUStaticInst*
4029  {
4030  return new Inst_VOP3__V_CMP_NGE_F16(&iFmt->iFmt_VOP3);
4031  } // decode_OPU_VOP3__V_CMP_NGE_F16
4032 
4033  GPUStaticInst*
4035  {
4036  return new Inst_VOP3__V_CMP_NLG_F16(&iFmt->iFmt_VOP3);
4037  } // decode_OPU_VOP3__V_CMP_NLG_F16
4038 
4039  GPUStaticInst*
4041  {
4042  return new Inst_VOP3__V_CMP_NGT_F16(&iFmt->iFmt_VOP3);
4043  } // decode_OPU_VOP3__V_CMP_NGT_F16
4044 
4045  GPUStaticInst*
4047  {
4048  return new Inst_VOP3__V_CMP_NLE_F16(&iFmt->iFmt_VOP3);
4049  } // decode_OPU_VOP3__V_CMP_NLE_F16
4050 
4051  GPUStaticInst*
4053  {
4054  return new Inst_VOP3__V_CMP_NEQ_F16(&iFmt->iFmt_VOP3);
4055  } // decode_OPU_VOP3__V_CMP_NEQ_F16
4056 
4057  GPUStaticInst*
4059  {
4060  return new Inst_VOP3__V_CMP_NLT_F16(&iFmt->iFmt_VOP3);
4061  } // decode_OPU_VOP3__V_CMP_NLT_F16
4062 
4063  GPUStaticInst*
4065  {
4066  return new Inst_VOP3__V_CMP_TRU_F16(&iFmt->iFmt_VOP3);
4067  } // decode_OPU_VOP3__V_CMP_TRU_F16
4068 
4069  GPUStaticInst*
4071  {
4072  return new Inst_VOP3__V_CMPX_F_F16(&iFmt->iFmt_VOP3);
4073  } // decode_OPU_VOP3__V_CMPX_F_F16
4074 
4075  GPUStaticInst*
4077  {
4078  return new Inst_VOP3__V_CMPX_LT_F16(&iFmt->iFmt_VOP3);
4079  } // decode_OPU_VOP3__V_CMPX_LT_F16
4080 
4081  GPUStaticInst*
4083  {
4084  return new Inst_VOP3__V_CMPX_EQ_F16(&iFmt->iFmt_VOP3);
4085  } // decode_OPU_VOP3__V_CMPX_EQ_F16
4086 
4087  GPUStaticInst*
4089  {
4090  return new Inst_VOP3__V_CMPX_LE_F16(&iFmt->iFmt_VOP3);
4091  } // decode_OPU_VOP3__V_CMPX_LE_F16
4092 
4093  GPUStaticInst*
4095  {
4096  return new Inst_VOP3__V_CMPX_GT_F16(&iFmt->iFmt_VOP3);
4097  } // decode_OPU_VOP3__V_CMPX_GT_F16
4098 
4099  GPUStaticInst*
4101  {
4102  return new Inst_VOP3__V_CMPX_LG_F16(&iFmt->iFmt_VOP3);
4103  } // decode_OPU_VOP3__V_CMPX_LG_F16
4104 
4105  GPUStaticInst*
4107  {
4108  return new Inst_VOP3__V_CMPX_GE_F16(&iFmt->iFmt_VOP3);
4109  } // decode_OPU_VOP3__V_CMPX_GE_F16
4110 
4111  GPUStaticInst*
4113  {
4114  return new Inst_VOP3__V_CMPX_O_F16(&iFmt->iFmt_VOP3);
4115  } // decode_OPU_VOP3__V_CMPX_O_F16
4116 
4117  GPUStaticInst*
4119  {
4120  return new Inst_VOP3__V_CMPX_U_F16(&iFmt->iFmt_VOP3);
4121  } // decode_OPU_VOP3__V_CMPX_U_F16
4122 
4123  GPUStaticInst*
4125  {
4126  return new Inst_VOP3__V_CMPX_NGE_F16(&iFmt->iFmt_VOP3);
4127  } // decode_OPU_VOP3__V_CMPX_NGE_F16
4128 
4129  GPUStaticInst*
4131  {
4132  return new Inst_VOP3__V_CMPX_NLG_F16(&iFmt->iFmt_VOP3);
4133  } // decode_OPU_VOP3__V_CMPX_NLG_F16
4134 
4135  GPUStaticInst*
4137  {
4138  return new Inst_VOP3__V_CMPX_NGT_F16(&iFmt->iFmt_VOP3);
4139  } // decode_OPU_VOP3__V_CMPX_NGT_F16
4140 
4141  GPUStaticInst*
4143  {
4144  return new Inst_VOP3__V_CMPX_NLE_F16(&iFmt->iFmt_VOP3);
4145  } // decode_OPU_VOP3__V_CMPX_NLE_F16
4146 
4147  GPUStaticInst*
4149  {
4150  return new Inst_VOP3__V_CMPX_NEQ_F16(&iFmt->iFmt_VOP3);
4151  } // decode_OPU_VOP3__V_CMPX_NEQ_F16
4152 
4153  GPUStaticInst*
4155  {
4156  return new Inst_VOP3__V_CMPX_NLT_F16(&iFmt->iFmt_VOP3);
4157  } // decode_OPU_VOP3__V_CMPX_NLT_F16
4158 
4159  GPUStaticInst*
4161  {
4162  return new Inst_VOP3__V_CMPX_TRU_F16(&iFmt->iFmt_VOP3);
4163  } // decode_OPU_VOP3__V_CMPX_TRU_F16
4164 
4165  GPUStaticInst*
4167  {
4168  return new Inst_VOP3__V_CMP_F_F32(&iFmt->iFmt_VOP3);
4169  } // decode_OPU_VOP3__V_CMP_F_F32
4170 
4171  GPUStaticInst*
4173  {
4174  return new Inst_VOP3__V_CMP_LT_F32(&iFmt->iFmt_VOP3);
4175  } // decode_OPU_VOP3__V_CMP_LT_F32
4176 
4177  GPUStaticInst*
4179  {
4180  return new Inst_VOP3__V_CMP_EQ_F32(&iFmt->iFmt_VOP3);
4181  } // decode_OPU_VOP3__V_CMP_EQ_F32
4182 
4183  GPUStaticInst*
4185  {
4186  return new Inst_VOP3__V_CMP_LE_F32(&iFmt->iFmt_VOP3);
4187  } // decode_OPU_VOP3__V_CMP_LE_F32
4188 
4189  GPUStaticInst*
4191  {
4192  return new Inst_VOP3__V_CMP_GT_F32(&iFmt->iFmt_VOP3);
4193  } // decode_OPU_VOP3__V_CMP_GT_F32
4194 
4195  GPUStaticInst*
4197  {
4198  return new Inst_VOP3__V_CMP_LG_F32(&iFmt->iFmt_VOP3);
4199  } // decode_OPU_VOP3__V_CMP_LG_F32
4200 
4201  GPUStaticInst*
4203  {
4204  return new Inst_VOP3__V_CMP_GE_F32(&iFmt->iFmt_VOP3);
4205  } // decode_OPU_VOP3__V_CMP_GE_F32
4206 
4207  GPUStaticInst*
4209  {
4210  return new Inst_VOP3__V_CMP_O_F32(&iFmt->iFmt_VOP3);
4211  } // decode_OPU_VOP3__V_CMP_O_F32
4212 
4213  GPUStaticInst*
4215  {
4216  return new Inst_VOP3__V_CMP_U_F32(&iFmt->iFmt_VOP3);
4217  } // decode_OPU_VOP3__V_CMP_U_F32
4218 
4219  GPUStaticInst*
4221  {
4222  return new Inst_VOP3__V_CMP_NGE_F32(&iFmt->iFmt_VOP3);
4223  } // decode_OPU_VOP3__V_CMP_NGE_F32
4224 
4225  GPUStaticInst*
4227  {
4228  return new Inst_VOP3__V_CMP_NLG_F32(&iFmt->iFmt_VOP3);
4229  } // decode_OPU_VOP3__V_CMP_NLG_F32
4230 
4231  GPUStaticInst*
4233  {
4234  return new Inst_VOP3__V_CMP_NGT_F32(&iFmt->iFmt_VOP3);
4235  } // decode_OPU_VOP3__V_CMP_NGT_F32
4236 
4237  GPUStaticInst*
4239  {
4240  return new Inst_VOP3__V_CMP_NLE_F32(&iFmt->iFmt_VOP3);
4241  } // decode_OPU_VOP3__V_CMP_NLE_F32
4242 
4243  GPUStaticInst*
4245  {
4246  return new Inst_VOP3__V_CMP_NEQ_F32(&iFmt->iFmt_VOP3);
4247  } // decode_OPU_VOP3__V_CMP_NEQ_F32
4248 
4249  GPUStaticInst*
4251  {
4252  return new Inst_VOP3__V_CMP_NLT_F32(&iFmt->iFmt_VOP3);
4253  } // decode_OPU_VOP3__V_CMP_NLT_F32
4254 
4255  GPUStaticInst*
4257  {
4258  return new Inst_VOP3__V_CMP_TRU_F32(&iFmt->iFmt_VOP3);
4259  } // decode_OPU_VOP3__V_CMP_TRU_F32
4260 
4261  GPUStaticInst*
4263  {
4264  return new Inst_VOP3__V_CMPX_F_F32(&iFmt->iFmt_VOP3);
4265  } // decode_OPU_VOP3__V_CMPX_F_F32
4266 
4267  GPUStaticInst*
4269  {
4270  return new Inst_VOP3__V_CMPX_LT_F32(&iFmt->iFmt_VOP3);
4271  } // decode_OPU_VOP3__V_CMPX_LT_F32
4272 
4273  GPUStaticInst*
4275  {
4276  return new Inst_VOP3__V_CMPX_EQ_F32(&iFmt->iFmt_VOP3);
4277  } // decode_OPU_VOP3__V_CMPX_EQ_F32
4278 
4279  GPUStaticInst*
4281  {
4282  return new Inst_VOP3__V_CMPX_LE_F32(&iFmt->iFmt_VOP3);
4283  } // decode_OPU_VOP3__V_CMPX_LE_F32
4284 
4285  GPUStaticInst*
4287  {
4288  return new Inst_VOP3__V_CMPX_GT_F32(&iFmt->iFmt_VOP3);
4289  } // decode_OPU_VOP3__V_CMPX_GT_F32
4290 
4291  GPUStaticInst*
4293  {
4294  return new Inst_VOP3__V_CMPX_LG_F32(&iFmt->iFmt_VOP3);
4295  } // decode_OPU_VOP3__V_CMPX_LG_F32
4296 
4297  GPUStaticInst*
4299  {
4300  return new Inst_VOP3__V_CMPX_GE_F32(&iFmt->iFmt_VOP3);
4301  } // decode_OPU_VOP3__V_CMPX_GE_F32
4302 
4303  GPUStaticInst*
4305  {
4306  return new Inst_VOP3__V_CMPX_O_F32(&iFmt->iFmt_VOP3);
4307  } // decode_OPU_VOP3__V_CMPX_O_F32
4308 
4309  GPUStaticInst*
4311  {
4312  return new Inst_VOP3__V_CMPX_U_F32(&iFmt->iFmt_VOP3);
4313  } // decode_OPU_VOP3__V_CMPX_U_F32
4314 
4315  GPUStaticInst*
4317  {
4318  return new Inst_VOP3__V_CMPX_NGE_F32(&iFmt->iFmt_VOP3);
4319  } // decode_OPU_VOP3__V_CMPX_NGE_F32
4320 
4321  GPUStaticInst*
4323  {
4324  return new Inst_VOP3__V_CMPX_NLG_F32(&iFmt->iFmt_VOP3);
4325  } // decode_OPU_VOP3__V_CMPX_NLG_F32
4326 
4327  GPUStaticInst*
4329  {
4330  return new Inst_VOP3__V_CMPX_NGT_F32(&iFmt->iFmt_VOP3);
4331  } // decode_OPU_VOP3__V_CMPX_NGT_F32
4332 
4333  GPUStaticInst*
4335  {
4336  return new Inst_VOP3__V_CMPX_NLE_F32(&iFmt->iFmt_VOP3);
4337  } // decode_OPU_VOP3__V_CMPX_NLE_F32
4338 
4339  GPUStaticInst*
4341  {
4342  return new Inst_VOP3__V_CMPX_NEQ_F32(&iFmt->iFmt_VOP3);
4343  } // decode_OPU_VOP3__V_CMPX_NEQ_F32
4344 
4345  GPUStaticInst*
4347  {
4348  return new Inst_VOP3__V_CMPX_NLT_F32(&iFmt->iFmt_VOP3);
4349  } // decode_OPU_VOP3__V_CMPX_NLT_F32
4350 
4351  GPUStaticInst*
4353  {
4354  return new Inst_VOP3__V_CMPX_TRU_F32(&iFmt->iFmt_VOP3);
4355  } // decode_OPU_VOP3__V_CMPX_TRU_F32
4356 
4357  GPUStaticInst*
4359  {
4360  return new Inst_VOP3__V_CMP_F_F64(&iFmt->iFmt_VOP3);
4361  } // decode_OPU_VOP3__V_CMP_F_F64
4362 
4363  GPUStaticInst*
4365  {
4366  return new Inst_VOP3__V_CMP_LT_F64(&iFmt->iFmt_VOP3);
4367  } // decode_OPU_VOP3__V_CMP_LT_F64
4368 
4369  GPUStaticInst*
4371  {
4372  return new Inst_VOP3__V_CMP_EQ_F64(&iFmt->iFmt_VOP3);
4373  } // decode_OPU_VOP3__V_CMP_EQ_F64
4374 
4375  GPUStaticInst*
4377  {
4378  return new Inst_VOP3__V_CMP_LE_F64(&iFmt->iFmt_VOP3);
4379  } // decode_OPU_VOP3__V_CMP_LE_F64
4380 
4381  GPUStaticInst*
4383  {
4384  return new Inst_VOP3__V_CMP_GT_F64(&iFmt->iFmt_VOP3);
4385  } // decode_OPU_VOP3__V_CMP_GT_F64
4386 
4387  GPUStaticInst*
4389  {
4390  return new Inst_VOP3__V_CMP_LG_F64(&iFmt->iFmt_VOP3);
4391  } // decode_OPU_VOP3__V_CMP_LG_F64
4392 
4393  GPUStaticInst*
4395  {
4396  return new Inst_VOP3__V_CMP_GE_F64(&iFmt->iFmt_VOP3);
4397  } // decode_OPU_VOP3__V_CMP_GE_F64
4398 
4399  GPUStaticInst*
4401  {
4402  return new Inst_VOP3__V_CMP_O_F64(&iFmt->iFmt_VOP3);
4403  } // decode_OPU_VOP3__V_CMP_O_F64
4404 
4405  GPUStaticInst*
4407  {
4408  return new Inst_VOP3__V_CMP_U_F64(&iFmt->iFmt_VOP3);
4409  } // decode_OPU_VOP3__V_CMP_U_F64
4410 
4411  GPUStaticInst*
4413  {
4414  return new Inst_VOP3__V_CMP_NGE_F64(&iFmt->iFmt_VOP3);
4415  } // decode_OPU_VOP3__V_CMP_NGE_F64
4416 
4417  GPUStaticInst*
4419  {
4420  return new Inst_VOP3__V_CMP_NLG_F64(&iFmt->iFmt_VOP3);
4421  } // decode_OPU_VOP3__V_CMP_NLG_F64
4422 
4423  GPUStaticInst*
4425  {
4426  return new Inst_VOP3__V_CMP_NGT_F64(&iFmt->iFmt_VOP3);
4427  } // decode_OPU_VOP3__V_CMP_NGT_F64
4428 
4429  GPUStaticInst*
4431  {
4432  return new Inst_VOP3__V_CMP_NLE_F64(&iFmt->iFmt_VOP3);
4433  } // decode_OPU_VOP3__V_CMP_NLE_F64
4434 
4435  GPUStaticInst*
4437  {
4438  return new Inst_VOP3__V_CMP_NEQ_F64(&iFmt->iFmt_VOP3);
4439  } // decode_OPU_VOP3__V_CMP_NEQ_F64
4440 
4441  GPUStaticInst*
4443  {
4444  return new Inst_VOP3__V_CMP_NLT_F64(&iFmt->iFmt_VOP3);
4445  } // decode_OPU_VOP3__V_CMP_NLT_F64
4446 
4447  GPUStaticInst*
4449  {
4450  return new Inst_VOP3__V_CMP_TRU_F64(&iFmt->iFmt_VOP3);
4451  } // decode_OPU_VOP3__V_CMP_TRU_F64
4452 
4453  GPUStaticInst*
4455  {
4456  return new Inst_VOP3__V_CMPX_F_F64(&iFmt->iFmt_VOP3);
4457  } // decode_OPU_VOP3__V_CMPX_F_F64
4458 
4459  GPUStaticInst*
4461  {
4462  return new Inst_VOP3__V_CMPX_LT_F64(&iFmt->iFmt_VOP3);
4463  } // decode_OPU_VOP3__V_CMPX_LT_F64
4464 
4465  GPUStaticInst*
4467  {
4468  return new Inst_VOP3__V_CMPX_EQ_F64(&iFmt->iFmt_VOP3);
4469  } // decode_OPU_VOP3__V_CMPX_EQ_F64
4470 
4471  GPUStaticInst*
4473  {
4474  return new Inst_VOP3__V_CMPX_LE_F64(&iFmt->iFmt_VOP3);
4475  } // decode_OPU_VOP3__V_CMPX_LE_F64
4476 
4477  GPUStaticInst*
4479  {
4480  return new Inst_VOP3__V_CMPX_GT_F64(&iFmt->iFmt_VOP3);
4481  } // decode_OPU_VOP3__V_CMPX_GT_F64
4482 
4483  GPUStaticInst*
4485  {
4486  return new Inst_VOP3__V_CMPX_LG_F64(&iFmt->iFmt_VOP3);
4487  } // decode_OPU_VOP3__V_CMPX_LG_F64
4488 
4489  GPUStaticInst*
4491  {
4492  return new Inst_VOP3__V_CMPX_GE_F64(&iFmt->iFmt_VOP3);
4493  } // decode_OPU_VOP3__V_CMPX_GE_F64
4494 
4495  GPUStaticInst*
4497  {
4498  return new Inst_VOP3__V_CMPX_O_F64(&iFmt->iFmt_VOP3);
4499  } // decode_OPU_VOP3__V_CMPX_O_F64
4500 
4501  GPUStaticInst*
4503  {
4504  return new Inst_VOP3__V_CMPX_U_F64(&iFmt->iFmt_VOP3);
4505  } // decode_OPU_VOP3__V_CMPX_U_F64
4506 
4507  GPUStaticInst*
4509  {
4510  return new Inst_VOP3__V_CMPX_NGE_F64(&iFmt->iFmt_VOP3);
4511  } // decode_OPU_VOP3__V_CMPX_NGE_F64
4512 
4513  GPUStaticInst*
4515  {
4516  return new Inst_VOP3__V_CMPX_NLG_F64(&iFmt->iFmt_VOP3);
4517  } // decode_OPU_VOP3__V_CMPX_NLG_F64
4518 
4519  GPUStaticInst*
4521  {
4522  return new Inst_VOP3__V_CMPX_NGT_F64(&iFmt->iFmt_VOP3);
4523  } // decode_OPU_VOP3__V_CMPX_NGT_F64
4524 
4525  GPUStaticInst*
4527  {
4528  return new Inst_VOP3__V_CMPX_NLE_F64(&iFmt->iFmt_VOP3);
4529  } // decode_OPU_VOP3__V_CMPX_NLE_F64
4530 
4531  GPUStaticInst*
4533  {
4534  return new Inst_VOP3__V_CMPX_NEQ_F64(&iFmt->iFmt_VOP3);
4535  } // decode_OPU_VOP3__V_CMPX_NEQ_F64
4536 
4537  GPUStaticInst*
4539  {
4540  return new Inst_VOP3__V_CMPX_NLT_F64(&iFmt->iFmt_VOP3);
4541  } // decode_OPU_VOP3__V_CMPX_NLT_F64
4542 
4543  GPUStaticInst*
4545  {
4546  return new Inst_VOP3__V_CMPX_TRU_F64(&iFmt->iFmt_VOP3);
4547  } // decode_OPU_VOP3__V_CMPX_TRU_F64
4548 
4549  GPUStaticInst*
4551  {
4552  return new Inst_VOP3__V_CMP_F_I16(&iFmt->iFmt_VOP3);
4553  } // decode_OPU_VOP3__V_CMP_F_I16
4554 
4555  GPUStaticInst*
4557  {
4558  return new Inst_VOP3__V_CMP_LT_I16(&iFmt->iFmt_VOP3);
4559  } // decode_OPU_VOP3__V_CMP_LT_I16
4560 
4561  GPUStaticInst*
4563  {
4564  return new Inst_VOP3__V_CMP_EQ_I16(&iFmt->iFmt_VOP3);
4565  } // decode_OPU_VOP3__V_CMP_EQ_I16
4566 
4567  GPUStaticInst*
4569  {
4570  return new Inst_VOP3__V_CMP_LE_I16(&iFmt->iFmt_VOP3);
4571  } // decode_OPU_VOP3__V_CMP_LE_I16
4572 
4573  GPUStaticInst*
4575  {
4576  return new Inst_VOP3__V_CMP_GT_I16(&iFmt->iFmt_VOP3);
4577  } // decode_OPU_VOP3__V_CMP_GT_I16
4578 
4579  GPUStaticInst*
4581  {
4582  return new Inst_VOP3__V_CMP_NE_I16(&iFmt->iFmt_VOP3);
4583  } // decode_OPU_VOP3__V_CMP_NE_I16
4584 
4585  GPUStaticInst*
4587  {
4588  return new Inst_VOP3__V_CMP_GE_I16(&iFmt->iFmt_VOP3);
4589  } // decode_OPU_VOP3__V_CMP_GE_I16
4590 
4591  GPUStaticInst*
4593  {
4594  return new Inst_VOP3__V_CMP_T_I16(&iFmt->iFmt_VOP3);
4595  } // decode_OPU_VOP3__V_CMP_T_I16
4596 
4597  GPUStaticInst*
4599  {
4600  return new Inst_VOP3__V_CMP_F_U16(&iFmt->iFmt_VOP3);
4601  } // decode_OPU_VOP3__V_CMP_F_U16
4602 
4603  GPUStaticInst*
4605  {
4606  return new Inst_VOP3__V_CMP_LT_U16(&iFmt->iFmt_VOP3);
4607  } // decode_OPU_VOP3__V_CMP_LT_U16
4608 
4609  GPUStaticInst*
4611  {
4612  return new Inst_VOP3__V_CMP_EQ_U16(&iFmt->iFmt_VOP3);
4613  } // decode_OPU_VOP3__V_CMP_EQ_U16
4614 
4615  GPUStaticInst*
4617  {
4618  return new Inst_VOP3__V_CMP_LE_U16(&iFmt->iFmt_VOP3);
4619  } // decode_OPU_VOP3__V_CMP_LE_U16
4620 
4621  GPUStaticInst*
4623  {
4624  return new Inst_VOP3__V_CMP_GT_U16(&iFmt->iFmt_VOP3);
4625  } // decode_OPU_VOP3__V_CMP_GT_U16
4626 
4627  GPUStaticInst*
4629  {
4630  return new Inst_VOP3__V_CMP_NE_U16(&iFmt->iFmt_VOP3);
4631  } // decode_OPU_VOP3__V_CMP_NE_U16
4632 
4633  GPUStaticInst*
4635  {
4636  return new Inst_VOP3__V_CMP_GE_U16(&iFmt->iFmt_VOP3);
4637  } // decode_OPU_VOP3__V_CMP_GE_U16
4638 
4639  GPUStaticInst*
4641  {
4642  return new Inst_VOP3__V_CMP_T_U16(&iFmt->iFmt_VOP3);
4643  } // decode_OPU_VOP3__V_CMP_T_U16
4644 
4645  GPUStaticInst*
4647  {
4648  return new Inst_VOP3__V_CMPX_F_I16(&iFmt->iFmt_VOP3);
4649  } // decode_OPU_VOP3__V_CMPX_F_I16
4650 
4651  GPUStaticInst*
4653  {
4654  return new Inst_VOP3__V_CMPX_LT_I16(&iFmt->iFmt_VOP3);
4655  } // decode_OPU_VOP3__V_CMPX_LT_I16
4656 
4657  GPUStaticInst*
4659  {
4660  return new Inst_VOP3__V_CMPX_EQ_I16(&iFmt->iFmt_VOP3);
4661  } // decode_OPU_VOP3__V_CMPX_EQ_I16
4662 
4663  GPUStaticInst*
4665  {
4666  return new Inst_VOP3__V_CMPX_LE_I16(&iFmt->iFmt_VOP3);
4667  } // decode_OPU_VOP3__V_CMPX_LE_I16
4668 
4669  GPUStaticInst*
4671  {
4672  return new Inst_VOP3__V_CMPX_GT_I16(&iFmt->iFmt_VOP3);
4673  } // decode_OPU_VOP3__V_CMPX_GT_I16
4674 
4675  GPUStaticInst*
4677  {
4678  return new Inst_VOP3__V_CMPX_NE_I16(&iFmt->iFmt_VOP3);
4679  } // decode_OPU_VOP3__V_CMPX_NE_I16
4680 
4681  GPUStaticInst*
4683  {
4684  return new Inst_VOP3__V_CMPX_GE_I16(&iFmt->iFmt_VOP3);
4685  } // decode_OPU_VOP3__V_CMPX_GE_I16
4686 
4687  GPUStaticInst*
4689  {
4690  return new Inst_VOP3__V_CMPX_T_I16(&iFmt->iFmt_VOP3);
4691  } // decode_OPU_VOP3__V_CMPX_T_I16
4692 
4693  GPUStaticInst*
4695  {
4696  return new Inst_VOP3__V_CMPX_F_U16(&iFmt->iFmt_VOP3);
4697  } // decode_OPU_VOP3__V_CMPX_F_U16
4698 
4699  GPUStaticInst*
4701  {
4702  return new Inst_VOP3__V_CMPX_LT_U16(&iFmt->iFmt_VOP3);
4703  } // decode_OPU_VOP3__V_CMPX_LT_U16
4704 
4705  GPUStaticInst*
4707  {
4708  return new Inst_VOP3__V_CMPX_EQ_U16(&iFmt->iFmt_VOP3);
4709  } // decode_OPU_VOP3__V_CMPX_EQ_U16
4710 
4711  GPUStaticInst*
4713  {
4714  return new Inst_VOP3__V_CMPX_LE_U16(&iFmt->iFmt_VOP3);
4715  } // decode_OPU_VOP3__V_CMPX_LE_U16
4716 
4717  GPUStaticInst*
4719  {
4720  return new Inst_VOP3__V_CMPX_GT_U16(&iFmt->iFmt_VOP3);
4721  } // decode_OPU_VOP3__V_CMPX_GT_U16
4722 
4723  GPUStaticInst*
4725  {
4726  return new Inst_VOP3__V_CMPX_NE_U16(&iFmt->iFmt_VOP3);
4727  } // decode_OPU_VOP3__V_CMPX_NE_U16
4728 
4729  GPUStaticInst*
4731  {
4732  return new Inst_VOP3__V_CMPX_GE_U16(&iFmt->iFmt_VOP3);
4733  } // decode_OPU_VOP3__V_CMPX_GE_U16
4734 
4735  GPUStaticInst*
4737  {
4738  return new Inst_VOP3__V_CMPX_T_U16(&iFmt->iFmt_VOP3);
4739  } // decode_OPU_VOP3__V_CMPX_T_U16
4740 
4741  GPUStaticInst*
4743  {
4744  return new Inst_VOP3__V_CMP_F_I32(&iFmt->iFmt_VOP3);
4745  } // decode_OPU_VOP3__V_CMP_F_I32
4746 
4747  GPUStaticInst*
4749  {
4750  return new Inst_VOP3__V_CMP_LT_I32(&iFmt->iFmt_VOP3);
4751  } // decode_OPU_VOP3__V_CMP_LT_I32
4752 
4753  GPUStaticInst*
4755  {
4756  return new Inst_VOP3__V_CMP_EQ_I32(&iFmt->iFmt_VOP3);
4757  } // decode_OPU_VOP3__V_CMP_EQ_I32
4758 
4759  GPUStaticInst*
4761  {
4762  return new Inst_VOP3__V_CMP_LE_I32(&iFmt->iFmt_VOP3);
4763  } // decode_OPU_VOP3__V_CMP_LE_I32
4764 
4765  GPUStaticInst*
4767  {
4768  return new Inst_VOP3__V_CMP_GT_I32(&iFmt->iFmt_VOP3);
4769  } // decode_OPU_VOP3__V_CMP_GT_I32
4770 
4771  GPUStaticInst*
4773  {
4774  return new Inst_VOP3__V_CMP_NE_I32(&iFmt->iFmt_VOP3);
4775  } // decode_OPU_VOP3__V_CMP_NE_I32
4776 
4777  GPUStaticInst*
4779  {
4780  return new Inst_VOP3__V_CMP_GE_I32(&iFmt->iFmt_VOP3);
4781  } // decode_OPU_VOP3__V_CMP_GE_I32
4782 
4783  GPUStaticInst*
4785  {
4786  return new Inst_VOP3__V_CMP_T_I32(&iFmt->iFmt_VOP3);
4787  } // decode_OPU_VOP3__V_CMP_T_I32
4788 
4789  GPUStaticInst*
4791  {
4792  return new Inst_VOP3__V_CMP_F_U32(&iFmt->iFmt_VOP3);
4793  } // decode_OPU_VOP3__V_CMP_F_U32
4794 
4795  GPUStaticInst*
4797  {
4798  return new Inst_VOP3__V_CMP_LT_U32(&iFmt->iFmt_VOP3);
4799  } // decode_OPU_VOP3__V_CMP_LT_U32
4800 
4801  GPUStaticInst*
4803  {
4804  return new Inst_VOP3__V_CMP_EQ_U32(&iFmt->iFmt_VOP3);
4805  } // decode_OPU_VOP3__V_CMP_EQ_U32
4806 
4807  GPUStaticInst*
4809  {
4810  return new Inst_VOP3__V_CMP_LE_U32(&iFmt->iFmt_VOP3);
4811  } // decode_OPU_VOP3__V_CMP_LE_U32
4812 
4813  GPUStaticInst*
4815  {
4816  return new Inst_VOP3__V_CMP_GT_U32(&iFmt->iFmt_VOP3);
4817  } // decode_OPU_VOP3__V_CMP_GT_U32
4818 
4819  GPUStaticInst*
4821  {
4822  return new Inst_VOP3__V_CMP_NE_U32(&iFmt->iFmt_VOP3);
4823  } // decode_OPU_VOP3__V_CMP_NE_U32
4824 
4825  GPUStaticInst*
4827  {
4828  return new Inst_VOP3__V_CMP_GE_U32(&iFmt->iFmt_VOP3);
4829  } // decode_OPU_VOP3__V_CMP_GE_U32
4830 
4831  GPUStaticInst*
4833  {
4834  return new Inst_VOP3__V_CMP_T_U32(&iFmt->iFmt_VOP3);
4835  } // decode_OPU_VOP3__V_CMP_T_U32
4836 
4837  GPUStaticInst*
4839  {
4840  return new Inst_VOP3__V_CMPX_F_I32(&iFmt->iFmt_VOP3);
4841  } // decode_OPU_VOP3__V_CMPX_F_I32
4842 
4843  GPUStaticInst*
4845  {
4846  return new Inst_VOP3__V_CMPX_LT_I32(&iFmt->iFmt_VOP3);
4847  } // decode_OPU_VOP3__V_CMPX_LT_I32
4848 
4849  GPUStaticInst*
4851  {
4852  return new Inst_VOP3__V_CMPX_EQ_I32(&iFmt->iFmt_VOP3);
4853  } // decode_OPU_VOP3__V_CMPX_EQ_I32
4854 
4855  GPUStaticInst*
4857  {
4858  return new Inst_VOP3__V_CMPX_LE_I32(&iFmt->iFmt_VOP3);
4859  } // decode_OPU_VOP3__V_CMPX_LE_I32
4860 
4861  GPUStaticInst*
4863  {
4864  return new Inst_VOP3__V_CMPX_GT_I32(&iFmt->iFmt_VOP3);
4865  } // decode_OPU_VOP3__V_CMPX_GT_I32
4866 
4867  GPUStaticInst*
4869  {
4870  return new Inst_VOP3__V_CMPX_NE_I32(&iFmt->iFmt_VOP3);
4871  } // decode_OPU_VOP3__V_CMPX_NE_I32
4872 
4873  GPUStaticInst*
4875  {
4876  return new Inst_VOP3__V_CMPX_GE_I32(&iFmt->iFmt_VOP3);
4877  } // decode_OPU_VOP3__V_CMPX_GE_I32
4878 
4879  GPUStaticInst*
4881  {
4882  return new Inst_VOP3__V_CMPX_T_I32(&iFmt->iFmt_VOP3);
4883  } // decode_OPU_VOP3__V_CMPX_T_I32
4884 
4885  GPUStaticInst*
4887  {
4888  return new Inst_VOP3__V_CMPX_F_U32(&iFmt->iFmt_VOP3);
4889  } // decode_OPU_VOP3__V_CMPX_F_U32
4890 
4891  GPUStaticInst*
4893  {
4894  return new Inst_VOP3__V_CMPX_LT_U32(&iFmt->iFmt_VOP3);
4895  } // decode_OPU_VOP3__V_CMPX_LT_U32
4896 
4897  GPUStaticInst*
4899  {
4900  return new Inst_VOP3__V_CMPX_EQ_U32(&iFmt->iFmt_VOP3);
4901  } // decode_OPU_VOP3__V_CMPX_EQ_U32
4902 
4903  GPUStaticInst*
4905  {
4906  return new Inst_VOP3__V_CMPX_LE_U32(&iFmt->iFmt_VOP3);
4907  } // decode_OPU_VOP3__V_CMPX_LE_U32
4908 
4909  GPUStaticInst*
4911  {
4912  return new Inst_VOP3__V_CMPX_GT_U32(&iFmt->iFmt_VOP3);
4913  } // decode_OPU_VOP3__V_CMPX_GT_U32
4914 
4915  GPUStaticInst*
4917  {
4918  return new Inst_VOP3__V_CMPX_NE_U32(&iFmt->iFmt_VOP3);
4919  } // decode_OPU_VOP3__V_CMPX_NE_U32
4920 
4921  GPUStaticInst*
4923  {
4924  return new Inst_VOP3__V_CMPX_GE_U32(&iFmt->iFmt_VOP3);
4925  } // decode_OPU_VOP3__V_CMPX_GE_U32
4926 
4927  GPUStaticInst*
4929  {
4930  return new Inst_VOP3__V_CMPX_T_U32(&iFmt->iFmt_VOP3);
4931  } // decode_OPU_VOP3__V_CMPX_T_U32
4932 
4933  GPUStaticInst*
4935  {
4936  return new Inst_VOP3__V_CMP_F_I64(&iFmt->iFmt_VOP3);
4937  } // decode_OPU_VOP3__V_CMP_F_I64
4938 
4939  GPUStaticInst*
4941  {
4942  return new Inst_VOP3__V_CMP_LT_I64(&iFmt->iFmt_VOP3);
4943  } // decode_OPU_VOP3__V_CMP_LT_I64
4944 
4945  GPUStaticInst*
4947  {
4948  return new Inst_VOP3__V_CMP_EQ_I64(&iFmt->iFmt_VOP3);
4949  } // decode_OPU_VOP3__V_CMP_EQ_I64
4950 
4951  GPUStaticInst*
4953  {
4954  return new Inst_VOP3__V_CMP_LE_I64(&iFmt->iFmt_VOP3);
4955  } // decode_OPU_VOP3__V_CMP_LE_I64
4956 
4957  GPUStaticInst*
4959  {
4960  return new Inst_VOP3__V_CMP_GT_I64(&iFmt->iFmt_VOP3);
4961  } // decode_OPU_VOP3__V_CMP_GT_I64
4962 
4963  GPUStaticInst*
4965  {
4966  return new Inst_VOP3__V_CMP_NE_I64(&iFmt->iFmt_VOP3);
4967  } // decode_OPU_VOP3__V_CMP_NE_I64
4968 
4969  GPUStaticInst*
4971  {
4972  return new Inst_VOP3__V_CMP_GE_I64(&iFmt->iFmt_VOP3);
4973  } // decode_OPU_VOP3__V_CMP_GE_I64
4974 
4975  GPUStaticInst*
4977  {
4978  return new Inst_VOP3__V_CMP_T_I64(&iFmt->iFmt_VOP3);
4979  } // decode_OPU_VOP3__V_CMP_T_I64
4980 
4981  GPUStaticInst*
4983  {
4984  return new Inst_VOP3__V_CMP_F_U64(&iFmt->iFmt_VOP3);
4985  } // decode_OPU_VOP3__V_CMP_F_U64
4986 
4987  GPUStaticInst*
4989  {
4990  return new Inst_VOP3__V_CMP_LT_U64(&iFmt->iFmt_VOP3);
4991  } // decode_OPU_VOP3__V_CMP_LT_U64
4992 
4993  GPUStaticInst*
4995  {
4996  return new Inst_VOP3__V_CMP_EQ_U64(&iFmt->iFmt_VOP3);
4997  } // decode_OPU_VOP3__V_CMP_EQ_U64
4998 
4999  GPUStaticInst*
5001  {
5002  return new Inst_VOP3__V_CMP_LE_U64(&iFmt->iFmt_VOP3);
5003  } // decode_OPU_VOP3__V_CMP_LE_U64
5004 
5005  GPUStaticInst*
5007  {
5008  return new Inst_VOP3__V_CMP_GT_U64(&iFmt->iFmt_VOP3);
5009  } // decode_OPU_VOP3__V_CMP_GT_U64
5010 
5011  GPUStaticInst*
5013  {
5014  return new Inst_VOP3__V_CMP_NE_U64(&iFmt->iFmt_VOP3);
5015  } // decode_OPU_VOP3__V_CMP_NE_U64
5016 
5017  GPUStaticInst*
5019  {
5020  return new Inst_VOP3__V_CMP_GE_U64(&iFmt->iFmt_VOP3);
5021  } // decode_OPU_VOP3__V_CMP_GE_U64
5022 
5023  GPUStaticInst*
5025  {
5026  return new Inst_VOP3__V_CMP_T_U64(&iFmt->iFmt_VOP3);
5027  } // decode_OPU_VOP3__V_CMP_T_U64
5028 
5029  GPUStaticInst*
5031  {
5032  return new Inst_VOP3__V_CMPX_F_I64(&iFmt->iFmt_VOP3);
5033  } // decode_OPU_VOP3__V_CMPX_F_I64
5034 
5035  GPUStaticInst*
5037  {
5038  return new Inst_VOP3__V_CMPX_LT_I64(&iFmt->iFmt_VOP3);
5039  } // decode_OPU_VOP3__V_CMPX_LT_I64
5040 
5041  GPUStaticInst*
5043  {
5044  return new Inst_VOP3__V_CMPX_EQ_I64(&iFmt->iFmt_VOP3);
5045  } // decode_OPU_VOP3__V_CMPX_EQ_I64
5046 
5047  GPUStaticInst*
5049  {
5050  return new Inst_VOP3__V_CMPX_LE_I64(&iFmt->iFmt_VOP3);
5051  } // decode_OPU_VOP3__V_CMPX_LE_I64
5052 
5053  GPUStaticInst*
5055  {
5056  return new Inst_VOP3__V_CMPX_GT_I64(&iFmt->iFmt_VOP3);
5057  } // decode_OPU_VOP3__V_CMPX_GT_I64
5058 
5059  GPUStaticInst*
5061  {
5062  return new Inst_VOP3__V_CMPX_NE_I64(&iFmt->iFmt_VOP3);
5063  } // decode_OPU_VOP3__V_CMPX_NE_I64
5064 
5065  GPUStaticInst*
5067  {
5068  return new Inst_VOP3__V_CMPX_GE_I64(&iFmt->iFmt_VOP3);
5069  } // decode_OPU_VOP3__V_CMPX_GE_I64
5070 
5071  GPUStaticInst*
5073  {
5074  return new Inst_VOP3__V_CMPX_T_I64(&iFmt->iFmt_VOP3);
5075  } // decode_OPU_VOP3__V_CMPX_T_I64
5076 
5077  GPUStaticInst*
5079  {
5080  return new Inst_VOP3__V_CMPX_F_U64(&iFmt->iFmt_VOP3);
5081  } // decode_OPU_VOP3__V_CMPX_F_U64
5082 
5083  GPUStaticInst*
5085  {
5086  return new Inst_VOP3__V_CMPX_LT_U64(&iFmt->iFmt_VOP3);
5087  } // decode_OPU_VOP3__V_CMPX_LT_U64
5088 
5089  GPUStaticInst*
5091  {
5092  return new Inst_VOP3__V_CMPX_EQ_U64(&iFmt->iFmt_VOP3);
5093  } // decode_OPU_VOP3__V_CMPX_EQ_U64
5094 
5095  GPUStaticInst*
5097  {
5098  return new Inst_VOP3__V_CMPX_LE_U64(&iFmt->iFmt_VOP3);
5099  } // decode_OPU_VOP3__V_CMPX_LE_U64
5100 
5101  GPUStaticInst*
5103  {
5104  return new Inst_VOP3__V_CMPX_GT_U64(&iFmt->iFmt_VOP3);
5105  } // decode_OPU_VOP3__V_CMPX_GT_U64
5106 
5107  GPUStaticInst*
5109  {
5110  return new Inst_VOP3__V_CMPX_NE_U64(&iFmt->iFmt_VOP3);
5111  } // decode_OPU_VOP3__V_CMPX_NE_U64
5112 
5113  GPUStaticInst*
5115  {
5116  return new Inst_VOP3__V_CMPX_GE_U64(&iFmt->iFmt_VOP3);
5117  } // decode_OPU_VOP3__V_CMPX_GE_U64
5118 
5119  GPUStaticInst*
5121  {
5122  return new Inst_VOP3__V_CMPX_T_U64(&iFmt->iFmt_VOP3);
5123  } // decode_OPU_VOP3__V_CMPX_T_U64
5124 
5125  GPUStaticInst*
5127  {
5128  return new Inst_VOP3__V_CNDMASK_B32(&iFmt->iFmt_VOP3);
5129  } // decode_OPU_VOP3__V_CNDMASK_B32
5130 
5131  GPUStaticInst*
5133  {
5134  return new Inst_VOP3__V_ADD_F32(&iFmt->iFmt_VOP3);
5135  } // decode_OPU_VOP3__V_ADD_F32
5136 
5137  GPUStaticInst*
5139  {
5140  return new Inst_VOP3__V_SUB_F32(&iFmt->iFmt_VOP3);
5141  } // decode_OPU_VOP3__V_SUB_F32
5142 
5143  GPUStaticInst*
5145  {
5146  return new Inst_VOP3__V_SUBREV_F32(&iFmt->iFmt_VOP3);
5147  } // decode_OPU_VOP3__V_SUBREV_F32
5148 
5149  GPUStaticInst*
5151  {
5152  return new Inst_VOP3__V_MUL_LEGACY_F32(&iFmt->iFmt_VOP3);
5153  } // decode_OPU_VOP3__V_MUL_LEGACY_F32
5154 
5155  GPUStaticInst*
5157  {
5158  return new Inst_VOP3__V_MUL_F32(&iFmt->iFmt_VOP3);
5159  } // decode_OPU_VOP3__V_MUL_F32
5160 
5161  GPUStaticInst*
5163  {
5164  return new Inst_VOP3__V_MUL_I32_I24(&iFmt->iFmt_VOP3);
5165  } // decode_OPU_VOP3__V_MUL_I32_I24
5166 
5167  GPUStaticInst*
5169  {
5170  return new Inst_VOP3__V_MUL_HI_I32_I24(&iFmt->iFmt_VOP3);
5171  } // decode_OPU_VOP3__V_MUL_HI_I32_I24
5172 
5173  GPUStaticInst*
5175  {
5176  return new Inst_VOP3__V_MUL_U32_U24(&iFmt->iFmt_VOP3);
5177  } // decode_OPU_VOP3__V_MUL_U32_U24
5178 
5179  GPUStaticInst*
5181  {
5182  return new Inst_VOP3__V_MUL_HI_U32_U24(&iFmt->iFmt_VOP3);
5183  } // decode_OPU_VOP3__V_MUL_HI_U32_U24
5184 
5185  GPUStaticInst*
5187  {
5188  return new Inst_VOP3__V_MIN_F32(&iFmt->iFmt_VOP3);
5189  } // decode_OPU_VOP3__V_MIN_F32
5190 
5191  GPUStaticInst*
5193  {
5194  return new Inst_VOP3__V_MAX_F32(&iFmt->iFmt_VOP3);
5195  } // decode_OPU_VOP3__V_MAX_F32
5196 
5197  GPUStaticInst*
5199  {
5200  return new Inst_VOP3__V_MIN_I32(&iFmt->iFmt_VOP3);
5201  } // decode_OPU_VOP3__V_MIN_I32
5202 
5203  GPUStaticInst*
5205  {
5206  return new Inst_VOP3__V_MAX_I32(&iFmt->iFmt_VOP3);
5207  } // decode_OPU_VOP3__V_MAX_I32
5208 
5209  GPUStaticInst*
5211  {
5212  return new Inst_VOP3__V_MIN_U32(&iFmt->iFmt_VOP3);
5213  } // decode_OPU_VOP3__V_MIN_U32
5214 
5215  GPUStaticInst*
5217  {
5218  return new Inst_VOP3__V_MAX_U32(&iFmt->iFmt_VOP3);
5219  } // decode_OPU_VOP3__V_MAX_U32
5220 
5221  GPUStaticInst*
5223  {
5224  return new Inst_VOP3__V_LSHRREV_B32(&iFmt->iFmt_VOP3);
5225  } // decode_OPU_VOP3__V_LSHRREV_B32
5226 
5227  GPUStaticInst*
5229  {
5230  return new Inst_VOP3__V_ASHRREV_I32(&iFmt->iFmt_VOP3);
5231  } // decode_OPU_VOP3__V_ASHRREV_I32
5232 
5233  GPUStaticInst*
5235  {
5236  return new Inst_VOP3__V_LSHLREV_B32(&iFmt->iFmt_VOP3);
5237  } // decode_OPU_VOP3__V_LSHLREV_B32
5238 
5239  GPUStaticInst*
5241  {
5242  return new Inst_VOP3__V_AND_B32(&iFmt->iFmt_VOP3);
5243  } // decode_OPU_VOP3__V_AND_B32
5244 
5245  GPUStaticInst*
5247  {
5248  return new Inst_VOP3__V_OR_B32(&iFmt->iFmt_VOP3);
5249  } // decode_OPU_VOP3__V_OR_B32
5250 
5251  GPUStaticInst*
5253  {
5254  return new Inst_VOP3__V_XOR_B32(&iFmt->iFmt_VOP3);
5255  } // decode_OPU_VOP3__V_XOR_B32
5256 
5257  GPUStaticInst*
5259  {
5260  return new Inst_VOP3__V_MAC_F32(&iFmt->iFmt_VOP3);
5261  } // decode_OPU_VOP3__V_MAC_F32
5262 
5263  GPUStaticInst*
5265  {
5266  return new Inst_VOP3__V_ADD_U32(&iFmt->iFmt_VOP3_SDST_ENC);
5267  } // decode_OPU_VOP3__V_ADD_U32
5268 
5269  GPUStaticInst*
5271  {
5272  return new Inst_VOP3__V_SUB_U32(&iFmt->iFmt_VOP3_SDST_ENC);
5273  } // decode_OPU_VOP3__V_SUB_U32
5274 
5275  GPUStaticInst*
5277  {
5278  return new Inst_VOP3__V_SUBREV_U32(&iFmt->iFmt_VOP3_SDST_ENC);
5279  } // decode_OPU_VOP3__V_SUBREV_U32
5280 
5281  GPUStaticInst*
5283  {
5284  return new Inst_VOP3__V_ADDC_U32(&iFmt->iFmt_VOP3_SDST_ENC);
5285  } // decode_OPU_VOP3__V_ADDC_U32
5286 
5287  GPUStaticInst*
5289  {
5290  return new Inst_VOP3__V_SUBB_U32(&iFmt->iFmt_VOP3_SDST_ENC);
5291  } // decode_OPU_VOP3__V_SUBB_U32
5292 
5293  GPUStaticInst*
5295  {
5296  return new Inst_VOP3__V_SUBBREV_U32(&iFmt->iFmt_VOP3_SDST_ENC);
5297  } // decode_OPU_VOP3__V_SUBBREV_U32
5298 
5299  GPUStaticInst*
5301  {
5302  return new Inst_VOP3__V_ADD_F16(&iFmt->iFmt_VOP3);
5303  } // decode_OPU_VOP3__V_ADD_F16
5304 
5305  GPUStaticInst*
5307  {
5308  return new Inst_VOP3__V_SUB_F16(&iFmt->iFmt_VOP3);
5309  } // decode_OPU_VOP3__V_SUB_F16
5310 
5311  GPUStaticInst*
5313  {
5314  return new Inst_VOP3__V_SUBREV_F16(&iFmt->iFmt_VOP3);
5315  } // decode_OPU_VOP3__V_SUBREV_F16
5316 
5317  GPUStaticInst*
5319  {
5320  return new Inst_VOP3__V_MUL_F16(&iFmt->iFmt_VOP3);
5321  } // decode_OPU_VOP3__V_MUL_F16
5322 
5323  GPUStaticInst*
5325  {
5326  return new Inst_VOP3__V_MAC_F16(&iFmt->iFmt_VOP3);
5327  } // decode_OPU_VOP3__V_MAC_F16
5328 
5329  GPUStaticInst*
5331  {
5332  return new Inst_VOP3__V_ADD_U16(&iFmt->iFmt_VOP3);
5333  } // decode_OPU_VOP3__V_ADD_U16
5334 
5335  GPUStaticInst*
5337  {
5338  return new Inst_VOP3__V_SUB_U16(&iFmt->iFmt_VOP3);
5339  } // decode_OPU_VOP3__V_SUB_U16
5340 
5341  GPUStaticInst*
5343  {
5344  return new Inst_VOP3__V_SUBREV_U16(&iFmt->iFmt_VOP3);
5345  } // decode_OPU_VOP3__V_SUBREV_U16
5346 
5347  GPUStaticInst*
5349  {
5350  return new Inst_VOP3__V_MUL_LO_U16(&iFmt->iFmt_VOP3);
5351  } // decode_OPU_VOP3__V_MUL_LO_U16
5352 
5353  GPUStaticInst*
5355  {
5356  return new Inst_VOP3__V_LSHLREV_B16(&iFmt->iFmt_VOP3);
5357  } // decode_OPU_VOP3__V_LSHLREV_B16
5358 
5359  GPUStaticInst*
5361  {
5362  return new Inst_VOP3__V_LSHRREV_B16(&iFmt->iFmt_VOP3);
5363  } // decode_OPU_VOP3__V_LSHRREV_B16
5364 
5365  GPUStaticInst*
5367  {
5368  return new Inst_VOP3__V_ASHRREV_I16(&iFmt->iFmt_VOP3);
5369  } // decode_OPU_VOP3__V_ASHRREV_I16
5370 
5371  GPUStaticInst*
5373  {
5374  return new Inst_VOP3__V_MAX_F16(&iFmt->iFmt_VOP3);
5375  } // decode_OPU_VOP3__V_MAX_F16
5376 
5377  GPUStaticInst*
5379  {
5380  return new Inst_VOP3__V_MIN_F16(&iFmt->iFmt_VOP3);
5381  } // decode_OPU_VOP3__V_MIN_F16
5382 
5383  GPUStaticInst*
5385  {
5386  return new Inst_VOP3__V_MAX_U16(&iFmt->iFmt_VOP3);
5387  } // decode_OPU_VOP3__V_MAX_U16
5388 
5389  GPUStaticInst*
5391  {
5392  return new Inst_VOP3__V_MAX_I16(&iFmt->iFmt_VOP3);
5393  } // decode_OPU_VOP3__V_MAX_I16
5394 
5395  GPUStaticInst*
5397  {
5398  return new Inst_VOP3__V_MIN_U16(&iFmt->iFmt_VOP3);
5399  } // decode_OPU_VOP3__V_MIN_U16
5400 
5401  GPUStaticInst*
5403  {
5404  return new Inst_VOP3__V_MIN_I16(&iFmt->iFmt_VOP3);
5405  } // decode_OPU_VOP3__V_MIN_I16
5406 
5407  GPUStaticInst*
5409  {
5410  return new Inst_VOP3__V_LDEXP_F16(&iFmt->iFmt_VOP3);
5411  } // decode_OPU_VOP3__V_LDEXP_F16
5412 
5413  GPUStaticInst*
5415  {
5416  return new Inst_VOP3__V_NOP(&iFmt->iFmt_VOP3);
5417  } // decode_OPU_VOP3__V_NOP
5418 
5419  GPUStaticInst*
5421  {
5422  return new Inst_VOP3__V_MOV_B32(&iFmt->iFmt_VOP3);
5423  } // decode_OPU_VOP3__V_MOV_B32
5424 
5425  GPUStaticInst*
5427  {
5428  return new Inst_VOP3__V_CVT_I32_F64(&iFmt->iFmt_VOP3);
5429  } // decode_OPU_VOP3__V_CVT_I32_F64
5430 
5431  GPUStaticInst*
5433  {
5434  return new Inst_VOP3__V_CVT_F64_I32(&iFmt->iFmt_VOP3);
5435  } // decode_OPU_VOP3__V_CVT_F64_I32
5436 
5437  GPUStaticInst*
5439  {
5440  return new Inst_VOP3__V_CVT_F32_I32(&iFmt->iFmt_VOP3);
5441  } // decode_OPU_VOP3__V_CVT_F32_I32
5442 
5443  GPUStaticInst*
5445  {
5446  return new Inst_VOP3__V_CVT_F32_U32(&iFmt->iFmt_VOP3);
5447  } // decode_OPU_VOP3__V_CVT_F32_U32
5448 
5449  GPUStaticInst*
5451  {
5452  return new Inst_VOP3__V_CVT_U32_F32(&iFmt->iFmt_VOP3);
5453  } // decode_OPU_VOP3__V_CVT_U32_F32
5454 
5455  GPUStaticInst*
5457  {
5458  return new Inst_VOP3__V_CVT_I32_F32(&iFmt->iFmt_VOP3);
5459  } // decode_OPU_VOP3__V_CVT_I32_F32
5460 
5461  GPUStaticInst*
5463  {
5464  return new Inst_VOP3__V_MOV_FED_B32(&iFmt->iFmt_VOP3);
5465  } // decode_OPU_VOP3__V_MOV_FED_B32
5466 
5467  GPUStaticInst*
5469  {
5470  return new Inst_VOP3__V_CVT_F16_F32(&iFmt->iFmt_VOP3);
5471  } // decode_OPU_VOP3__V_CVT_F16_F32
5472 
5473  GPUStaticInst*
5475  {
5476  return new Inst_VOP3__V_CVT_F32_F16(&iFmt->iFmt_VOP3);
5477  } // decode_OPU_VOP3__V_CVT_F32_F16
5478 
5479  GPUStaticInst*
5481  {
5482  return new Inst_VOP3__V_CVT_RPI_I32_F32(&iFmt->iFmt_VOP3);
5483  } // decode_OPU_VOP3__V_CVT_RPI_I32_F32
5484 
5485  GPUStaticInst*
5487  {
5488  return new Inst_VOP3__V_CVT_FLR_I32_F32(&iFmt->iFmt_VOP3);
5489  } // decode_OPU_VOP3__V_CVT_FLR_I32_F32
5490 
5491  GPUStaticInst*
5493  {
5494  return new Inst_VOP3__V_CVT_OFF_F32_I4(&iFmt->iFmt_VOP3);
5495  } // decode_OPU_VOP3__V_CVT_OFF_F32_I4
5496 
5497  GPUStaticInst*
5499  {
5500  return new Inst_VOP3__V_CVT_F32_F64(&iFmt->iFmt_VOP3);
5501  } // decode_OPU_VOP3__V_CVT_F32_F64
5502 
5503  GPUStaticInst*
5505  {
5506  return new Inst_VOP3__V_CVT_F64_F32(&iFmt->iFmt_VOP3);
5507  } // decode_OPU_VOP3__V_CVT_F64_F32
5508 
5509  GPUStaticInst*
5511  {
5512  return new Inst_VOP3__V_CVT_F32_UBYTE0(&iFmt->iFmt_VOP3);
5513  } // decode_OPU_VOP3__V_CVT_F32_UBYTE0
5514 
5515  GPUStaticInst*
5517  {
5518  return new Inst_VOP3__V_CVT_F32_UBYTE1(&iFmt->iFmt_VOP3);
5519  } // decode_OPU_VOP3__V_CVT_F32_UBYTE1
5520 
5521  GPUStaticInst*
5523  {
5524  return new Inst_VOP3__V_CVT_F32_UBYTE2(&iFmt->iFmt_VOP3);
5525  } // decode_OPU_VOP3__V_CVT_F32_UBYTE2
5526 
5527  GPUStaticInst*
5529  {
5530  return new Inst_VOP3__V_CVT_F32_UBYTE3(&iFmt->iFmt_VOP3);
5531  } // decode_OPU_VOP3__V_CVT_F32_UBYTE3
5532 
5533  GPUStaticInst*
5535  {
5536  return new Inst_VOP3__V_CVT_U32_F64(&iFmt->iFmt_VOP3);
5537  } // decode_OPU_VOP3__V_CVT_U32_F64
5538 
5539  GPUStaticInst*
5541  {
5542  return new Inst_VOP3__V_CVT_F64_U32(&iFmt->iFmt_VOP3);
5543  } // decode_OPU_VOP3__V_CVT_F64_U32
5544 
5545  GPUStaticInst*
5547  {
5548  return new Inst_VOP3__V_TRUNC_F64(&iFmt->iFmt_VOP3);
5549  } // decode_OPU_VOP3__V_TRUNC_F64
5550 
5551  GPUStaticInst*
5553  {
5554  return new Inst_VOP3__V_CEIL_F64(&iFmt->iFmt_VOP3);
5555  } // decode_OPU_VOP3__V_CEIL_F64
5556 
5557  GPUStaticInst*
5559  {
5560  return new Inst_VOP3__V_RNDNE_F64(&iFmt->iFmt_VOP3);
5561  } // decode_OPU_VOP3__V_RNDNE_F64
5562 
5563  GPUStaticInst*
5565  {
5566  return new Inst_VOP3__V_FLOOR_F64(&iFmt->iFmt_VOP3);
5567  } // decode_OPU_VOP3__V_FLOOR_F64
5568 
5569  GPUStaticInst*
5571  {
5572  return new Inst_VOP3__V_FRACT_F32(&iFmt->iFmt_VOP3);
5573  } // decode_OPU_VOP3__V_FRACT_F32
5574 
5575  GPUStaticInst*
5577  {
5578  return new Inst_VOP3__V_TRUNC_F32(&iFmt->iFmt_VOP3);
5579  } // decode_OPU_VOP3__V_TRUNC_F32
5580 
5581  GPUStaticInst*
5583  {
5584  return new Inst_VOP3__V_CEIL_F32(&iFmt->iFmt_VOP3);
5585  } // decode_OPU_VOP3__V_CEIL_F32
5586 
5587  GPUStaticInst*
5589  {
5590  return new Inst_VOP3__V_RNDNE_F32(&iFmt->iFmt_VOP3);
5591  } // decode_OPU_VOP3__V_RNDNE_F32
5592 
5593  GPUStaticInst*
5595  {
5596  return new Inst_VOP3__V_FLOOR_F32(&iFmt->iFmt_VOP3);
5597  } // decode_OPU_VOP3__V_FLOOR_F32
5598 
5599  GPUStaticInst*
5601  {
5602  return new Inst_VOP3__V_EXP_F32(&iFmt->iFmt_VOP3);
5603  } // decode_OPU_VOP3__V_EXP_F32
5604 
5605  GPUStaticInst*
5607  {
5608  return new Inst_VOP3__V_LOG_F32(&iFmt->iFmt_VOP3);
5609  } // decode_OPU_VOP3__V_LOG_F32
5610 
5611  GPUStaticInst*
5613  {
5614  return new Inst_VOP3__V_RCP_F32(&iFmt->iFmt_VOP3);
5615  } // decode_OPU_VOP3__V_RCP_F32
5616 
5617  GPUStaticInst*
5619  {
5620  return new Inst_VOP3__V_RCP_IFLAG_F32(&iFmt->iFmt_VOP3);
5621  } // decode_OPU_VOP3__V_RCP_IFLAG_F32
5622 
5623  GPUStaticInst*
5625  {
5626  return new Inst_VOP3__V_RSQ_F32(&iFmt->iFmt_VOP3);
5627  } // decode_OPU_VOP3__V_RSQ_F32
5628 
5629  GPUStaticInst*
5631  {
5632  return new Inst_VOP3__V_RCP_F64(&iFmt->iFmt_VOP3);
5633  } // decode_OPU_VOP3__V_RCP_F64
5634 
5635  GPUStaticInst*
5637  {
5638  return new Inst_VOP3__V_RSQ_F64(&iFmt->iFmt_VOP3);
5639  } // decode_OPU_VOP3__V_RSQ_F64
5640 
5641  GPUStaticInst*
5643  {
5644  return new Inst_VOP3__V_SQRT_F32(&iFmt->iFmt_VOP3);
5645  } // decode_OPU_VOP3__V_SQRT_F32
5646 
5647  GPUStaticInst*
5649  {
5650  return new Inst_VOP3__V_SQRT_F64(&iFmt->iFmt_VOP3);
5651  } // decode_OPU_VOP3__V_SQRT_F64
5652 
5653  GPUStaticInst*
5655  {
5656  return new Inst_VOP3__V_SIN_F32(&iFmt->iFmt_VOP3);
5657  } // decode_OPU_VOP3__V_SIN_F32
5658 
5659  GPUStaticInst*
5661  {
5662  return new Inst_VOP3__V_COS_F32(&iFmt->iFmt_VOP3);
5663  } // decode_OPU_VOP3__V_COS_F32
5664 
5665  GPUStaticInst*
5667  {
5668  return new Inst_VOP3__V_NOT_B32(&iFmt->iFmt_VOP3);
5669  } // decode_OPU_VOP3__V_NOT_B32
5670 
5671  GPUStaticInst*
5673  {
5674  return new Inst_VOP3__V_BFREV_B32(&iFmt->iFmt_VOP3);
5675  } // decode_OPU_VOP3__V_BFREV_B32
5676 
5677  GPUStaticInst*
5679  {
5680  return new Inst_VOP3__V_FFBH_U32(&iFmt->iFmt_VOP3);
5681  } // decode_OPU_VOP3__V_FFBH_U32
5682 
5683  GPUStaticInst*
5685  {
5686  return new Inst_VOP3__V_FFBL_B32(&iFmt->iFmt_VOP3);
5687  } // decode_OPU_VOP3__V_FFBL_B32
5688 
5689  GPUStaticInst*
5691  {
5692  return new Inst_VOP3__V_FFBH_I32(&iFmt->iFmt_VOP3);
5693  } // decode_OPU_VOP3__V_FFBH_I32
5694 
5695  GPUStaticInst*
5697  {
5698  return new Inst_VOP3__V_FREXP_EXP_I32_F64(&iFmt->iFmt_VOP3);
5699  } // decode_OPU_VOP3__V_FREXP_EXP_I32_F64
5700 
5701  GPUStaticInst*
5703  {
5704  return new Inst_VOP3__V_FREXP_MANT_F64(&iFmt->iFmt_VOP3);
5705  } // decode_OPU_VOP3__V_FREXP_MANT_F64
5706 
5707  GPUStaticInst*
5709  {
5710  return new Inst_VOP3__V_FRACT_F64(&iFmt->iFmt_VOP3);
5711  } // decode_OPU_VOP3__V_FRACT_F64
5712 
5713  GPUStaticInst*
5715  {
5716  return new Inst_VOP3__V_FREXP_EXP_I32_F32(&iFmt->iFmt_VOP3);
5717  } // decode_OPU_VOP3__V_FREXP_EXP_I32_F32
5718 
5719  GPUStaticInst*
5721  {
5722  return new Inst_VOP3__V_FREXP_MANT_F32(&iFmt->iFmt_VOP3);
5723  } // decode_OPU_VOP3__V_FREXP_MANT_F32
5724 
5725  GPUStaticInst*
5727  {
5728  return new Inst_VOP3__V_CLREXCP(&iFmt->iFmt_VOP3);
5729  } // decode_OPU_VOP3__V_CLREXCP
5730 
5731  GPUStaticInst*
5733  {
5734  return new Inst_VOP3__V_CVT_F16_U16(&iFmt->iFmt_VOP3);
5735  } // decode_OPU_VOP3__V_CVT_F16_U16
5736 
5737  GPUStaticInst*
5739  {
5740  return new Inst_VOP3__V_CVT_F16_I16(&iFmt->iFmt_VOP3);
5741  } // decode_OPU_VOP3__V_CVT_F16_I16
5742 
5743  GPUStaticInst*
5745  {
5746  return new Inst_VOP3__V_CVT_U16_F16(&iFmt->iFmt_VOP3);
5747  } // decode_OPU_VOP3__V_CVT_U16_F16
5748 
5749  GPUStaticInst*
5751  {
5752  return new Inst_VOP3__V_CVT_I16_F16(&iFmt->iFmt_VOP3);
5753  } // decode_OPU_VOP3__V_CVT_I16_F16
5754 
5755  GPUStaticInst*
5757  {
5758  return new Inst_VOP3__V_RCP_F16(&iFmt->iFmt_VOP3);
5759  } // decode_OPU_VOP3__V_RCP_F16
5760 
5761  GPUStaticInst*
5763  {
5764  return new Inst_VOP3__V_SQRT_F16(&iFmt->iFmt_VOP3);
5765  } // decode_OPU_VOP3__V_SQRT_F16
5766 
5767  GPUStaticInst*
5769  {
5770  return new Inst_VOP3__V_RSQ_F16(&iFmt->iFmt_VOP3);
5771  } // decode_OPU_VOP3__V_RSQ_F16
5772 
5773  GPUStaticInst*
5775  {
5776  return new Inst_VOP3__V_LOG_F16(&iFmt->iFmt_VOP3);
5777  } // decode_OPU_VOP3__V_LOG_F16
5778 
5779  GPUStaticInst*
5781  {
5782  return new Inst_VOP3__V_EXP_F16(&iFmt->iFmt_VOP3);
5783  } // decode_OPU_VOP3__V_EXP_F16
5784 
5785  GPUStaticInst*
5787  {
5788  return new Inst_VOP3__V_FREXP_MANT_F16(&iFmt->iFmt_VOP3);
5789  } // decode_OPU_VOP3__V_FREXP_MANT_F16
5790 
5791  GPUStaticInst*
5793  {
5794  return new Inst_VOP3__V_FREXP_EXP_I16_F16(&iFmt->iFmt_VOP3);
5795  } // decode_OPU_VOP3__V_FREXP_EXP_I16_F16
5796 
5797  GPUStaticInst*
5799  {
5800  return new Inst_VOP3__V_FLOOR_F16(&iFmt->iFmt_VOP3);
5801  } // decode_OPU_VOP3__V_FLOOR_F16
5802 
5803  GPUStaticInst*
5805  {
5806  return new Inst_VOP3__V_CEIL_F16(&iFmt->iFmt_VOP3);
5807  } // decode_OPU_VOP3__V_CEIL_F16
5808 
5809  GPUStaticInst*
5811  {
5812  return new Inst_VOP3__V_TRUNC_F16(&iFmt->iFmt_VOP3);
5813  } // decode_OPU_VOP3__V_TRUNC_F16
5814 
5815  GPUStaticInst*
5817  {
5818  return new Inst_VOP3__V_RNDNE_F16(&iFmt->iFmt_VOP3);
5819  } // decode_OPU_VOP3__V_RNDNE_F16
5820 
5821  GPUStaticInst*
5823  {
5824  return new Inst_VOP3__V_FRACT_F16(&iFmt->iFmt_VOP3);
5825  } // decode_OPU_VOP3__V_FRACT_F16
5826 
5827  GPUStaticInst*
5829  {
5830  return new Inst_VOP3__V_SIN_F16(&iFmt->iFmt_VOP3);
5831  } // decode_OPU_VOP3__V_SIN_F16
5832 
5833  GPUStaticInst*
5835  {
5836  return new Inst_VOP3__V_COS_F16(&iFmt->iFmt_VOP3);
5837  } // decode_OPU_VOP3__V_COS_F16
5838 
5839  GPUStaticInst*
5841  {
5842  return new Inst_VOP3__V_EXP_LEGACY_F32(&iFmt->iFmt_VOP3);
5843  } // decode_OPU_VOP3__V_EXP_LEGACY_F32
5844 
5845  GPUStaticInst*
5847  {
5848  return new Inst_VOP3__V_LOG_LEGACY_F32(&iFmt->iFmt_VOP3);
5849  } // decode_OPU_VOP3__V_LOG_LEGACY_F32
5850 
5851  GPUStaticInst*
5853  {
5854  return new Inst_VOP3__V_MAD_LEGACY_F32(&iFmt->iFmt_VOP3);
5855  } // decode_OPU_VOP3__V_MAD_LEGACY_F32
5856 
5857  GPUStaticInst*
5859  {
5860  return new Inst_VOP3__V_MAD_F32(&iFmt->iFmt_VOP3);
5861  } // decode_OPU_VOP3__V_MAD_F32
5862 
5863  GPUStaticInst*
5865  {
5866  return new Inst_VOP3__V_MAD_I32_I24(&iFmt->iFmt_VOP3);
5867  } // decode_OPU_VOP3__V_MAD_I32_I24
5868 
5869  GPUStaticInst*
5871  {
5872  return new Inst_VOP3__V_MAD_U32_U24(&iFmt->iFmt_VOP3);
5873  } // decode_OPU_VOP3__V_MAD_U32_U24
5874 
5875  GPUStaticInst*
5877  {
5878  return new Inst_VOP3__V_CUBEID_F32(&iFmt->iFmt_VOP3);
5879  } // decode_OPU_VOP3__V_CUBEID_F32
5880 
5881  GPUStaticInst*
5883  {
5884  return new Inst_VOP3__V_CUBESC_F32(&iFmt->iFmt_VOP3);
5885  } // decode_OPU_VOP3__V_CUBESC_F32
5886 
5887  GPUStaticInst*
5889  {
5890  return new Inst_VOP3__V_CUBETC_F32(&iFmt->iFmt_VOP3);
5891  } // decode_OPU_VOP3__V_CUBETC_F32
5892 
5893  GPUStaticInst*
5895  {
5896  return new Inst_VOP3__V_CUBEMA_F32(&iFmt->iFmt_VOP3);
5897  } // decode_OPU_VOP3__V_CUBEMA_F32
5898 
5899  GPUStaticInst*
5901  {
5902  return new Inst_VOP3__V_BFE_U32(&iFmt->iFmt_VOP3);
5903  } // decode_OPU_VOP3__V_BFE_U32
5904 
5905  GPUStaticInst*
5907  {
5908  return new Inst_VOP3__V_BFE_I32(&iFmt->iFmt_VOP3);
5909  } // decode_OPU_VOP3__V_BFE_I32
5910 
5911  GPUStaticInst*
5913  {
5914  return new Inst_VOP3__V_BFI_B32(&iFmt->iFmt_VOP3);
5915  } // decode_OPU_VOP3__V_BFI_B32
5916 
5917  GPUStaticInst*
5919  {
5920  return new Inst_VOP3__V_FMA_F32(&iFmt->iFmt_VOP3);
5921  } // decode_OPU_VOP3__V_FMA_F32
5922 
5923  GPUStaticInst*
5925  {
5926  return new Inst_VOP3__V_FMA_F64(&iFmt->iFmt_VOP3);
5927  } // decode_OPU_VOP3__V_FMA_F64
5928 
5929  GPUStaticInst*
5931  {
5932  return new Inst_VOP3__V_LERP_U8(&iFmt->iFmt_VOP3);
5933  } // decode_OPU_VOP3__V_LERP_U8
5934 
5935  GPUStaticInst*
5937  {
5938  return new Inst_VOP3__V_ALIGNBIT_B32(&iFmt->iFmt_VOP3);
5939  } // decode_OPU_VOP3__V_ALIGNBIT_B32
5940 
5941  GPUStaticInst*
5943  {
5944  return new Inst_VOP3__V_ALIGNBYTE_B32(&iFmt->iFmt_VOP3);
5945  } // decode_OPU_VOP3__V_ALIGNBYTE_B32
5946 
5947  GPUStaticInst*
5949  {
5950  return new Inst_VOP3__V_MIN3_F32(&iFmt->iFmt_VOP3);
5951  } // decode_OPU_VOP3__V_MIN3_F32
5952 
5953  GPUStaticInst*
5955  {
5956  return new Inst_VOP3__V_MIN3_I32(&iFmt->iFmt_VOP3);
5957  } // decode_OPU_VOP3__V_MIN3_I32
5958 
5959  GPUStaticInst*
5961  {
5962  return new Inst_VOP3__V_MIN3_U32(&iFmt->iFmt_VOP3);
5963  } // decode_OPU_VOP3__V_MIN3_U32
5964 
5965  GPUStaticInst*
5967  {
5968  return new Inst_VOP3__V_MAX3_F32(&iFmt->iFmt_VOP3);
5969  } // decode_OPU_VOP3__V_MAX3_F32
5970 
5971  GPUStaticInst*
5973  {
5974  return new Inst_VOP3__V_MAX3_I32(&iFmt->iFmt_VOP3);
5975  } // decode_OPU_VOP3__V_MAX3_I32
5976 
5977  GPUStaticInst*
5979  {
5980  return new Inst_VOP3__V_MAX3_U32(&iFmt->iFmt_VOP3);
5981  } // decode_OPU_VOP3__V_MAX3_U32
5982 
5983  GPUStaticInst*
5985  {
5986  return new Inst_VOP3__V_MED3_F32(&iFmt->iFmt_VOP3);
5987  } // decode_OPU_VOP3__V_MED3_F32
5988 
5989  GPUStaticInst*
5991  {
5992  return new Inst_VOP3__V_MED3_I32(&iFmt->iFmt_VOP3);
5993  } // decode_OPU_VOP3__V_MED3_I32
5994 
5995  GPUStaticInst*
5997  {
5998  return new Inst_VOP3__V_MED3_U32(&iFmt->iFmt_VOP3);
5999  } // decode_OPU_VOP3__V_MED3_U32
6000 
6001  GPUStaticInst*
6003  {
6004  return new Inst_VOP3__V_SAD_U8(&iFmt->iFmt_VOP3);
6005  } // decode_OPU_VOP3__V_SAD_U8
6006 
6007  GPUStaticInst*
6009  {
6010  return new Inst_VOP3__V_SAD_HI_U8(&iFmt->iFmt_VOP3);
6011  } // decode_OPU_VOP3__V_SAD_HI_U8
6012 
6013  GPUStaticInst*
6015  {
6016  return new Inst_VOP3__V_SAD_U16(&iFmt->iFmt_VOP3);
6017  } // decode_OPU_VOP3__V_SAD_U16
6018 
6019  GPUStaticInst*
6021  {
6022  return new Inst_VOP3__V_SAD_U32(&iFmt->iFmt_VOP3);
6023  } // decode_OPU_VOP3__V_SAD_U32
6024 
6025  GPUStaticInst*
6027  {
6028  return new Inst_VOP3__V_CVT_PK_U8_F32(&iFmt->iFmt_VOP3);
6029  } // decode_OPU_VOP3__V_CVT_PK_U8_F32
6030 
6031  GPUStaticInst*
6033  {
6034  return new Inst_VOP3__V_DIV_FIXUP_F32(&iFmt->iFmt_VOP3);
6035  } // decode_OPU_VOP3__V_DIV_FIXUP_F32
6036 
6037  GPUStaticInst*
6039  {
6040  return new Inst_VOP3__V_DIV_FIXUP_F64(&iFmt->iFmt_VOP3);
6041  } // decode_OPU_VOP3__V_DIV_FIXUP_F64
6042 
6043  GPUStaticInst*
6045  {
6047  } // decode_OPU_VOP3__V_DIV_SCALE_F32
6048 
6049  GPUStaticInst*
6051  {
6053  } // decode_OPU_VOP3__V_DIV_SCALE_F64
6054 
6055  GPUStaticInst*
6057  {
6058  return new Inst_VOP3__V_DIV_FMAS_F32(&iFmt->iFmt_VOP3);
6059  } // decode_OPU_VOP3__V_DIV_FMAS_F32
6060 
6061  GPUStaticInst*
6063  {
6064  return new Inst_VOP3__V_DIV_FMAS_F64(&iFmt->iFmt_VOP3);
6065  } // decode_OPU_VOP3__V_DIV_FMAS_F64
6066 
6067  GPUStaticInst*
6069  {
6070  return new Inst_VOP3__V_MSAD_U8(&iFmt->iFmt_VOP3);
6071  } // decode_OPU_VOP3__V_MSAD_U8
6072 
6073  GPUStaticInst*
6075  {
6076  return new Inst_VOP3__V_QSAD_PK_U16_U8(&iFmt->iFmt_VOP3);
6077  } // decode_OPU_VOP3__V_QSAD_PK_U16_U8
6078 
6079  GPUStaticInst*
6081  {
6082  return new Inst_VOP3__V_MQSAD_PK_U16_U8(&iFmt->iFmt_VOP3);
6083  } // decode_OPU_VOP3__V_MQSAD_PK_U16_U8
6084 
6085  GPUStaticInst*
6087  {
6088  return new Inst_VOP3__V_MQSAD_U32_U8(&iFmt->iFmt_VOP3);
6089  } // decode_OPU_VOP3__V_MQSAD_U32_U8
6090 
6091  GPUStaticInst*
6093  {
6094  return new Inst_VOP3__V_MAD_U64_U32(&iFmt->iFmt_VOP3_SDST_ENC);
6095  } // decode_OPU_VOP3__V_MAD_U64_U32
6096 
6097  GPUStaticInst*
6099  {
6100  return new Inst_VOP3__V_MAD_I64_I32(&iFmt->iFmt_VOP3_SDST_ENC);
6101  } // decode_OPU_VOP3__V_MAD_I64_I32
6102 
6103  GPUStaticInst*
6105  {
6106  return new Inst_VOP3__V_MAD_F16(&iFmt->iFmt_VOP3);
6107  } // decode_OPU_VOP3__V_MAD_F16
6108 
6109  GPUStaticInst*
6111  {
6112  return new Inst_VOP3__V_MAD_U16(&iFmt->iFmt_VOP3);
6113  } // decode_OPU_VOP3__V_MAD_U16
6114 
6115  GPUStaticInst*
6117  {
6118  return new Inst_VOP3__V_MAD_I16(&iFmt->iFmt_VOP3);
6119  } // decode_OPU_VOP3__V_MAD_I16
6120 
6121  GPUStaticInst*
6123  {
6124  return new Inst_VOP3__V_PERM_B32(&iFmt->iFmt_VOP3);
6125  } // decode_OPU_VOP3__V_PERM_B32
6126 
6127  GPUStaticInst*
6129  {
6130  return new Inst_VOP3__V_FMA_F16(&iFmt->iFmt_VOP3);
6131  } // decode_OPU_VOP3__V_FMA_F16
6132 
6133  GPUStaticInst*
6135  {
6136  return new Inst_VOP3__V_DIV_FIXUP_F16(&iFmt->iFmt_VOP3);
6137  } // decode_OPU_VOP3__V_DIV_FIXUP_F16
6138 
6139  GPUStaticInst*
6141  {
6142  return new Inst_VOP3__V_CVT_PKACCUM_U8_F32(&iFmt->iFmt_VOP3);
6143  } // decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32
6144 
6145  GPUStaticInst*
6147  {
6148  return new Inst_VOP3__V_INTERP_P1_F32(&iFmt->iFmt_VOP3);
6149  } // decode_OPU_VOP3__V_INTERP_P1_F32
6150 
6151  GPUStaticInst*
6153  {
6154  return new Inst_VOP3__V_INTERP_P2_F32(&iFmt->iFmt_VOP3);
6155  } // decode_OPU_VOP3__V_INTERP_P2_F32
6156 
6157  GPUStaticInst*
6159  {
6160  return new Inst_VOP3__V_INTERP_MOV_F32(&iFmt->iFmt_VOP3);
6161  } // decode_OPU_VOP3__V_INTERP_MOV_F32
6162 
6163  GPUStaticInst*
6165  {
6166  return new Inst_VOP3__V_INTERP_P1LL_F16(&iFmt->iFmt_VOP3);
6167  } // decode_OPU_VOP3__V_INTERP_P1LL_F16
6168 
6169  GPUStaticInst*
6171  {
6172  return new Inst_VOP3__V_INTERP_P1LV_F16(&iFmt->iFmt_VOP3);
6173  } // decode_OPU_VOP3__V_INTERP_P1LV_F16
6174 
6175  GPUStaticInst*
6177  {
6178  return new Inst_VOP3__V_INTERP_P2_F16(&iFmt->iFmt_VOP3);
6179  } // decode_OPU_VOP3__V_INTERP_P2_F16
6180 
6181  GPUStaticInst*
6183  {
6184  return new Inst_VOP3__V_ADD_F64(&iFmt->iFmt_VOP3);
6185  } // decode_OPU_VOP3__V_ADD_F64
6186 
6187  GPUStaticInst*
6189  {
6190  return new Inst_VOP3__V_MUL_F64(&iFmt->iFmt_VOP3);
6191  } // decode_OPU_VOP3__V_MUL_F64
6192 
6193  GPUStaticInst*
6195  {
6196  return new Inst_VOP3__V_MIN_F64(&iFmt->iFmt_VOP3);
6197  } // decode_OPU_VOP3__V_MIN_F64
6198 
6199  GPUStaticInst*
6201  {
6202  return new Inst_VOP3__V_MAX_F64(&iFmt->iFmt_VOP3);
6203  } // decode_OPU_VOP3__V_MAX_F64
6204 
6205  GPUStaticInst*
6207  {
6208  return new Inst_VOP3__V_LDEXP_F64(&iFmt->iFmt_VOP3);
6209  } // decode_OPU_VOP3__V_LDEXP_F64
6210 
6211  GPUStaticInst*
6213  {
6214  return new Inst_VOP3__V_MUL_LO_U32(&iFmt->iFmt_VOP3);
6215  } // decode_OPU_VOP3__V_MUL_LO_U32
6216 
6217  GPUStaticInst*
6219  {
6220  return new Inst_VOP3__V_MUL_HI_U32(&iFmt->iFmt_VOP3);
6221  } // decode_OPU_VOP3__V_MUL_HI_U32
6222 
6223  GPUStaticInst*
6225  {
6226  return new Inst_VOP3__V_MUL_HI_I32(&iFmt->iFmt_VOP3);
6227  } // decode_OPU_VOP3__V_MUL_HI_I32
6228 
6229  GPUStaticInst*
6231  {
6232  return new Inst_VOP3__V_LDEXP_F32(&iFmt->iFmt_VOP3);
6233  } // decode_OPU_VOP3__V_LDEXP_F32
6234 
6235  GPUStaticInst*
6237  {
6238  return new Inst_VOP3__V_READLANE_B32(&iFmt->iFmt_VOP3);
6239  } // decode_OPU_VOP3__V_READLANE_B32
6240 
6241  GPUStaticInst*
6243  {
6244  return new Inst_VOP3__V_WRITELANE_B32(&iFmt->iFmt_VOP3);
6245  } // decode_OPU_VOP3__V_WRITELANE_B32
6246 
6247  GPUStaticInst*
6249  {
6250  return new Inst_VOP3__V_BCNT_U32_B32(&iFmt->iFmt_VOP3);
6251  } // decode_OPU_VOP3__V_BCNT_U32_B32
6252 
6253  GPUStaticInst*
6255  {
6256  return new Inst_VOP3__V_MBCNT_LO_U32_B32(&iFmt->iFmt_VOP3);
6257  } // decode_OPU_VOP3__V_MBCNT_LO_U32_B32
6258 
6259  GPUStaticInst*
6261  {
6262  return new Inst_VOP3__V_MBCNT_HI_U32_B32(&iFmt->iFmt_VOP3);
6263  } // decode_OPU_VOP3__V_MBCNT_HI_U32_B32
6264 
6265  GPUStaticInst*
6267  {
6268  return new Inst_VOP3__V_LSHLREV_B64(&iFmt->iFmt_VOP3);
6269  } // decode_OPU_VOP3__V_LSHLREV_B64
6270 
6271  GPUStaticInst*
6273  {
6274  return new Inst_VOP3__V_LSHRREV_B64(&iFmt->iFmt_VOP3);
6275  } // decode_OPU_VOP3__V_LSHRREV_B64
6276 
6277  GPUStaticInst*
6279  {
6280  return new Inst_VOP3__V_ASHRREV_I64(&iFmt->iFmt_VOP3);
6281  } // decode_OPU_VOP3__V_ASHRREV_I64
6282 
6283  GPUStaticInst*
6285  {
6286  return new Inst_VOP3__V_TRIG_PREOP_F64(&iFmt->iFmt_VOP3);
6287  } // decode_OPU_VOP3__V_TRIG_PREOP_F64
6288 
6289  GPUStaticInst*
6291  {
6292  return new Inst_VOP3__V_BFM_B32(&iFmt->iFmt_VOP3);
6293  } // decode_OPU_VOP3__V_BFM_B32
6294 
6295  GPUStaticInst*
6297  {
6298  return new Inst_VOP3__V_CVT_PKNORM_I16_F32(&iFmt->iFmt_VOP3);
6299  } // decode_OPU_VOP3__V_CVT_PKNORM_I16_F32
6300 
6301  GPUStaticInst*
6303  {
6304  return new Inst_VOP3__V_CVT_PKNORM_U16_F32(&iFmt->iFmt_VOP3);
6305  } // decode_OPU_VOP3__V_CVT_PKNORM_U16_F32
6306 
6307  GPUStaticInst*
6309  {
6310  return new Inst_VOP3__V_CVT_PKRTZ_F16_F32(&iFmt->iFmt_VOP3);
6311  } // decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32
6312 
6313  GPUStaticInst*
6315  {
6316  return new Inst_VOP3__V_CVT_PK_U16_U32(&iFmt->iFmt_VOP3);
6317  } // decode_OPU_VOP3__V_CVT_PK_U16_U32
6318 
6319  GPUStaticInst*
6321  {
6322  return new Inst_VOP3__V_CVT_PK_I16_I32(&iFmt->iFmt_VOP3);
6323  } // decode_OPU_VOP3__V_CVT_PK_I16_I32
6324 
6325  GPUStaticInst*
6327  {
6328  return new Inst_DS__DS_ADD_U32(&iFmt->iFmt_DS);
6329  } // decode_OP_DS__DS_ADD_U32
6330 
6331  GPUStaticInst*
6333  {
6334  return new Inst_DS__DS_SUB_U32(&iFmt->iFmt_DS);
6335  } // decode_OP_DS__DS_SUB_U32
6336 
6337  GPUStaticInst*
6339  {
6340  return new Inst_DS__DS_RSUB_U32(&iFmt->iFmt_DS);
6341  } // decode_OP_DS__DS_RSUB_U32
6342 
6343  GPUStaticInst*
6345  {
6346  return new Inst_DS__DS_INC_U32(&iFmt->iFmt_DS);
6347  } // decode_OP_DS__DS_INC_U32
6348 
6349  GPUStaticInst*
6351  {
6352  return new Inst_DS__DS_DEC_U32(&iFmt->iFmt_DS);
6353  } // decode_OP_DS__DS_DEC_U32
6354 
6355  GPUStaticInst*
6357  {
6358  return new Inst_DS__DS_MIN_I32(&iFmt->iFmt_DS);
6359  } // decode_OP_DS__DS_MIN_I32
6360 
6361  GPUStaticInst*
6363  {
6364  return new Inst_DS__DS_MAX_I32(&iFmt->iFmt_DS);
6365  } // decode_OP_DS__DS_MAX_I32
6366 
6367  GPUStaticInst*
6369  {
6370  return new Inst_DS__DS_MIN_U32(&iFmt->iFmt_DS);
6371  } // decode_OP_DS__DS_MIN_U32
6372 
6373  GPUStaticInst*
6375  {
6376  return new Inst_DS__DS_MAX_U32(&iFmt->iFmt_DS);
6377  } // decode_OP_DS__DS_MAX_U32
6378 
6379  GPUStaticInst*
6381  {
6382  return new Inst_DS__DS_AND_B32(&iFmt->iFmt_DS);
6383  } // decode_OP_DS__DS_AND_B32
6384 
6385  GPUStaticInst*
6387  {
6388  return new Inst_DS__DS_OR_B32(&iFmt->iFmt_DS);
6389  } // decode_OP_DS__DS_OR_B32
6390 
6391  GPUStaticInst*
6393  {
6394  return new Inst_DS__DS_XOR_B32(&iFmt->iFmt_DS);
6395  } // decode_OP_DS__DS_XOR_B32
6396 
6397  GPUStaticInst*
6399  {
6400  return new Inst_DS__DS_MSKOR_B32(&iFmt->iFmt_DS);
6401  } // decode_OP_DS__DS_MSKOR_B32
6402 
6403  GPUStaticInst*
6405  {
6406  return new Inst_DS__DS_WRITE_B32(&iFmt->iFmt_DS);
6407  } // decode_OP_DS__DS_WRITE_B32
6408 
6409  GPUStaticInst*
6411  {
6412  return new Inst_DS__DS_WRITE2_B32(&iFmt->iFmt_DS);
6413  } // decode_OP_DS__DS_WRITE2_B32
6414 
6415  GPUStaticInst*
6417  {
6418  return new Inst_DS__DS_WRITE2ST64_B32(&iFmt->iFmt_DS);
6419  } // decode_OP_DS__DS_WRITE2ST64_B32
6420 
6421  GPUStaticInst*
6423  {
6424  return new Inst_DS__DS_CMPST_B32(&iFmt->iFmt_DS);
6425  } // decode_OP_DS__DS_CMPST_B32
6426 
6427  GPUStaticInst*
6429  {
6430  return new Inst_DS__DS_CMPST_F32(&iFmt->iFmt_DS);
6431  } // decode_OP_DS__DS_CMPST_F32
6432 
6433  GPUStaticInst*
6435  {
6436  return new Inst_DS__DS_MIN_F32(&iFmt->iFmt_DS);
6437  } // decode_OP_DS__DS_MIN_F32
6438 
6439  GPUStaticInst*
6441  {
6442  return new Inst_DS__DS_MAX_F32(&iFmt->iFmt_DS);
6443  } // decode_OP_DS__DS_MAX_F32
6444 
6445  GPUStaticInst*
6447  {
6448  return new Inst_DS__DS_NOP(&iFmt->iFmt_DS);
6449  } // decode_OP_DS__DS_NOP
6450 
6451  GPUStaticInst*
6453  {
6454  return new Inst_DS__DS_ADD_F32(&iFmt->iFmt_DS);
6455  } // decode_OP_DS__DS_ADD_F32
6456 
6457  GPUStaticInst*
6459  {
6460  return new Inst_DS__DS_WRITE_B8(&iFmt->iFmt_DS);
6461  } // decode_OP_DS__DS_WRITE_B8
6462 
6463  GPUStaticInst*
6465  {
6466  return new Inst_DS__DS_WRITE_B16(&iFmt->iFmt_DS);
6467  } // decode_OP_DS__DS_WRITE_B16
6468 
6469  GPUStaticInst*
6471  {
6472  return new Inst_DS__DS_ADD_RTN_U32(&iFmt->iFmt_DS);
6473  } // decode_OP_DS__DS_ADD_RTN_U32
6474 
6475  GPUStaticInst*
6477  {
6478  return new Inst_DS__DS_SUB_RTN_U32(&iFmt->iFmt_DS);
6479  } // decode_OP_DS__DS_SUB_RTN_U32
6480 
6481  GPUStaticInst*
6483  {
6484  return new Inst_DS__DS_RSUB_RTN_U32(&iFmt->iFmt_DS);
6485  } // decode_OP_DS__DS_RSUB_RTN_U32
6486 
6487  GPUStaticInst*
6489  {
6490  return new Inst_DS__DS_INC_RTN_U32(&iFmt->iFmt_DS);
6491  } // decode_OP_DS__DS_INC_RTN_U32
6492 
6493  GPUStaticInst*
6495  {
6496  return new Inst_DS__DS_DEC_RTN_U32(&iFmt->iFmt_DS);
6497  } // decode_OP_DS__DS_DEC_RTN_U32
6498 
6499  GPUStaticInst*
6501  {
6502  return new Inst_DS__DS_MIN_RTN_I32(&iFmt->iFmt_DS);
6503  } // decode_OP_DS__DS_MIN_RTN_I32
6504 
6505  GPUStaticInst*
6507  {
6508  return new Inst_DS__DS_MAX_RTN_I32(&iFmt->iFmt_DS);
6509  } // decode_OP_DS__DS_MAX_RTN_I32
6510 
6511  GPUStaticInst*
6513  {
6514  return new Inst_DS__DS_MIN_RTN_U32(&iFmt->iFmt_DS);
6515  } // decode_OP_DS__DS_MIN_RTN_U32
6516 
6517  GPUStaticInst*
6519  {
6520  return new Inst_DS__DS_MAX_RTN_U32(&iFmt->iFmt_DS);
6521  } // decode_OP_DS__DS_MAX_RTN_U32
6522 
6523  GPUStaticInst*
6525  {
6526  return new Inst_DS__DS_AND_RTN_B32(&iFmt->iFmt_DS);
6527  } // decode_OP_DS__DS_AND_RTN_B32
6528 
6529  GPUStaticInst*
6531  {
6532  return new Inst_DS__DS_OR_RTN_B32(&iFmt->iFmt_DS);
6533  } // decode_OP_DS__DS_OR_RTN_B32
6534 
6535  GPUStaticInst*
6537  {
6538  return new Inst_DS__DS_XOR_RTN_B32(&iFmt->iFmt_DS);
6539  } // decode_OP_DS__DS_XOR_RTN_B32
6540 
6541  GPUStaticInst*
6543  {
6544  return new Inst_DS__DS_MSKOR_RTN_B32(&iFmt->iFmt_DS);
6545  } // decode_OP_DS__DS_MSKOR_RTN_B32
6546 
6547  GPUStaticInst*
6549  {
6550  return new Inst_DS__DS_WRXCHG_RTN_B32(&iFmt->iFmt_DS);
6551  } // decode_OP_DS__DS_WRXCHG_RTN_B32
6552 
6553  GPUStaticInst*
6555  {
6556  return new Inst_DS__DS_WRXCHG2_RTN_B32(&iFmt->iFmt_DS);
6557  } // decode_OP_DS__DS_WRXCHG2_RTN_B32
6558 
6559  GPUStaticInst*
6561  {
6562  return new Inst_DS__DS_WRXCHG2ST64_RTN_B32(&iFmt->iFmt_DS);
6563  } // decode_OP_DS__DS_WRXCHG2ST64_RTN_B32
6564 
6565  GPUStaticInst*
6567  {
6568  return new Inst_DS__DS_CMPST_RTN_B32(&iFmt->iFmt_DS);
6569  } // decode_OP_DS__DS_CMPST_RTN_B32
6570 
6571  GPUStaticInst*
6573  {
6574  return new Inst_DS__DS_CMPST_RTN_F32(&iFmt->iFmt_DS);
6575  } // decode_OP_DS__DS_CMPST_RTN_F32
6576 
6577  GPUStaticInst*
6579  {
6580  return new Inst_DS__DS_MIN_RTN_F32(&iFmt->iFmt_DS);
6581  } // decode_OP_DS__DS_MIN_RTN_F32
6582 
6583  GPUStaticInst*
6585  {
6586  return new Inst_DS__DS_MAX_RTN_F32(&iFmt->iFmt_DS);
6587  } // decode_OP_DS__DS_MAX_RTN_F32
6588 
6589  GPUStaticInst*
6591  {
6592  return new Inst_DS__DS_WRAP_RTN_B32(&iFmt->iFmt_DS);
6593  } // decode_OP_DS__DS_WRAP_RTN_B32
6594 
6595  GPUStaticInst*
6597  {
6598  return new Inst_DS__DS_ADD_RTN_F32(&iFmt->iFmt_DS);
6599  } // decode_OP_DS__DS_ADD_RTN_F32
6600 
6601  GPUStaticInst*
6603  {
6604  return new Inst_DS__DS_READ_B32(&iFmt->iFmt_DS);
6605  } // decode_OP_DS__DS_READ_B32
6606 
6607  GPUStaticInst*
6609  {
6610  return new Inst_DS__DS_READ2_B32(&iFmt->iFmt_DS);
6611  } // decode_OP_DS__DS_READ2_B32
6612 
6613  GPUStaticInst*
6615  {
6616  return new Inst_DS__DS_READ2ST64_B32(&iFmt->iFmt_DS);
6617  } // decode_OP_DS__DS_READ2ST64_B32
6618 
6619  GPUStaticInst*
6621  {
6622  return new Inst_DS__DS_READ_I8(&iFmt->iFmt_DS);
6623  } // decode_OP_DS__DS_READ_I8
6624 
6625  GPUStaticInst*
6627  {
6628  return new Inst_DS__DS_READ_U8(&iFmt->iFmt_DS);
6629  } // decode_OP_DS__DS_READ_U8
6630 
6631  GPUStaticInst*
6633  {
6634  return new Inst_DS__DS_READ_I16(&iFmt->iFmt_DS);
6635  } // decode_OP_DS__DS_READ_I16
6636 
6637  GPUStaticInst*
6639  {
6640  return new Inst_DS__DS_READ_U16(&iFmt->iFmt_DS);
6641  } // decode_OP_DS__DS_READ_U16
6642 
6643  GPUStaticInst*
6645  {
6646  return new Inst_DS__DS_SWIZZLE_B32(&iFmt->iFmt_DS);
6647  } // decode_OP_DS__DS_SWIZZLE_B32
6648 
6649  GPUStaticInst*
6651  {
6652  return new Inst_DS__DS_PERMUTE_B32(&iFmt->iFmt_DS);
6653  } // decode_OP_DS__DS_PERMUTE_B32
6654 
6655  GPUStaticInst*
6657  {
6658  return new Inst_DS__DS_BPERMUTE_B32(&iFmt->iFmt_DS);
6659  } // decode_OP_DS__DS_BPERMUTE_B32
6660 
6661  GPUStaticInst*
6663  {
6664  return new Inst_DS__DS_ADD_U64(&iFmt->iFmt_DS);
6665  } // decode_OP_DS__DS_ADD_U64
6666 
6667  GPUStaticInst*
6669  {
6670  return new Inst_DS__DS_SUB_U64(&iFmt->iFmt_DS);
6671  } // decode_OP_DS__DS_SUB_U64
6672 
6673  GPUStaticInst*
6675  {
6676  return new Inst_DS__DS_RSUB_U64(&iFmt->iFmt_DS);
6677  } // decode_OP_DS__DS_RSUB_U64
6678 
6679  GPUStaticInst*
6681  {
6682  return new Inst_DS__DS_INC_U64(&iFmt->iFmt_DS);
6683  } // decode_OP_DS__DS_INC_U64
6684 
6685  GPUStaticInst*
6687  {
6688  return new Inst_DS__DS_DEC_U64(&iFmt->iFmt_DS);
6689  } // decode_OP_DS__DS_DEC_U64
6690 
6691  GPUStaticInst*
6693  {
6694  return new Inst_DS__DS_MIN_I64(&iFmt->iFmt_DS);
6695  } // decode_OP_DS__DS_MIN_I64
6696 
6697  GPUStaticInst*
6699  {
6700  return new Inst_DS__DS_MAX_I64(&iFmt->iFmt_DS);
6701  } // decode_OP_DS__DS_MAX_I64
6702 
6703  GPUStaticInst*
6705  {
6706  return new Inst_DS__DS_MIN_U64(&iFmt->iFmt_DS);
6707  } // decode_OP_DS__DS_MIN_U64
6708 
6709  GPUStaticInst*
6711  {
6712  return new Inst_DS__DS_MAX_U64(&iFmt->iFmt_DS);
6713  } // decode_OP_DS__DS_MAX_U64
6714 
6715  GPUStaticInst*
6717  {
6718  return new Inst_DS__DS_AND_B64(&iFmt->iFmt_DS);
6719  } // decode_OP_DS__DS_AND_B64
6720 
6721  GPUStaticInst*
6723  {
6724  return new Inst_DS__DS_OR_B64(&iFmt->iFmt_DS);
6725  } // decode_OP_DS__DS_OR_B64
6726 
6727  GPUStaticInst*
6729  {
6730  return new Inst_DS__DS_XOR_B64(&iFmt->iFmt_DS);
6731  } // decode_OP_DS__DS_XOR_B64
6732 
6733  GPUStaticInst*
6735  {
6736  return new Inst_DS__DS_MSKOR_B64(&iFmt->iFmt_DS);
6737  } // decode_OP_DS__DS_MSKOR_B64
6738 
6739  GPUStaticInst*
6741  {
6742  return new Inst_DS__DS_WRITE_B64(&iFmt->iFmt_DS);
6743  } // decode_OP_DS__DS_WRITE_B64
6744 
6745  GPUStaticInst*
6747  {
6748  return new Inst_DS__DS_WRITE2_B64(&iFmt->iFmt_DS);
6749  } // decode_OP_DS__DS_WRITE2_B64
6750 
6751  GPUStaticInst*
6753  {
6754  return new Inst_DS__DS_WRITE2ST64_B64(&iFmt->iFmt_DS);
6755  } // decode_OP_DS__DS_WRITE2ST64_B64
6756 
6757  GPUStaticInst*
6759  {
6760  return new Inst_DS__DS_CMPST_B64(&iFmt->iFmt_DS);
6761  } // decode_OP_DS__DS_CMPST_B64
6762 
6763  GPUStaticInst*
6765  {
6766  return new Inst_DS__DS_CMPST_F64(&iFmt->iFmt_DS);
6767  } // decode_OP_DS__DS_CMPST_F64
6768 
6769  GPUStaticInst*
6771  {
6772  return new Inst_DS__DS_MIN_F64(&iFmt->iFmt_DS);
6773  } // decode_OP_DS__DS_MIN_F64
6774 
6775  GPUStaticInst*
6777  {
6778  return new Inst_DS__DS_MAX_F64(&iFmt->iFmt_DS);
6779  } // decode_OP_DS__DS_MAX_F64
6780 
6781  GPUStaticInst*
6783  {
6784  return new Inst_DS__DS_ADD_RTN_U64(&iFmt->iFmt_DS);
6785  } // decode_OP_DS__DS_ADD_RTN_U64
6786 
6787  GPUStaticInst*
6789  {
6790  return new Inst_DS__DS_SUB_RTN_U64(&iFmt->iFmt_DS);
6791  } // decode_OP_DS__DS_SUB_RTN_U64
6792 
6793  GPUStaticInst*
6795  {
6796  return new Inst_DS__DS_RSUB_RTN_U64(&iFmt->iFmt_DS);
6797  } // decode_OP_DS__DS_RSUB_RTN_U64
6798 
6799  GPUStaticInst*
6801  {
6802  return new Inst_DS__DS_INC_RTN_U64(&iFmt->iFmt_DS);
6803  } // decode_OP_DS__DS_INC_RTN_U64
6804 
6805  GPUStaticInst*
6807  {
6808  return new Inst_DS__DS_DEC_RTN_U64(&iFmt->iFmt_DS);
6809  } // decode_OP_DS__DS_DEC_RTN_U64
6810 
6811  GPUStaticInst*
6813  {
6814  return new Inst_DS__DS_MIN_RTN_I64(&iFmt->iFmt_DS);
6815  } // decode_OP_DS__DS_MIN_RTN_I64
6816 
6817  GPUStaticInst*
6819  {
6820  return new Inst_DS__DS_MAX_RTN_I64(&iFmt->iFmt_DS);
6821  } // decode_OP_DS__DS_MAX_RTN_I64
6822 
6823  GPUStaticInst*
6825  {
6826  return new Inst_DS__DS_MIN_RTN_U64(&iFmt->iFmt_DS);
6827  } // decode_OP_DS__DS_MIN_RTN_U64
6828 
6829  GPUStaticInst*
6831  {
6832  return new Inst_DS__DS_MAX_RTN_U64(&iFmt->iFmt_DS);
6833  } // decode_OP_DS__DS_MAX_RTN_U64
6834 
6835  GPUStaticInst*
6837  {
6838  return new Inst_DS__DS_AND_RTN_B64(&iFmt->iFmt_DS);
6839  } // decode_OP_DS__DS_AND_RTN_B64
6840 
6841  GPUStaticInst*
6843  {
6844  return new Inst_DS__DS_OR_RTN_B64(&iFmt->iFmt_DS);
6845  } // decode_OP_DS__DS_OR_RTN_B64
6846 
6847  GPUStaticInst*
6849  {
6850  return new Inst_DS__DS_XOR_RTN_B64(&iFmt->iFmt_DS);
6851  } // decode_OP_DS__DS_XOR_RTN_B64
6852 
6853  GPUStaticInst*
6855  {
6856  return new Inst_DS__DS_MSKOR_RTN_B64(&iFmt->iFmt_DS);
6857  } // decode_OP_DS__DS_MSKOR_RTN_B64
6858 
6859  GPUStaticInst*
6861  {
6862  return new Inst_DS__DS_WRXCHG_RTN_B64(&iFmt->iFmt_DS);
6863  } // decode_OP_DS__DS_WRXCHG_RTN_B64
6864 
6865  GPUStaticInst*
6867  {
6868  return new Inst_DS__DS_WRXCHG2_RTN_B64(&iFmt->iFmt_DS);
6869  } // decode_OP_DS__DS_WRXCHG2_RTN_B64
6870 
6871  GPUStaticInst*
6873  {
6874  return new Inst_DS__DS_WRXCHG2ST64_RTN_B64(&iFmt->iFmt_DS);
6875  } // decode_OP_DS__DS_WRXCHG2ST64_RTN_B64
6876 
6877  GPUStaticInst*
6879  {
6880  return new Inst_DS__DS_CMPST_RTN_B64(&iFmt->iFmt_DS);
6881  } // decode_OP_DS__DS_CMPST_RTN_B64
6882 
6883  GPUStaticInst*
6885  {
6886  return new Inst_DS__DS_CMPST_RTN_F64(&iFmt->iFmt_DS);
6887  } // decode_OP_DS__DS_CMPST_RTN_F64
6888 
6889  GPUStaticInst*
6891  {
6892  return new Inst_DS__DS_MIN_RTN_F64(&iFmt->iFmt_DS);
6893  } // decode_OP_DS__DS_MIN_RTN_F64
6894 
6895  GPUStaticInst*
6897  {
6898  return new Inst_DS__DS_MAX_RTN_F64(&iFmt->iFmt_DS);
6899  } // decode_OP_DS__DS_MAX_RTN_F64
6900 
6901  GPUStaticInst*
6903  {
6904  return new Inst_DS__DS_READ_B64(&iFmt->iFmt_DS);
6905  } // decode_OP_DS__DS_READ_B64
6906 
6907  GPUStaticInst*
6909  {
6910  return new Inst_DS__DS_READ2_B64(&iFmt->iFmt_DS);
6911  } // decode_OP_DS__DS_READ2_B64
6912 
6913  GPUStaticInst*
6915  {
6916  return new Inst_DS__DS_READ2ST64_B64(&iFmt->iFmt_DS);
6917  } // decode_OP_DS__DS_READ2ST64_B64
6918 
6919  GPUStaticInst*
6921  {
6922  return new Inst_DS__DS_CONDXCHG32_RTN_B64(&iFmt->iFmt_DS);
6923  } // decode_OP_DS__DS_CONDXCHG32_RTN_B64
6924 
6925  GPUStaticInst*
6927  {
6928  return new Inst_DS__DS_ADD_SRC2_U32(&iFmt->iFmt_DS);
6929  } // decode_OP_DS__DS_ADD_SRC2_U32
6930 
6931  GPUStaticInst*
6933  {
6934  return new Inst_DS__DS_SUB_SRC2_U32(&iFmt->iFmt_DS);
6935  } // decode_OP_DS__DS_SUB_SRC2_U32
6936 
6937  GPUStaticInst*
6939  {
6940  return new Inst_DS__DS_RSUB_SRC2_U32(&iFmt->iFmt_DS);
6941  } // decode_OP_DS__DS_RSUB_SRC2_U32
6942 
6943  GPUStaticInst*
6945  {
6946  return new Inst_DS__DS_INC_SRC2_U32(&iFmt->iFmt_DS);
6947  } // decode_OP_DS__DS_INC_SRC2_U32
6948 
6949  GPUStaticInst*
6951  {
6952  return new Inst_DS__DS_DEC_SRC2_U32(&iFmt->iFmt_DS);
6953  } // decode_OP_DS__DS_DEC_SRC2_U32
6954 
6955  GPUStaticInst*
6957  {
6958  return new Inst_DS__DS_MIN_SRC2_I32(&iFmt->iFmt_DS);
6959  } // decode_OP_DS__DS_MIN_SRC2_I32
6960 
6961  GPUStaticInst*
6963  {
6964  return new Inst_DS__DS_MAX_SRC2_I32(&iFmt->iFmt_DS);
6965  } // decode_OP_DS__DS_MAX_SRC2_I32
6966 
6967  GPUStaticInst*
6969  {
6970  return new Inst_DS__DS_MIN_SRC2_U32(&iFmt->iFmt_DS);
6971  } // decode_OP_DS__DS_MIN_SRC2_U32
6972 
6973  GPUStaticInst*
6975  {
6976  return new Inst_DS__DS_MAX_SRC2_U32(&iFmt->iFmt_DS);
6977  } // decode_OP_DS__DS_MAX_SRC2_U32
6978 
6979  GPUStaticInst*
6981  {
6982  return new Inst_DS__DS_AND_SRC2_B32(&iFmt->iFmt_DS);
6983  } // decode_OP_DS__DS_AND_SRC2_B32
6984 
6985  GPUStaticInst*
6987  {
6988  return new Inst_DS__DS_OR_SRC2_B32(&iFmt->iFmt_DS);
6989  } // decode_OP_DS__DS_OR_SRC2_B32
6990 
6991  GPUStaticInst*
6993  {
6994  return new Inst_DS__DS_XOR_SRC2_B32(&iFmt->iFmt_DS);
6995  } // decode_OP_DS__DS_XOR_SRC2_B32
6996 
6997  GPUStaticInst*
6999  {
7000  return new Inst_DS__DS_WRITE_SRC2_B32(&iFmt->iFmt_DS);
7001  } // decode_OP_DS__DS_WRITE_SRC2_B32
7002 
7003  GPUStaticInst*
7005  {
7006  return new Inst_DS__DS_MIN_SRC2_F32(&iFmt->iFmt_DS);
7007  } // decode_OP_DS__DS_MIN_SRC2_F32
7008 
7009  GPUStaticInst*
7011  {
7012  return new Inst_DS__DS_MAX_SRC2_F32(&iFmt->iFmt_DS);
7013  } // decode_OP_DS__DS_MAX_SRC2_F32
7014 
7015  GPUStaticInst*
7017  {
7018  return new Inst_DS__DS_ADD_SRC2_F32(&iFmt->iFmt_DS);
7019  } // decode_OP_DS__DS_ADD_SRC2_F32
7020 
7021  GPUStaticInst*
7023  {
7024  return new Inst_DS__DS_GWS_SEMA_RELEASE_ALL(&iFmt->iFmt_DS);
7025  } // decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL
7026 
7027  GPUStaticInst*
7029  {
7030  return new Inst_DS__DS_GWS_INIT(&iFmt->iFmt_DS);
7031  } // decode_OP_DS__DS_GWS_INIT
7032 
7033  GPUStaticInst*
7035  {
7036  return new Inst_DS__DS_GWS_SEMA_V(&iFmt->iFmt_DS);
7037  } // decode_OP_DS__DS_GWS_SEMA_V
7038 
7039  GPUStaticInst*
7041  {
7042  return new Inst_DS__DS_GWS_SEMA_BR(&iFmt->iFmt_DS);
7043  } // decode_OP_DS__DS_GWS_SEMA_BR
7044 
7045  GPUStaticInst*
7047  {
7048  return new Inst_DS__DS_GWS_SEMA_P(&iFmt->iFmt_DS);
7049  } // decode_OP_DS__DS_GWS_SEMA_P
7050 
7051  GPUStaticInst*
7053  {
7054  return new Inst_DS__DS_GWS_BARRIER(&iFmt->iFmt_DS);
7055  } // decode_OP_DS__DS_GWS_BARRIER
7056 
7057  GPUStaticInst*
7059  {
7060  return new Inst_DS__DS_CONSUME(&iFmt->iFmt_DS);
7061  } // decode_OP_DS__DS_CONSUME
7062 
7063  GPUStaticInst*
7065  {
7066  return new Inst_DS__DS_APPEND(&iFmt->iFmt_DS);
7067  } // decode_OP_DS__DS_APPEND
7068 
7069  GPUStaticInst*
7071  {
7072  return new Inst_DS__DS_ORDERED_COUNT(&iFmt->iFmt_DS);
7073  } // decode_OP_DS__DS_ORDERED_COUNT
7074 
7075  GPUStaticInst*
7077  {
7078  return new Inst_DS__DS_ADD_SRC2_U64(&iFmt->iFmt_DS);
7079  } // decode_OP_DS__DS_ADD_SRC2_U64
7080 
7081  GPUStaticInst*
7083  {
7084  return new Inst_DS__DS_SUB_SRC2_U64(&iFmt->iFmt_DS);
7085  } // decode_OP_DS__DS_SUB_SRC2_U64
7086 
7087  GPUStaticInst*
7089  {
7090  return new Inst_DS__DS_RSUB_SRC2_U64(&iFmt->iFmt_DS);
7091  } // decode_OP_DS__DS_RSUB_SRC2_U64
7092 
7093  GPUStaticInst*
7095  {
7096  return new Inst_DS__DS_INC_SRC2_U64(&iFmt->iFmt_DS);
7097  } // decode_OP_DS__DS_INC_SRC2_U64
7098 
7099  GPUStaticInst*
7101  {
7102  return new Inst_DS__DS_DEC_SRC2_U64(&iFmt->iFmt_DS);
7103  } // decode_OP_DS__DS_DEC_SRC2_U64
7104 
7105  GPUStaticInst*
7107  {
7108  return new Inst_DS__DS_MIN_SRC2_I64(&iFmt->iFmt_DS);
7109  } // decode_OP_DS__DS_MIN_SRC2_I64
7110 
7111  GPUStaticInst*
7113  {
7114  return new Inst_DS__DS_MAX_SRC2_I64(&iFmt->iFmt_DS);
7115  } // decode_OP_DS__DS_MAX_SRC2_I64
7116 
7117  GPUStaticInst*
7119  {
7120  return new Inst_DS__DS_MIN_SRC2_U64(&iFmt->iFmt_DS);
7121  } // decode_OP_DS__DS_MIN_SRC2_U64
7122 
7123  GPUStaticInst*
7125  {
7126  return new Inst_DS__DS_MAX_SRC2_U64(&iFmt->iFmt_DS);
7127  } // decode_OP_DS__DS_MAX_SRC2_U64
7128 
7129  GPUStaticInst*
7131  {
7132  return new Inst_DS__DS_AND_SRC2_B64(&iFmt->iFmt_DS);
7133  } // decode_OP_DS__DS_AND_SRC2_B64
7134 
7135  GPUStaticInst*
7137  {
7138  return new Inst_DS__DS_OR_SRC2_B64(&iFmt->iFmt_DS);
7139  } // decode_OP_DS__DS_OR_SRC2_B64
7140 
7141  GPUStaticInst*
7143  {
7144  return new Inst_DS__DS_XOR_SRC2_B64(&iFmt->iFmt_DS);
7145  } // decode_OP_DS__DS_XOR_SRC2_B64
7146 
7147  GPUStaticInst*
7149  {
7150  return new Inst_DS__DS_WRITE_SRC2_B64(&iFmt->iFmt_DS);
7151  } // decode_OP_DS__DS_WRITE_SRC2_B64
7152 
7153  GPUStaticInst*
7155  {
7156  return new Inst_DS__DS_MIN_SRC2_F64(&iFmt->iFmt_DS);
7157  } // decode_OP_DS__DS_MIN_SRC2_F64
7158 
7159  GPUStaticInst*
7161  {
7162  return new Inst_DS__DS_MAX_SRC2_F64(&iFmt->iFmt_DS);
7163  } // decode_OP_DS__DS_MAX_SRC2_F64
7164 
7165  GPUStaticInst*
7167  {
7168  return new Inst_DS__DS_WRITE_B96(&iFmt->iFmt_DS);
7169  } // decode_OP_DS__DS_WRITE_B96
7170 
7171  GPUStaticInst*
7173  {
7174  return new Inst_DS__DS_WRITE_B128(&iFmt->iFmt_DS);
7175  } // decode_OP_DS__DS_WRITE_B128
7176 
7177  GPUStaticInst*
7179  {
7180  return new Inst_DS__DS_READ_B96(&iFmt->iFmt_DS);
7181  } // decode_OP_DS__DS_READ_B96
7182 
7183  GPUStaticInst*
7185  {
7186  return new Inst_DS__DS_READ_B128(&iFmt->iFmt_DS);
7187  } // decode_OP_DS__DS_READ_B128
7188 
7189  GPUStaticInst*
7191  {
7192  return new Inst_FLAT__FLAT_LOAD_UBYTE(&iFmt->iFmt_FLAT);
7193  } // decode_OP_FLAT__FLAT_LOAD_UBYTE
7194 
7195  GPUStaticInst*
7197  {
7198  return new Inst_FLAT__FLAT_LOAD_SBYTE(&iFmt->iFmt_FLAT);
7199  } // decode_OP_FLAT__FLAT_LOAD_SBYTE
7200 
7201  GPUStaticInst*
7203  {
7204  return new Inst_FLAT__FLAT_LOAD_USHORT(&iFmt->iFmt_FLAT);
7205  } // decode_OP_FLAT__FLAT_LOAD_USHORT
7206 
7207  GPUStaticInst*
7209  {
7210  return new Inst_FLAT__FLAT_LOAD_SSHORT(&iFmt->iFmt_FLAT);
7211  } // decode_OP_FLAT__FLAT_LOAD_SSHORT
7212 
7213  GPUStaticInst*
7215  {
7216  return new Inst_FLAT__FLAT_LOAD_DWORD(&iFmt->iFmt_FLAT);
7217  } // decode_OP_FLAT__FLAT_LOAD_DWORD
7218 
7219  GPUStaticInst*
7221  {
7222  return new Inst_FLAT__FLAT_LOAD_DWORDX2(&iFmt->iFmt_FLAT);
7223  } // decode_OP_FLAT__FLAT_LOAD_DWORDX2
7224 
7225  GPUStaticInst*
7227  {
7228  return new Inst_FLAT__FLAT_LOAD_DWORDX3(&iFmt->iFmt_FLAT);
7229  } // decode_OP_FLAT__FLAT_LOAD_DWORDX3
7230 
7231  GPUStaticInst*
7233  {
7234  return new Inst_FLAT__FLAT_LOAD_DWORDX4(&iFmt->iFmt_FLAT);
7235  } // decode_OP_FLAT__FLAT_LOAD_DWORDX4
7236 
7237  GPUStaticInst*
7239  {
7240  return new Inst_FLAT__FLAT_STORE_BYTE(&iFmt->iFmt_FLAT);
7241  } // decode_OP_FLAT__FLAT_STORE_BYTE
7242 
7243  GPUStaticInst*
7245  {
7246  return new Inst_FLAT__FLAT_STORE_SHORT(&iFmt->iFmt_FLAT);
7247  } // decode_OP_FLAT__FLAT_STORE_SHORT
7248 
7249  GPUStaticInst*
7251  {
7252  return new Inst_FLAT__FLAT_STORE_DWORD(&iFmt->iFmt_FLAT);
7253  } // decode_OP_FLAT__FLAT_STORE_DWORD
7254 
7255  GPUStaticInst*
7257  {
7258  return new Inst_FLAT__FLAT_STORE_DWORDX2(&iFmt->iFmt_FLAT);
7259  } // decode_OP_FLAT__FLAT_STORE_DWORDX2
7260 
7261  GPUStaticInst*
7263  {
7264  return new Inst_FLAT__FLAT_STORE_DWORDX3(&iFmt->iFmt_FLAT);
7265  } // decode_OP_FLAT__FLAT_STORE_DWORDX3
7266 
7267  GPUStaticInst*
7269  {
7270  return new Inst_FLAT__FLAT_STORE_DWORDX4(&iFmt->iFmt_FLAT);
7271  } // decode_OP_FLAT__FLAT_STORE_DWORDX4
7272 
7273  GPUStaticInst*
7275  {
7276  return new Inst_FLAT__FLAT_ATOMIC_SWAP(&iFmt->iFmt_FLAT);
7277  } // decode_OP_FLAT__FLAT_ATOMIC_SWAP
7278 
7279  GPUStaticInst*
7281  {
7282  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP(&iFmt->iFmt_FLAT);
7283  } // decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP
7284 
7285  GPUStaticInst*
7287  {
7288  return new Inst_FLAT__FLAT_ATOMIC_ADD(&iFmt->iFmt_FLAT);
7289  } // decode_OP_FLAT__FLAT_ATOMIC_ADD
7290 
7291  GPUStaticInst*
7293  {
7294  return new Inst_FLAT__FLAT_ATOMIC_SUB(&iFmt->iFmt_FLAT);
7295  } // decode_OP_FLAT__FLAT_ATOMIC_SUB
7296 
7297  GPUStaticInst*
7299  {
7300  return new Inst_FLAT__FLAT_ATOMIC_SMIN(&iFmt->iFmt_FLAT);
7301  } // decode_OP_FLAT__FLAT_ATOMIC_SMIN
7302 
7303  GPUStaticInst*
7305  {
7306  return new Inst_FLAT__FLAT_ATOMIC_UMIN(&iFmt->iFmt_FLAT);
7307  } // decode_OP_FLAT__FLAT_ATOMIC_UMIN
7308 
7309  GPUStaticInst*
7311  {
7312  return new Inst_FLAT__FLAT_ATOMIC_SMAX(&iFmt->iFmt_FLAT);
7313  } // decode_OP_FLAT__FLAT_ATOMIC_SMAX
7314 
7315  GPUStaticInst*
7317  {
7318  return new Inst_FLAT__FLAT_ATOMIC_UMAX(&iFmt->iFmt_FLAT);
7319  } // decode_OP_FLAT__FLAT_ATOMIC_UMAX
7320 
7321  GPUStaticInst*
7323  {
7324  return new Inst_FLAT__FLAT_ATOMIC_AND(&iFmt->iFmt_FLAT);
7325  } // decode_OP_FLAT__FLAT_ATOMIC_AND
7326 
7327  GPUStaticInst*
7329  {
7330  return new Inst_FLAT__FLAT_ATOMIC_OR(&iFmt->iFmt_FLAT);
7331  } // decode_OP_FLAT__FLAT_ATOMIC_OR
7332 
7333  GPUStaticInst*
7335  {
7336  return new Inst_FLAT__FLAT_ATOMIC_XOR(&iFmt->iFmt_FLAT);
7337  } // decode_OP_FLAT__FLAT_ATOMIC_XOR
7338 
7339  GPUStaticInst*
7341  {
7342  return new Inst_FLAT__FLAT_ATOMIC_INC(&iFmt->iFmt_FLAT);
7343  } // decode_OP_FLAT__FLAT_ATOMIC_INC
7344 
7345  GPUStaticInst*
7347  {
7348  return new Inst_FLAT__FLAT_ATOMIC_DEC(&iFmt->iFmt_FLAT);
7349  } // decode_OP_FLAT__FLAT_ATOMIC_DEC
7350 
7351  GPUStaticInst*
7353  {
7354  return new Inst_FLAT__FLAT_ATOMIC_SWAP_X2(&iFmt->iFmt_FLAT);
7355  } // decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2
7356 
7357  GPUStaticInst*
7359  {
7360  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2(&iFmt->iFmt_FLAT);
7361  } // decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2
7362 
7363  GPUStaticInst*
7365  {
7366  return new Inst_FLAT__FLAT_ATOMIC_ADD_X2(&iFmt->iFmt_FLAT);
7367  } // decode_OP_FLAT__FLAT_ATOMIC_ADD_X2
7368 
7369  GPUStaticInst*
7371  {
7372  return new Inst_FLAT__FLAT_ATOMIC_SUB_X2(&iFmt->iFmt_FLAT);
7373  } // decode_OP_FLAT__FLAT_ATOMIC_SUB_X2
7374 
7375  GPUStaticInst*
7377  {
7378  return new Inst_FLAT__FLAT_ATOMIC_SMIN_X2(&iFmt->iFmt_FLAT);
7379  } // decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2
7380 
7381  GPUStaticInst*
7383  {
7384  return new Inst_FLAT__FLAT_ATOMIC_UMIN_X2(&iFmt->iFmt_FLAT);
7385  } // decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2
7386 
7387  GPUStaticInst*
7389  {
7390  return new Inst_FLAT__FLAT_ATOMIC_SMAX_X2(&iFmt->iFmt_FLAT);
7391  } // decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2
7392 
7393  GPUStaticInst*
7395  {
7396  return new Inst_FLAT__FLAT_ATOMIC_UMAX_X2(&iFmt->iFmt_FLAT);
7397  } // decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2
7398 
7399  GPUStaticInst*
7401  {
7402  return new Inst_FLAT__FLAT_ATOMIC_AND_X2(&iFmt->iFmt_FLAT);
7403  } // decode_OP_FLAT__FLAT_ATOMIC_AND_X2
7404 
7405  GPUStaticInst*
7407  {
7408  return new Inst_FLAT__FLAT_ATOMIC_OR_X2(&iFmt->iFmt_FLAT);
7409  } // decode_OP_FLAT__FLAT_ATOMIC_OR_X2
7410 
7411  GPUStaticInst*
7413  {
7414  return new Inst_FLAT__FLAT_ATOMIC_XOR_X2(&iFmt->iFmt_FLAT);
7415  } // decode_OP_FLAT__FLAT_ATOMIC_XOR_X2
7416 
7417  GPUStaticInst*
7419  {
7420  return new Inst_FLAT__FLAT_ATOMIC_INC_X2(&iFmt->iFmt_FLAT);
7421  } // decode_OP_FLAT__FLAT_ATOMIC_INC_X2
7422 
7423  GPUStaticInst*
7425  {
7426  return new Inst_FLAT__FLAT_ATOMIC_DEC_X2(&iFmt->iFmt_FLAT);
7427  } // decode_OP_FLAT__FLAT_ATOMIC_DEC_X2
7428 
7429  GPUStaticInst*
7431  {
7432  return new Inst_MIMG__IMAGE_LOAD(&iFmt->iFmt_MIMG);
7433  } // decode_OP_MIMG__IMAGE_LOAD
7434 
7435  GPUStaticInst*
7437  {
7438  return new Inst_MIMG__IMAGE_LOAD_MIP(&iFmt->iFmt_MIMG);
7439  } // decode_OP_MIMG__IMAGE_LOAD_MIP
7440 
7441  GPUStaticInst*
7443  {
7444  return new Inst_MIMG__IMAGE_LOAD_PCK(&iFmt->iFmt_MIMG);
7445  } // decode_OP_MIMG__IMAGE_LOAD_PCK
7446 
7447  GPUStaticInst*
7449  {
7450  return new Inst_MIMG__IMAGE_LOAD_PCK_SGN(&iFmt->iFmt_MIMG);
7451  } // decode_OP_MIMG__IMAGE_LOAD_PCK_SGN
7452 
7453  GPUStaticInst*
7455  {
7456  return new Inst_MIMG__IMAGE_LOAD_MIP_PCK(&iFmt->iFmt_MIMG);
7457  } // decode_OP_MIMG__IMAGE_LOAD_MIP_PCK
7458 
7459  GPUStaticInst*
7461  {
7462  return new Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN(&iFmt->iFmt_MIMG);
7463  } // decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN
7464 
7465  GPUStaticInst*
7467  {
7468  return new Inst_MIMG__IMAGE_STORE(&iFmt->iFmt_MIMG);
7469  } // decode_OP_MIMG__IMAGE_STORE
7470 
7471  GPUStaticInst*
7473  {
7474  return new Inst_MIMG__IMAGE_STORE_MIP(&iFmt->iFmt_MIMG);
7475  } // decode_OP_MIMG__IMAGE_STORE_MIP
7476 
7477  GPUStaticInst*
7479  {
7480  return new Inst_MIMG__IMAGE_STORE_PCK(&iFmt->iFmt_MIMG);
7481  } // decode_OP_MIMG__IMAGE_STORE_PCK
7482 
7483  GPUStaticInst*
7485  {
7486  return new Inst_MIMG__IMAGE_STORE_MIP_PCK(&iFmt->iFmt_MIMG);
7487  } // decode_OP_MIMG__IMAGE_STORE_MIP_PCK
7488 
7489  GPUStaticInst*
7491  {
7492  return new Inst_MIMG__IMAGE_GET_RESINFO(&iFmt->iFmt_MIMG);
7493  } // decode_OP_MIMG__IMAGE_GET_RESINFO
7494 
7495  GPUStaticInst*
7497  {
7498  return new Inst_MIMG__IMAGE_ATOMIC_SWAP(&iFmt->iFmt_MIMG);
7499  } // decode_OP_MIMG__IMAGE_ATOMIC_SWAP
7500 
7501  GPUStaticInst*
7503  {
7504  return new Inst_MIMG__IMAGE_ATOMIC_CMPSWAP(&iFmt->iFmt_MIMG);
7505  } // decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP
7506 
7507  GPUStaticInst*
7509  {
7510  return new Inst_MIMG__IMAGE_ATOMIC_ADD(&iFmt->iFmt_MIMG);
7511  } // decode_OP_MIMG__IMAGE_ATOMIC_ADD
7512 
7513  GPUStaticInst*
7515  {
7516  return new Inst_MIMG__IMAGE_ATOMIC_SUB(&iFmt->iFmt_MIMG);
7517  } // decode_OP_MIMG__IMAGE_ATOMIC_SUB
7518 
7519  GPUStaticInst*
7521  {
7522  return new Inst_MIMG__IMAGE_ATOMIC_SMIN(&iFmt->iFmt_MIMG);
7523  } // decode_OP_MIMG__IMAGE_ATOMIC_SMIN
7524 
7525  GPUStaticInst*
7527  {
7528  return new Inst_MIMG__IMAGE_ATOMIC_UMIN(&iFmt->iFmt_MIMG);
7529  } // decode_OP_MIMG__IMAGE_ATOMIC_UMIN
7530 
7531  GPUStaticInst*
7533  {
7534  return new Inst_MIMG__IMAGE_ATOMIC_SMAX(&iFmt->iFmt_MIMG);
7535  } // decode_OP_MIMG__IMAGE_ATOMIC_SMAX
7536 
7537  GPUStaticInst*
7539  {
7540  return new Inst_MIMG__IMAGE_ATOMIC_UMAX(&iFmt->iFmt_MIMG);
7541  } // decode_OP_MIMG__IMAGE_ATOMIC_UMAX
7542 
7543  GPUStaticInst*
7545  {
7546  return new Inst_MIMG__IMAGE_ATOMIC_AND(&iFmt->iFmt_MIMG);
7547  } // decode_OP_MIMG__IMAGE_ATOMIC_AND
7548 
7549  GPUStaticInst*
7551  {
7552  return new Inst_MIMG__IMAGE_ATOMIC_OR(&iFmt->iFmt_MIMG);
7553  } // decode_OP_MIMG__IMAGE_ATOMIC_OR
7554 
7555  GPUStaticInst*
7557  {
7558  return new Inst_MIMG__IMAGE_ATOMIC_XOR(&iFmt->iFmt_MIMG);
7559  } // decode_OP_MIMG__IMAGE_ATOMIC_XOR
7560 
7561  GPUStaticInst*
7563  {
7564  return new Inst_MIMG__IMAGE_ATOMIC_INC(&iFmt->iFmt_MIMG);
7565  } // decode_OP_MIMG__IMAGE_ATOMIC_INC
7566 
7567  GPUStaticInst*
7569  {
7570  return new Inst_MIMG__IMAGE_ATOMIC_DEC(&iFmt->iFmt_MIMG);
7571  } // decode_OP_MIMG__IMAGE_ATOMIC_DEC
7572 
7573  GPUStaticInst*
7575  {
7576  return new Inst_MIMG__IMAGE_SAMPLE(&iFmt->iFmt_MIMG);
7577  } // decode_OP_MIMG__IMAGE_SAMPLE
7578 
7579  GPUStaticInst*
7581  {
7582  return new Inst_MIMG__IMAGE_SAMPLE_CL(&iFmt->iFmt_MIMG);
7583  } // decode_OP_MIMG__IMAGE_SAMPLE_CL
7584 
7585  GPUStaticInst*
7587  {
7588  return new Inst_MIMG__IMAGE_SAMPLE_D(&iFmt->iFmt_MIMG);
7589  } // decode_OP_MIMG__IMAGE_SAMPLE_D
7590 
7591  GPUStaticInst*
7593  {
7594  return new Inst_MIMG__IMAGE_SAMPLE_D_CL(&iFmt->iFmt_MIMG);
7595  } // decode_OP_MIMG__IMAGE_SAMPLE_D_CL
7596 
7597  GPUStaticInst*
7599  {
7600  return new Inst_MIMG__IMAGE_SAMPLE_L(&iFmt->iFmt_MIMG);
7601  } // decode_OP_MIMG__IMAGE_SAMPLE_L
7602 
7603  GPUStaticInst*
7605  {
7606  return new Inst_MIMG__IMAGE_SAMPLE_B(&iFmt->iFmt_MIMG);
7607  } // decode_OP_MIMG__IMAGE_SAMPLE_B
7608 
7609  GPUStaticInst*
7611  {
7612  return new Inst_MIMG__IMAGE_SAMPLE_B_CL(&iFmt->iFmt_MIMG);
7613  } // decode_OP_MIMG__IMAGE_SAMPLE_B_CL
7614 
7615  GPUStaticInst*
7617  {
7618  return new Inst_MIMG__IMAGE_SAMPLE_LZ(&iFmt->iFmt_MIMG);
7619  } // decode_OP_MIMG__IMAGE_SAMPLE_LZ
7620 
7621  GPUStaticInst*
7623  {
7624  return new Inst_MIMG__IMAGE_SAMPLE_C(&iFmt->iFmt_MIMG);
7625  } // decode_OP_MIMG__IMAGE_SAMPLE_C
7626 
7627  GPUStaticInst*
7629  {
7630  return new Inst_MIMG__IMAGE_SAMPLE_C_CL(&iFmt->iFmt_MIMG);
7631  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CL
7632 
7633  GPUStaticInst*
7635  {
7636  return new Inst_MIMG__IMAGE_SAMPLE_C_D(&iFmt->iFmt_MIMG);
7637  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D
7638 
7639  GPUStaticInst*
7641  {
7642  return new Inst_MIMG__IMAGE_SAMPLE_C_D_CL(&iFmt->iFmt_MIMG);
7643  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL
7644 
7645  GPUStaticInst*
7647  {
7648  return new Inst_MIMG__IMAGE_SAMPLE_C_L(&iFmt->iFmt_MIMG);
7649  } // decode_OP_MIMG__IMAGE_SAMPLE_C_L
7650 
7651  GPUStaticInst*
7653  {
7654  return new Inst_MIMG__IMAGE_SAMPLE_C_B(&iFmt->iFmt_MIMG);
7655  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B
7656 
7657  GPUStaticInst*
7659  {
7660  return new Inst_MIMG__IMAGE_SAMPLE_C_B_CL(&iFmt->iFmt_MIMG);
7661  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL
7662 
7663  GPUStaticInst*
7665  {
7666  return new Inst_MIMG__IMAGE_SAMPLE_C_LZ(&iFmt->iFmt_MIMG);
7667  } // decode_OP_MIMG__IMAGE_SAMPLE_C_LZ
7668 
7669  GPUStaticInst*
7671  {
7672  return new Inst_MIMG__IMAGE_SAMPLE_O(&iFmt->iFmt_MIMG);
7673  } // decode_OP_MIMG__IMAGE_SAMPLE_O
7674 
7675  GPUStaticInst*
7677  {
7678  return new Inst_MIMG__IMAGE_SAMPLE_CL_O(&iFmt->iFmt_MIMG);
7679  } // decode_OP_MIMG__IMAGE_SAMPLE_CL_O
7680 
7681  GPUStaticInst*
7683  {
7684  return new Inst_MIMG__IMAGE_SAMPLE_D_O(&iFmt->iFmt_MIMG);
7685  } // decode_OP_MIMG__IMAGE_SAMPLE_D_O
7686 
7687  GPUStaticInst*
7689  {
7690  return new Inst_MIMG__IMAGE_SAMPLE_D_CL_O(&iFmt->iFmt_MIMG);
7691  } // decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O
7692 
7693  GPUStaticInst*
7695  {
7696  return new Inst_MIMG__IMAGE_SAMPLE_L_O(&iFmt->iFmt_MIMG);
7697  } // decode_OP_MIMG__IMAGE_SAMPLE_L_O
7698 
7699  GPUStaticInst*
7701  {
7702  return new Inst_MIMG__IMAGE_SAMPLE_B_O(&iFmt->iFmt_MIMG);
7703  } // decode_OP_MIMG__IMAGE_SAMPLE_B_O
7704 
7705  GPUStaticInst*
7707  {
7708  return new Inst_MIMG__IMAGE_SAMPLE_B_CL_O(&iFmt->iFmt_MIMG);
7709  } // decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O
7710 
7711  GPUStaticInst*
7713  {
7714  return new Inst_MIMG__IMAGE_SAMPLE_LZ_O(&iFmt->iFmt_MIMG);
7715  } // decode_OP_MIMG__IMAGE_SAMPLE_LZ_O
7716 
7717  GPUStaticInst*
7719  {
7720  return new Inst_MIMG__IMAGE_SAMPLE_C_O(&iFmt->iFmt_MIMG);
7721  } // decode_OP_MIMG__IMAGE_SAMPLE_C_O
7722 
7723  GPUStaticInst*
7725  {
7726  return new Inst_MIMG__IMAGE_SAMPLE_C_CL_O(&iFmt->iFmt_MIMG);
7727  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O
7728 
7729  GPUStaticInst*
7731  {
7732  return new Inst_MIMG__IMAGE_SAMPLE_C_D_O(&iFmt->iFmt_MIMG);
7733  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_O
7734 
7735  GPUStaticInst*
7737  {
7738  return new Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O(&iFmt->iFmt_MIMG);
7739  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O
7740 
7741  GPUStaticInst*
7743  {
7744  return new Inst_MIMG__IMAGE_SAMPLE_C_L_O(&iFmt->iFmt_MIMG);
7745  } // decode_OP_MIMG__IMAGE_SAMPLE_C_L_O
7746 
7747  GPUStaticInst*
7749  {
7750  return new Inst_MIMG__IMAGE_SAMPLE_C_B_O(&iFmt->iFmt_MIMG);
7751  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_O
7752 
7753  GPUStaticInst*
7755  {
7756  return new Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O(&iFmt->iFmt_MIMG);
7757  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O
7758 
7759  GPUStaticInst*
7761  {
7762  return new Inst_MIMG__IMAGE_SAMPLE_C_LZ_O(&iFmt->iFmt_MIMG);
7763  } // decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O
7764 
7765  GPUStaticInst*
7767  {
7768  return new Inst_MIMG__IMAGE_GATHER4(&iFmt->iFmt_MIMG);
7769  } // decode_OP_MIMG__IMAGE_GATHER4
7770 
7771  GPUStaticInst*
7773  {
7774  return new Inst_MIMG__IMAGE_GATHER4_CL(&iFmt->iFmt_MIMG);
7775  } // decode_OP_MIMG__IMAGE_GATHER4_CL
7776 
7777  GPUStaticInst*
7779  {
7780  return new Inst_MIMG__IMAGE_GATHER4_L(&iFmt->iFmt_MIMG);
7781  } // decode_OP_MIMG__IMAGE_GATHER4_L
7782 
7783  GPUStaticInst*
7785  {
7786  return new Inst_MIMG__IMAGE_GATHER4_B(&iFmt->iFmt_MIMG);
7787  } // decode_OP_MIMG__IMAGE_GATHER4_B
7788 
7789  GPUStaticInst*
7791  {
7792  return new Inst_MIMG__IMAGE_GATHER4_B_CL(&iFmt->iFmt_MIMG);
7793  } // decode_OP_MIMG__IMAGE_GATHER4_B_CL
7794 
7795  GPUStaticInst*
7797  {
7798  return new Inst_MIMG__IMAGE_GATHER4_LZ(&iFmt->iFmt_MIMG);
7799  } // decode_OP_MIMG__IMAGE_GATHER4_LZ
7800 
7801  GPUStaticInst*
7803  {
7804  return new Inst_MIMG__IMAGE_GATHER4_C(&iFmt->iFmt_MIMG);
7805  } // decode_OP_MIMG__IMAGE_GATHER4_C
7806 
7807  GPUStaticInst*
7809  {
7810  return new Inst_MIMG__IMAGE_GATHER4_C_CL(&iFmt->iFmt_MIMG);
7811  } // decode_OP_MIMG__IMAGE_GATHER4_C_CL
7812 
7813  GPUStaticInst*
7815  {
7816  return new Inst_MIMG__IMAGE_GATHER4_C_L(&iFmt->iFmt_MIMG);
7817  } // decode_OP_MIMG__IMAGE_GATHER4_C_L
7818 
7819  GPUStaticInst*
7821  {
7822  return new Inst_MIMG__IMAGE_GATHER4_C_B(&iFmt->iFmt_MIMG);
7823  } // decode_OP_MIMG__IMAGE_GATHER4_C_B
7824 
7825  GPUStaticInst*
7827  {
7828  return new Inst_MIMG__IMAGE_GATHER4_C_B_CL(&iFmt->iFmt_MIMG);
7829  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_CL
7830 
7831  GPUStaticInst*
7833  {
7834  return new Inst_MIMG__IMAGE_GATHER4_C_LZ(&iFmt->iFmt_MIMG);
7835  } // decode_OP_MIMG__IMAGE_GATHER4_C_LZ
7836 
7837  GPUStaticInst*
7839  {
7840  return new Inst_MIMG__IMAGE_GATHER4_O(&iFmt->iFmt_MIMG);
7841  } // decode_OP_MIMG__IMAGE_GATHER4_O
7842 
7843  GPUStaticInst*
7845  {
7846  return new Inst_MIMG__IMAGE_GATHER4_CL_O(&iFmt->iFmt_MIMG);
7847  } // decode_OP_MIMG__IMAGE_GATHER4_CL_O
7848 
7849  GPUStaticInst*
7851  {
7852  return new Inst_MIMG__IMAGE_GATHER4_L_O(&iFmt->iFmt_MIMG);
7853  } // decode_OP_MIMG__IMAGE_GATHER4_L_O
7854 
7855  GPUStaticInst*
7857  {
7858  return new Inst_MIMG__IMAGE_GATHER4_B_O(&iFmt->iFmt_MIMG);
7859  } // decode_OP_MIMG__IMAGE_GATHER4_B_O
7860 
7861  GPUStaticInst*
7863  {
7864  return new Inst_MIMG__IMAGE_GATHER4_B_CL_O(&iFmt->iFmt_MIMG);
7865  } // decode_OP_MIMG__IMAGE_GATHER4_B_CL_O
7866 
7867  GPUStaticInst*
7869  {
7870  return new Inst_MIMG__IMAGE_GATHER4_LZ_O(&iFmt->iFmt_MIMG);
7871  } // decode_OP_MIMG__IMAGE_GATHER4_LZ_O
7872 
7873  GPUStaticInst*
7875  {
7876  return new Inst_MIMG__IMAGE_GATHER4_C_O(&iFmt->iFmt_MIMG);
7877  } // decode_OP_MIMG__IMAGE_GATHER4_C_O
7878 
7879  GPUStaticInst*
7881  {
7882  return new Inst_MIMG__IMAGE_GATHER4_C_CL_O(&iFmt->iFmt_MIMG);
7883  } // decode_OP_MIMG__IMAGE_GATHER4_C_CL_O
7884 
7885  GPUStaticInst*
7887  {
7888  return new Inst_MIMG__IMAGE_GATHER4_C_L_O(&iFmt->iFmt_MIMG);
7889  } // decode_OP_MIMG__IMAGE_GATHER4_C_L_O
7890 
7891  GPUStaticInst*
7893  {
7894  return new Inst_MIMG__IMAGE_GATHER4_C_B_O(&iFmt->iFmt_MIMG);
7895  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_O
7896 
7897  GPUStaticInst*
7899  {
7900  return new Inst_MIMG__IMAGE_GATHER4_C_B_CL_O(&iFmt->iFmt_MIMG);
7901  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O
7902 
7903  GPUStaticInst*
7905  {
7906  return new Inst_MIMG__IMAGE_GATHER4_C_LZ_O(&iFmt->iFmt_MIMG);
7907  } // decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O
7908 
7909  GPUStaticInst*
7911  {
7912  return new Inst_MIMG__IMAGE_GET_LOD(&iFmt->iFmt_MIMG);
7913  } // decode_OP_MIMG__IMAGE_GET_LOD
7914 
7915  GPUStaticInst*
7917  {
7918  return new Inst_MIMG__IMAGE_SAMPLE_CD(&iFmt->iFmt_MIMG);
7919  } // decode_OP_MIMG__IMAGE_SAMPLE_CD
7920 
7921  GPUStaticInst*
7923  {
7924  return new Inst_MIMG__IMAGE_SAMPLE_CD_CL(&iFmt->iFmt_MIMG);
7925  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_CL
7926 
7927  GPUStaticInst*
7929  {
7930  return new Inst_MIMG__IMAGE_SAMPLE_C_CD(&iFmt->iFmt_MIMG);
7931  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD
7932 
7933  GPUStaticInst*
7935  {
7936  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_CL(&iFmt->iFmt_MIMG);
7937  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL
7938 
7939  GPUStaticInst*
7941  {
7942  return new Inst_MIMG__IMAGE_SAMPLE_CD_O(&iFmt->iFmt_MIMG);
7943  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_O
7944 
7945  GPUStaticInst*
7947  {
7948  return new Inst_MIMG__IMAGE_SAMPLE_CD_CL_O(&iFmt->iFmt_MIMG);
7949  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O
7950 
7951  GPUStaticInst*
7953  {
7954  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_O(&iFmt->iFmt_MIMG);
7955  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O
7956 
7957  GPUStaticInst*
7959  {
7960  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O(&iFmt->iFmt_MIMG);
7961  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O
7962 
7963  GPUStaticInst*
7965  {
7966  return new Inst_MTBUF__TBUFFER_LOAD_FORMAT_X(&iFmt->iFmt_MTBUF);
7967  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X
7968 
7969  GPUStaticInst*
7971  {
7973  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY
7974 
7975  GPUStaticInst*
7977  {
7979  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
7980 
7981  GPUStaticInst*
7983  {
7985  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
7986 
7987  GPUStaticInst*
7989  {
7991  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X
7992 
7993  GPUStaticInst*
7995  {
7997  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY
7998 
7999  GPUStaticInst*
8001  {
8003  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ
8004 
8005  GPUStaticInst*
8007  {
8009  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW
8010 
8011  GPUStaticInst*
8013  {
8015  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
8016 
8017  GPUStaticInst*
8019  {
8021  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
8022 
8023  GPUStaticInst*
8025  {
8027  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
8028 
8029  GPUStaticInst*
8031  {
8033  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
8034 
8035  GPUStaticInst*
8037  {
8039  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X
8040 
8041  GPUStaticInst*
8043  {
8045  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
8046 
8047  GPUStaticInst*
8049  {
8051  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
8052 
8053  GPUStaticInst*
8055  {
8056  return new
8058  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
8059 
8060  GPUStaticInst*
8062  {
8063  return new Inst_MUBUF__BUFFER_LOAD_FORMAT_X(&iFmt->iFmt_MUBUF);
8064  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X
8065 
8066  GPUStaticInst*
8068  {
8069  return new Inst_MUBUF__BUFFER_LOAD_FORMAT_XY(&iFmt->iFmt_MUBUF);
8070  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY
8071 
8072  GPUStaticInst*
8074  {
8076  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ
8077 
8078  GPUStaticInst*
8080  {
8082  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW
8083 
8084  GPUStaticInst*
8086  {
8087  return new Inst_MUBUF__BUFFER_STORE_FORMAT_X(&iFmt->iFmt_MUBUF);
8088  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_X
8089 
8090  GPUStaticInst*
8092  {
8094  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY
8095 
8096  GPUStaticInst*
8098  {
8100  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ
8101 
8102  GPUStaticInst*
8104  {
8106  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW
8107 
8108  GPUStaticInst*
8110  {
8112  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X
8113 
8114  GPUStaticInst*
8116  {
8118  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
8119 
8120  GPUStaticInst*
8122  {
8124  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
8125 
8126  GPUStaticInst*
8128  {
8130  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
8131 
8132  GPUStaticInst*
8134  {
8136  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X
8137 
8138  GPUStaticInst*
8140  {
8142  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY
8143 
8144  GPUStaticInst*
8146  {
8148  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
8149 
8150  GPUStaticInst*
8152  {
8154  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
8155 
8156  GPUStaticInst*
8158  {
8159  return new Inst_MUBUF__BUFFER_LOAD_UBYTE(&iFmt->iFmt_MUBUF);
8160  } // decode_OP_MUBUF__BUFFER_LOAD_UBYTE
8161 
8162  GPUStaticInst*
8164  {
8165  return new Inst_MUBUF__BUFFER_LOAD_SBYTE(&iFmt->iFmt_MUBUF);
8166  } // decode_OP_MUBUF__BUFFER_LOAD_SBYTE
8167 
8168  GPUStaticInst*
8170  {
8171  return new Inst_MUBUF__BUFFER_LOAD_USHORT(&iFmt->iFmt_MUBUF);
8172  } // decode_OP_MUBUF__BUFFER_LOAD_USHORT
8173 
8174  GPUStaticInst*
8176  {
8177  return new Inst_MUBUF__BUFFER_LOAD_SSHORT(&iFmt->iFmt_MUBUF);
8178  } // decode_OP_MUBUF__BUFFER_LOAD_SSHORT
8179 
8180  GPUStaticInst*
8182  {
8183  return new Inst_MUBUF__BUFFER_LOAD_DWORD(&iFmt->iFmt_MUBUF);
8184  } // decode_OP_MUBUF__BUFFER_LOAD_DWORD
8185 
8186  GPUStaticInst*
8188  {
8189  return new Inst_MUBUF__BUFFER_LOAD_DWORDX2(&iFmt->iFmt_MUBUF);
8190  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX2
8191 
8192  GPUStaticInst*
8194  {
8195  return new Inst_MUBUF__BUFFER_LOAD_DWORDX3(&iFmt->iFmt_MUBUF);
8196  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX3
8197 
8198  GPUStaticInst*
8200  {
8201  return new Inst_MUBUF__BUFFER_LOAD_DWORDX4(&iFmt->iFmt_MUBUF);
8202  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX4
8203 
8204  GPUStaticInst*
8206  {
8207  return new Inst_MUBUF__BUFFER_STORE_BYTE(&iFmt->iFmt_MUBUF);
8208  } // decode_OP_MUBUF__BUFFER_STORE_BYTE
8209 
8210  GPUStaticInst*
8212  {
8213  return new Inst_MUBUF__BUFFER_STORE_SHORT(&iFmt->iFmt_MUBUF);
8214  } // decode_OP_MUBUF__BUFFER_STORE_SHORT
8215 
8216  GPUStaticInst*
8218  {
8219  return new Inst_MUBUF__BUFFER_STORE_DWORD(&iFmt->iFmt_MUBUF);
8220  } // decode_OP_MUBUF__BUFFER_STORE_DWORD
8221 
8222  GPUStaticInst*
8224  {
8225  return new Inst_MUBUF__BUFFER_STORE_DWORDX2(&iFmt->iFmt_MUBUF);
8226  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX2
8227 
8228  GPUStaticInst*
8230  {
8231  return new Inst_MUBUF__BUFFER_STORE_DWORDX3(&iFmt->iFmt_MUBUF);
8232  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX3
8233 
8234  GPUStaticInst*
8236  {
8237  return new Inst_MUBUF__BUFFER_STORE_DWORDX4(&iFmt->iFmt_MUBUF);
8238  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX4
8239 
8240  GPUStaticInst*
8242  {
8244  } // decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD
8245 
8246  GPUStaticInst*
8248  {
8249  return new Inst_MUBUF__BUFFER_WBINVL1(&iFmt->iFmt_MUBUF);
8250  } // decode_OP_MUBUF__BUFFER_WBINVL1
8251 
8252  GPUStaticInst*
8254  {
8255  return new Inst_MUBUF__BUFFER_WBINVL1_VOL(&iFmt->iFmt_MUBUF);
8256  } // decode_OP_MUBUF__BUFFER_WBINVL1_VOL
8257 
8258  GPUStaticInst*
8260  {
8261  return new Inst_MUBUF__BUFFER_ATOMIC_SWAP(&iFmt->iFmt_MUBUF);
8262  } // decode_OP_MUBUF__BUFFER_ATOMIC_SWAP
8263 
8264  GPUStaticInst*
8266  {
8267  return new Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP(&iFmt->iFmt_MUBUF);
8268  } // decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP
8269 
8270  GPUStaticInst*
8272  {
8273  return new Inst_MUBUF__BUFFER_ATOMIC_ADD(&iFmt->iFmt_MUBUF);
8274  } // decode_OP_MUBUF__BUFFER_ATOMIC_ADD
8275 
8276  GPUStaticInst*
8278  {
8279  return new Inst_MUBUF__BUFFER_ATOMIC_SUB(&iFmt->iFmt_MUBUF);
8280  } // decode_OP_MUBUF__BUFFER_ATOMIC_SUB
8281 
8282  GPUStaticInst*
8284  {
8285  return new Inst_MUBUF__BUFFER_ATOMIC_SMIN(&iFmt->iFmt_MUBUF);
8286  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMIN
8287 
8288  GPUStaticInst*
8290  {
8291  return new Inst_MUBUF__BUFFER_ATOMIC_UMIN(&iFmt->iFmt_MUBUF);
8292  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMIN
8293 
8294  GPUStaticInst*
8296  {
8297  return new Inst_MUBUF__BUFFER_ATOMIC_SMAX(&iFmt->iFmt_MUBUF);
8298  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMAX
8299 
8300  GPUStaticInst*
8302  {
8303  return new Inst_MUBUF__BUFFER_ATOMIC_UMAX(&iFmt->iFmt_MUBUF);
8304  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMAX
8305 
8306  GPUStaticInst*
8308  {
8309  return new Inst_MUBUF__BUFFER_ATOMIC_AND(&iFmt->iFmt_MUBUF);
8310  } // decode_OP_MUBUF__BUFFER_ATOMIC_AND
8311 
8312  GPUStaticInst*
8314  {
8315  return new Inst_MUBUF__BUFFER_ATOMIC_OR(&iFmt->iFmt_MUBUF);
8316  } // decode_OP_MUBUF__BUFFER_ATOMIC_OR
8317 
8318  GPUStaticInst*
8320  {
8321  return new Inst_MUBUF__BUFFER_ATOMIC_XOR(&iFmt->iFmt_MUBUF);
8322  } // decode_OP_MUBUF__BUFFER_ATOMIC_XOR
8323 
8324  GPUStaticInst*
8326  {
8327  return new Inst_MUBUF__BUFFER_ATOMIC_INC(&iFmt->iFmt_MUBUF);
8328  } // decode_OP_MUBUF__BUFFER_ATOMIC_INC
8329 
8330  GPUStaticInst*
8332  {
8333  return new Inst_MUBUF__BUFFER_ATOMIC_DEC(&iFmt->iFmt_MUBUF);
8334  } // decode_OP_MUBUF__BUFFER_ATOMIC_DEC
8335 
8336  GPUStaticInst*
8338  {
8339  return new Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2(&iFmt->iFmt_MUBUF);
8340  } // decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2
8341 
8342  GPUStaticInst*
8344  {
8346  } // decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
8347 
8348  GPUStaticInst*
8350  {
8351  return new Inst_MUBUF__BUFFER_ATOMIC_ADD_X2(&iFmt->iFmt_MUBUF);
8352  } // decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2
8353 
8354  GPUStaticInst*
8356  {
8357  return new Inst_MUBUF__BUFFER_ATOMIC_SUB_X2(&iFmt->iFmt_MUBUF);
8358  } // decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2
8359 
8360  GPUStaticInst*
8362  {
8363  return new Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2(&iFmt->iFmt_MUBUF);
8364  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2
8365 
8366  GPUStaticInst*
8368  {
8369  return new Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2(&iFmt->iFmt_MUBUF);
8370  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2
8371 
8372  GPUStaticInst*
8374  {
8375  return new Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2(&iFmt->iFmt_MUBUF);
8376  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2
8377 
8378  GPUStaticInst*
8380  {
8381  return new Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2(&iFmt->iFmt_MUBUF);
8382  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2
8383 
8384  GPUStaticInst*
8386  {
8387  return new Inst_MUBUF__BUFFER_ATOMIC_AND_X2(&iFmt->iFmt_MUBUF);
8388  } // decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2
8389 
8390  GPUStaticInst*
8392  {
8393  return new Inst_MUBUF__BUFFER_ATOMIC_OR_X2(&iFmt->iFmt_MUBUF);
8394  } // decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2
8395 
8396  GPUStaticInst*
8398  {
8399  return new Inst_MUBUF__BUFFER_ATOMIC_XOR_X2(&iFmt->iFmt_MUBUF);
8400  } // decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2
8401 
8402  GPUStaticInst*
8404  {
8405  return new Inst_MUBUF__BUFFER_ATOMIC_INC_X2(&iFmt->iFmt_MUBUF);
8406  } // decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2
8407 
8408  GPUStaticInst*
8410  {
8411  return new Inst_MUBUF__BUFFER_ATOMIC_DEC_X2(&iFmt->iFmt_MUBUF);
8412  } // decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2
8413 
8414  GPUStaticInst*
8416  {
8417  return new Inst_SMEM__S_LOAD_DWORD(&iFmt->iFmt_SMEM);
8418  } // decode_OP_SMEM__S_LOAD_DWORD
8419 
8420  GPUStaticInst*
8422  {
8423  return new Inst_SMEM__S_LOAD_DWORDX2(&iFmt->iFmt_SMEM);
8424  } // decode_OP_SMEM__S_LOAD_DWORDX2
8425 
8426  GPUStaticInst*
8428  {
8429  return new Inst_SMEM__S_LOAD_DWORDX4(&iFmt->iFmt_SMEM);
8430  } // decode_OP_SMEM__S_LOAD_DWORDX4
8431 
8432  GPUStaticInst*
8434  {
8435  return new Inst_SMEM__S_LOAD_DWORDX8(&iFmt->iFmt_SMEM);
8436  } // decode_OP_SMEM__S_LOAD_DWORDX8
8437 
8438  GPUStaticInst*
8440  {
8441  return new Inst_SMEM__S_LOAD_DWORDX16(&iFmt->iFmt_SMEM);
8442  } // decode_OP_SMEM__S_LOAD_DWORDX16
8443 
8444  GPUStaticInst*
8446  {
8447  return new Inst_SMEM__S_BUFFER_LOAD_DWORD(&iFmt->iFmt_SMEM);
8448  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORD
8449 
8450  GPUStaticInst*
8452  {
8453  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX2(&iFmt->iFmt_SMEM);
8454  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2
8455 
8456  GPUStaticInst*
8458  {
8459  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX4(&iFmt->iFmt_SMEM);
8460  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4
8461 
8462  GPUStaticInst*
8464  {
8465  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX8(&iFmt->iFmt_SMEM);
8466  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8
8467 
8468  GPUStaticInst*
8470  {
8471  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX16(&iFmt->iFmt_SMEM);
8472  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16
8473 
8474  GPUStaticInst*
8476  {
8477  return new Inst_SMEM__S_STORE_DWORD(&iFmt->iFmt_SMEM);
8478  } // decode_OP_SMEM__S_STORE_DWORD
8479 
8480  GPUStaticInst*
8482  {
8483  return new Inst_SMEM__S_STORE_DWORDX2(&iFmt->iFmt_SMEM);
8484  } // decode_OP_SMEM__S_STORE_DWORDX2
8485 
8486  GPUStaticInst*
8488  {
8489  return new Inst_SMEM__S_STORE_DWORDX4(&iFmt->iFmt_SMEM);
8490  } // decode_OP_SMEM__S_STORE_DWORDX4
8491 
8492  GPUStaticInst*
8494  {
8495  return new Inst_SMEM__S_BUFFER_STORE_DWORD(&iFmt->iFmt_SMEM);
8496  } // decode_OP_SMEM__S_BUFFER_STORE_DWORD
8497 
8498  GPUStaticInst*
8500  {
8501  return new Inst_SMEM__S_BUFFER_STORE_DWORDX2(&iFmt->iFmt_SMEM);
8502  } // decode_OP_SMEM__S_BUFFER_STORE_DWORDX2
8503 
8504  GPUStaticInst*
8506  {
8507  return new Inst_SMEM__S_BUFFER_STORE_DWORDX4(&iFmt->iFmt_SMEM);
8508  } // decode_OP_SMEM__S_BUFFER_STORE_DWORDX4
8509 
8510  GPUStaticInst*
8512  {
8513  return new Inst_SMEM__S_DCACHE_INV(&iFmt->iFmt_SMEM);
8514  } // decode_OP_SMEM__S_DCACHE_INV
8515 
8516  GPUStaticInst*
8518  {
8519  return new Inst_SMEM__S_DCACHE_WB(&iFmt->iFmt_SMEM);
8520  } // decode_OP_SMEM__S_DCACHE_WB
8521 
8522  GPUStaticInst*
8524  {
8525  return new Inst_SMEM__S_DCACHE_INV_VOL(&iFmt->iFmt_SMEM);
8526  } // decode_OP_SMEM__S_DCACHE_INV_VOL
8527 
8528  GPUStaticInst*
8530  {
8531  return new Inst_SMEM__S_DCACHE_WB_VOL(&iFmt->iFmt_SMEM);
8532  } // decode_OP_SMEM__S_DCACHE_WB_VOL
8533 
8534  GPUStaticInst*
8536  {
8537  return new Inst_SMEM__S_MEMTIME(&iFmt->iFmt_SMEM);
8538  } // decode_OP_SMEM__S_MEMTIME
8539 
8540  GPUStaticInst*
8542  {
8543  return new Inst_SMEM__S_MEMREALTIME(&iFmt->iFmt_SMEM);
8544  } // decode_OP_SMEM__S_MEMREALTIME
8545 
8546  GPUStaticInst*
8548  {
8549  return new Inst_SMEM__S_ATC_PROBE(&iFmt->iFmt_SMEM);
8550  } // decode_OP_SMEM__S_ATC_PROBE
8551 
8552  GPUStaticInst*
8554  {
8555  return new Inst_SMEM__S_ATC_PROBE_BUFFER(&iFmt->iFmt_SMEM);
8556  } // decode_OP_SMEM__S_ATC_PROBE_BUFFER
8557 
8558  GPUStaticInst*
8560  {
8561  return new Inst_SOP1__S_MOV_B32(&iFmt->iFmt_SOP1);
8562  } // decode_OP_SOP1__S_MOV_B32
8563 
8564  GPUStaticInst*
8566  {
8567  return new Inst_SOP1__S_MOV_B64(&iFmt->iFmt_SOP1);
8568  } // decode_OP_SOP1__S_MOV_B64
8569 
8570  GPUStaticInst*
8572  {
8573  return new Inst_SOP1__S_CMOV_B32(&iFmt->iFmt_SOP1);
8574  } // decode_OP_SOP1__S_CMOV_B32
8575 
8576  GPUStaticInst*
8578  {
8579  return new Inst_SOP1__S_CMOV_B64(&iFmt->iFmt_SOP1);
8580  } // decode_OP_SOP1__S_CMOV_B64
8581 
8582  GPUStaticInst*
8584  {
8585  return new Inst_SOP1__S_NOT_B32(&iFmt->iFmt_SOP1);
8586  } // decode_OP_SOP1__S_NOT_B32
8587 
8588  GPUStaticInst*
8590  {
8591  return new Inst_SOP1__S_NOT_B64(&iFmt->iFmt_SOP1);
8592  } // decode_OP_SOP1__S_NOT_B64
8593 
8594  GPUStaticInst*
8596  {
8597  return new Inst_SOP1__S_WQM_B32(&iFmt->iFmt_SOP1);
8598  } // decode_OP_SOP1__S_WQM_B32
8599 
8600  GPUStaticInst*
8602  {
8603  return new Inst_SOP1__S_WQM_B64(&iFmt->iFmt_SOP1);
8604  } // decode_OP_SOP1__S_WQM_B64
8605 
8606  GPUStaticInst*
8608  {
8609  return new Inst_SOP1__S_BREV_B32(&iFmt->iFmt_SOP1);
8610  } // decode_OP_SOP1__S_BREV_B32
8611 
8612  GPUStaticInst*
8614  {
8615  return new Inst_SOP1__S_BREV_B64(&iFmt->iFmt_SOP1);
8616  } // decode_OP_SOP1__S_BREV_B64
8617 
8618  GPUStaticInst*
8620  {
8621  return new Inst_SOP1__S_BCNT0_I32_B32(&iFmt->iFmt_SOP1);
8622  } // decode_OP_SOP1__S_BCNT0_I32_B32
8623 
8624  GPUStaticInst*
8626  {
8627  return new Inst_SOP1__S_BCNT0_I32_B64(&iFmt->iFmt_SOP1);
8628  } // decode_OP_SOP1__S_BCNT0_I32_B64
8629 
8630  GPUStaticInst*
8632  {
8633  return new Inst_SOP1__S_BCNT1_I32_B32(&iFmt->iFmt_SOP1);
8634  } // decode_OP_SOP1__S_BCNT1_I32_B32
8635 
8636  GPUStaticInst*
8638  {
8639  return new Inst_SOP1__S_BCNT1_I32_B64(&iFmt->iFmt_SOP1);
8640  } // decode_OP_SOP1__S_BCNT1_I32_B64
8641 
8642  GPUStaticInst*
8644  {
8645  return new Inst_SOP1__S_FF0_I32_B32(&iFmt->iFmt_SOP1);
8646  } // decode_OP_SOP1__S_FF0_I32_B32
8647 
8648  GPUStaticInst*
8650  {
8651  return new Inst_SOP1__S_FF0_I32_B64(&iFmt->iFmt_SOP1);
8652  } // decode_OP_SOP1__S_FF0_I32_B64
8653 
8654  GPUStaticInst*
8656  {
8657  return new Inst_SOP1__S_FF1_I32_B32(&iFmt->iFmt_SOP1);
8658  } // decode_OP_SOP1__S_FF1_I32_B32
8659 
8660  GPUStaticInst*
8662  {
8663  return new Inst_SOP1__S_FF1_I32_B64(&iFmt->iFmt_SOP1);
8664  } // decode_OP_SOP1__S_FF1_I32_B64
8665 
8666  GPUStaticInst*
8668  {
8669  return new Inst_SOP1__S_FLBIT_I32_B32(&iFmt->iFmt_SOP1);
8670  } // decode_OP_SOP1__S_FLBIT_I32_B32
8671 
8672  GPUStaticInst*
8674  {
8675  return new Inst_SOP1__S_FLBIT_I32_B64(&iFmt->iFmt_SOP1);
8676  } // decode_OP_SOP1__S_FLBIT_I32_B64
8677 
8678  GPUStaticInst*
8680  {
8681  return new Inst_SOP1__S_FLBIT_I32(&iFmt->iFmt_SOP1);
8682  } // decode_OP_SOP1__S_FLBIT_I32
8683 
8684  GPUStaticInst*
8686  {
8687  return new Inst_SOP1__S_FLBIT_I32_I64(&iFmt->iFmt_SOP1);
8688  } // decode_OP_SOP1__S_FLBIT_I32_I64
8689 
8690  GPUStaticInst*
8692  {
8693  return new Inst_SOP1__S_SEXT_I32_I8(&iFmt->iFmt_SOP1);
8694  } // decode_OP_SOP1__S_SEXT_I32_I8
8695 
8696  GPUStaticInst*
8698  {
8699  return new Inst_SOP1__S_SEXT_I32_I16(&iFmt->iFmt_SOP1);
8700  } // decode_OP_SOP1__S_SEXT_I32_I16
8701 
8702  GPUStaticInst*
8704  {
8705  return new Inst_SOP1__S_BITSET0_B32(&iFmt->iFmt_SOP1);
8706  } // decode_OP_SOP1__S_BITSET0_B32
8707 
8708  GPUStaticInst*
8710  {
8711  return new Inst_SOP1__S_BITSET0_B64(&iFmt->iFmt_SOP1);
8712  } // decode_OP_SOP1__S_BITSET0_B64
8713 
8714  GPUStaticInst*
8716  {
8717  return new Inst_SOP1__S_BITSET1_B32(&iFmt->iFmt_SOP1);
8718  } // decode_OP_SOP1__S_BITSET1_B32
8719 
8720  GPUStaticInst*
8722  {
8723  return new Inst_SOP1__S_BITSET1_B64(&iFmt->iFmt_SOP1);
8724  } // decode_OP_SOP1__S_BITSET1_B64
8725 
8726  GPUStaticInst*
8728  {
8729  return new Inst_SOP1__S_GETPC_B64(&iFmt->iFmt_SOP1);
8730  } // decode_OP_SOP1__S_GETPC_B64
8731 
8732  GPUStaticInst*
8734  {
8735  return new Inst_SOP1__S_SETPC_B64(&iFmt->iFmt_SOP1);
8736  } // decode_OP_SOP1__S_SETPC_B64
8737 
8738  GPUStaticInst*
8740  {
8741  return new Inst_SOP1__S_SWAPPC_B64(&iFmt->iFmt_SOP1);
8742  } // decode_OP_SOP1__S_SWAPPC_B64
8743 
8744  GPUStaticInst*
8746  {
8747  return new Inst_SOP1__S_RFE_B64(&iFmt->iFmt_SOP1);
8748  } // decode_OP_SOP1__S_RFE_B64
8749 
8750  GPUStaticInst*
8752  {
8753  return new Inst_SOP1__S_AND_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
8754  } // decode_OP_SOP1__S_AND_SAVEEXEC_B64
8755 
8756  GPUStaticInst*
8758  {
8759  return new Inst_SOP1__S_OR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
8760  } // decode_OP_SOP1__S_OR_SAVEEXEC_B64
8761 
8762  GPUStaticInst*
8764  {
8765  return new Inst_SOP1__S_XOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
8766  } // decode_OP_SOP1__S_XOR_SAVEEXEC_B64
8767 
8768  GPUStaticInst*
8770  {
8771  return new Inst_SOP1__S_ANDN2_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
8772  } // decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64
8773 
8774  GPUStaticInst*
8776  {
8777  return new Inst_SOP1__S_ORN2_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
8778  } // decode_OP_SOP1__S_ORN2_SAVEEXEC_B64
8779 
8780  GPUStaticInst*
8782  {
8783  return new Inst_SOP1__S_NAND_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
8784  } // decode_OP_SOP1__S_NAND_SAVEEXEC_B64
8785 
8786  GPUStaticInst*
8788  {
8789  return new Inst_SOP1__S_NOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
8790  } // decode_OP_SOP1__S_NOR_SAVEEXEC_B64
8791 
8792  GPUStaticInst*
8794  {
8795  return new Inst_SOP1__S_XNOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
8796  } // decode_OP_SOP1__S_XNOR_SAVEEXEC_B64
8797 
8798  GPUStaticInst*
8800  {
8801  return new Inst_SOP1__S_QUADMASK_B32(&iFmt->iFmt_SOP1);
8802  } // decode_OP_SOP1__S_QUADMASK_B32
8803 
8804  GPUStaticInst*
8806  {
8807  return new Inst_SOP1__S_QUADMASK_B64(&iFmt->iFmt_SOP1);
8808  } // decode_OP_SOP1__S_QUADMASK_B64
8809 
8810  GPUStaticInst*
8812  {
8813  return new Inst_SOP1__S_MOVRELS_B32(&iFmt->iFmt_SOP1);
8814  } // decode_OP_SOP1__S_MOVRELS_B32
8815 
8816  GPUStaticInst*
8818  {
8819  return new Inst_SOP1__S_MOVRELS_B64(&iFmt->iFmt_SOP1);
8820  } // decode_OP_SOP1__S_MOVRELS_B64
8821 
8822  GPUStaticInst*
8824  {
8825  return new Inst_SOP1__S_MOVRELD_B32(&iFmt->iFmt_SOP1);
8826  } // decode_OP_SOP1__S_MOVRELD_B32
8827 
8828  GPUStaticInst*
8830  {
8831  return new Inst_SOP1__S_MOVRELD_B64(&iFmt->iFmt_SOP1);
8832  } // decode_OP_SOP1__S_MOVRELD_B64
8833 
8834  GPUStaticInst*
8836  {
8837  return new Inst_SOP1__S_CBRANCH_JOIN(&iFmt->iFmt_SOP1);
8838  } // decode_OP_SOP1__S_CBRANCH_JOIN
8839 
8840  GPUStaticInst*
8842  {
8843  return new Inst_SOP1__S_ABS_I32(&iFmt->iFmt_SOP1);
8844  } // decode_OP_SOP1__S_ABS_I32
8845 
8846  GPUStaticInst*
8848  {
8849  return new Inst_SOP1__S_MOV_FED_B32(&iFmt->iFmt_SOP1);
8850  } // decode_OP_SOP1__S_MOV_FED_B32
8851 
8852  GPUStaticInst*
8854  {
8855  return new Inst_SOP1__S_SET_GPR_IDX_IDX(&iFmt->iFmt_SOP1);
8856  } // decode_OP_SOP1__S_SET_GPR_IDX_IDX
8857 
8858  GPUStaticInst*
8860  {
8861  return new Inst_SOPC__S_CMP_EQ_I32(&iFmt->iFmt_SOPC);
8862  } // decode_OP_SOPC__S_CMP_EQ_I32
8863 
8864  GPUStaticInst*
8866  {
8867  return new Inst_SOPC__S_CMP_LG_I32(&iFmt->iFmt_SOPC);
8868  } // decode_OP_SOPC__S_CMP_LG_I32
8869 
8870  GPUStaticInst*
8872  {
8873  return new Inst_SOPC__S_CMP_GT_I32(&iFmt->iFmt_SOPC);
8874  } // decode_OP_SOPC__S_CMP_GT_I32
8875 
8876  GPUStaticInst*
8878  {
8879  return new Inst_SOPC__S_CMP_GE_I32(&iFmt->iFmt_SOPC);
8880  } // decode_OP_SOPC__S_CMP_GE_I32
8881 
8882  GPUStaticInst*
8884  {
8885  return new Inst_SOPC__S_CMP_LT_I32(&iFmt->iFmt_SOPC);
8886  } // decode_OP_SOPC__S_CMP_LT_I32
8887 
8888  GPUStaticInst*
8890  {
8891  return new Inst_SOPC__S_CMP_LE_I32(&iFmt->iFmt_SOPC);
8892  } // decode_OP_SOPC__S_CMP_LE_I32
8893 
8894  GPUStaticInst*
8896  {
8897  return new Inst_SOPC__S_CMP_EQ_U32(&iFmt->iFmt_SOPC);
8898  } // decode_OP_SOPC__S_CMP_EQ_U32
8899 
8900  GPUStaticInst*
8902  {
8903  return new Inst_SOPC__S_CMP_LG_U32(&iFmt->iFmt_SOPC);
8904  } // decode_OP_SOPC__S_CMP_LG_U32
8905 
8906  GPUStaticInst*
8908  {
8909  return new Inst_SOPC__S_CMP_GT_U32(&iFmt->iFmt_SOPC);
8910  } // decode_OP_SOPC__S_CMP_GT_U32
8911 
8912  GPUStaticInst*
8914  {
8915  return new Inst_SOPC__S_CMP_GE_U32(&iFmt->iFmt_SOPC);
8916  } // decode_OP_SOPC__S_CMP_GE_U32
8917 
8918  GPUStaticInst*
8920  {
8921  return new Inst_SOPC__S_CMP_LT_U32(&iFmt->iFmt_SOPC);
8922  } // decode_OP_SOPC__S_CMP_LT_U32
8923 
8924  GPUStaticInst*
8926  {
8927  return new Inst_SOPC__S_CMP_LE_U32(&iFmt->iFmt_SOPC);
8928  } // decode_OP_SOPC__S_CMP_LE_U32
8929 
8930  GPUStaticInst*
8932  {
8933  return new Inst_SOPC__S_BITCMP0_B32(&iFmt->iFmt_SOPC);
8934  } // decode_OP_SOPC__S_BITCMP0_B32
8935 
8936  GPUStaticInst*
8938  {
8939  return new Inst_SOPC__S_BITCMP1_B32(&iFmt->iFmt_SOPC);
8940  } // decode_OP_SOPC__S_BITCMP1_B32
8941 
8942  GPUStaticInst*
8944  {
8945  return new Inst_SOPC__S_BITCMP0_B64(&iFmt->iFmt_SOPC);
8946  } // decode_OP_SOPC__S_BITCMP0_B64
8947 
8948  GPUStaticInst*
8950  {
8951  return new Inst_SOPC__S_BITCMP1_B64(&iFmt->iFmt_SOPC);
8952  } // decode_OP_SOPC__S_BITCMP1_B64
8953 
8954  GPUStaticInst*
8956  {
8957  return new Inst_SOPC__S_SETVSKIP(&iFmt->iFmt_SOPC);
8958  } // decode_OP_SOPC__S_SETVSKIP
8959 
8960  GPUStaticInst*
8962  {
8963  return new Inst_SOPC__S_SET_GPR_IDX_ON(&iFmt->iFmt_SOPC);
8964  } // decode_OP_SOPC__S_SET_GPR_IDX_ON
8965 
8966  GPUStaticInst*
8968  {
8969  return new Inst_SOPC__S_CMP_EQ_U64(&iFmt->iFmt_SOPC);
8970  } // decode_OP_SOPC__S_CMP_EQ_U64
8971 
8972  GPUStaticInst*
8974  {
8975  return new Inst_SOPC__S_CMP_LG_U64(&iFmt->iFmt_SOPC);
8976  } // decode_OP_SOPC__S_CMP_LG_U64
8977 
8978  GPUStaticInst*
8980  {
8981  return new Inst_SOPP__S_NOP(&iFmt->iFmt_SOPP);
8982  } // decode_OP_SOPP__S_NOP
8983 
8984  GPUStaticInst*
8986  {
8987  return new Inst_SOPP__S_ENDPGM(&iFmt->iFmt_SOPP);
8988  } // decode_OP_SOPP__S_ENDPGM
8989 
8990  GPUStaticInst*
8992  {
8993  return new Inst_SOPP__S_BRANCH(&iFmt->iFmt_SOPP);
8994  } // decode_OP_SOPP__S_BRANCH
8995 
8996  GPUStaticInst*
8998  {
8999  return new Inst_SOPP__S_WAKEUP(&iFmt->iFmt_SOPP);
9000  } // decode_OP_SOPP__S_WAKEUP
9001 
9002  GPUStaticInst*
9004  {
9005  return new Inst_SOPP__S_CBRANCH_SCC0(&iFmt->iFmt_SOPP);
9006  } // decode_OP_SOPP__S_CBRANCH_SCC0
9007 
9008  GPUStaticInst*
9010  {
9011  return new Inst_SOPP__S_CBRANCH_SCC1(&iFmt->iFmt_SOPP);
9012  } // decode_OP_SOPP__S_CBRANCH_SCC1
9013 
9014  GPUStaticInst*
9016  {
9017  return new Inst_SOPP__S_CBRANCH_VCCZ(&iFmt->iFmt_SOPP);
9018  } // decode_OP_SOPP__S_CBRANCH_VCCZ
9019 
9020  GPUStaticInst*
9022  {
9023  return new Inst_SOPP__S_CBRANCH_VCCNZ(&iFmt->iFmt_SOPP);
9024  } // decode_OP_SOPP__S_CBRANCH_VCCNZ
9025 
9026  GPUStaticInst*
9028  {
9029  return new Inst_SOPP__S_CBRANCH_EXECZ(&iFmt->iFmt_SOPP);
9030  } // decode_OP_SOPP__S_CBRANCH_EXECZ
9031 
9032  GPUStaticInst*
9034  {
9035  return new Inst_SOPP__S_CBRANCH_EXECNZ(&iFmt->iFmt_SOPP);
9036  } // decode_OP_SOPP__S_CBRANCH_EXECNZ
9037 
9038  GPUStaticInst*
9040  {
9041  return new Inst_SOPP__S_BARRIER(&iFmt->iFmt_SOPP);
9042  } // decode_OP_SOPP__S_BARRIER
9043 
9044  GPUStaticInst*
9046  {
9047  return new Inst_SOPP__S_SETKILL(&iFmt->iFmt_SOPP);
9048  } // decode_OP_SOPP__S_SETKILL
9049 
9050  GPUStaticInst*
9052  {
9053  return new Inst_SOPP__S_WAITCNT(&iFmt->iFmt_SOPP);
9054  } // decode_OP_SOPP__S_WAITCNT
9055 
9056  GPUStaticInst*
9058  {
9059  return new Inst_SOPP__S_SETHALT(&iFmt->iFmt_SOPP);
9060  } // decode_OP_SOPP__S_SETHALT
9061 
9062  GPUStaticInst*
9064  {
9065  return new Inst_SOPP__S_SLEEP(&iFmt->iFmt_SOPP);
9066  } // decode_OP_SOPP__S_SLEEP
9067 
9068  GPUStaticInst*
9070  {
9071  return new Inst_SOPP__S_SETPRIO(&iFmt->iFmt_SOPP);
9072  } // decode_OP_SOPP__S_SETPRIO
9073 
9074  GPUStaticInst*
9076  {
9077  return new Inst_SOPP__S_SENDMSG(&iFmt->iFmt_SOPP);
9078  } // decode_OP_SOPP__S_SENDMSG
9079 
9080  GPUStaticInst*
9082  {
9083  return new Inst_SOPP__S_SENDMSGHALT(&iFmt->iFmt_SOPP);
9084  } // decode_OP_SOPP__S_SENDMSGHALT
9085 
9086  GPUStaticInst*
9088  {
9089  return new Inst_SOPP__S_TRAP(&iFmt->iFmt_SOPP);
9090  } // decode_OP_SOPP__S_TRAP
9091 
9092  GPUStaticInst*
9094  {
9095  return new Inst_SOPP__S_ICACHE_INV(&iFmt->iFmt_SOPP);
9096  } // decode_OP_SOPP__S_ICACHE_INV
9097 
9098  GPUStaticInst*
9100  {
9101  return new Inst_SOPP__S_INCPERFLEVEL(&iFmt->iFmt_SOPP);
9102  } // decode_OP_SOPP__S_INCPERFLEVEL
9103 
9104  GPUStaticInst*
9106  {
9107  return new Inst_SOPP__S_DECPERFLEVEL(&iFmt->iFmt_SOPP);
9108  } // decode_OP_SOPP__S_DECPERFLEVEL
9109 
9110  GPUStaticInst*
9112  {
9113  return new Inst_SOPP__S_TTRACEDATA(&iFmt->iFmt_SOPP);
9114  } // decode_OP_SOPP__S_TTRACEDATA
9115 
9116  GPUStaticInst*
9118  {
9119  return new Inst_SOPP__S_CBRANCH_CDBGSYS(&iFmt->iFmt_SOPP);
9120  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS
9121 
9122  GPUStaticInst*
9124  {
9125  return new Inst_SOPP__S_CBRANCH_CDBGUSER(&iFmt->iFmt_SOPP);
9126  } // decode_OP_SOPP__S_CBRANCH_CDBGUSER
9127 
9128  GPUStaticInst*
9130  {
9132  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER
9133 
9134  GPUStaticInst*
9136  {
9138  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER
9139 
9140  GPUStaticInst*
9142  {
9143  return new Inst_SOPP__S_ENDPGM_SAVED(&iFmt->iFmt_SOPP);
9144  } // decode_OP_SOPP__S_ENDPGM_SAVED
9145 
9146  GPUStaticInst*
9148  {
9149  return new Inst_SOPP__S_SET_GPR_IDX_OFF(&iFmt->iFmt_SOPP);
9150  } // decode_OP_SOPP__S_SET_GPR_IDX_OFF
9151 
9152  GPUStaticInst*
9154  {
9155  return new Inst_SOPP__S_SET_GPR_IDX_MODE(&iFmt->iFmt_SOPP);
9156  } // decode_OP_SOPP__S_SET_GPR_IDX_MODE
9157 
9158  GPUStaticInst*
9160  {
9161  return new Inst_VINTRP__V_INTERP_P1_F32(&iFmt->iFmt_VINTRP);
9162  } // decode_OP_VINTRP__V_INTERP_P1_F32
9163 
9164  GPUStaticInst*
9166  {
9167  return new Inst_VINTRP__V_INTERP_P2_F32(&iFmt->iFmt_VINTRP);
9168  } // decode_OP_VINTRP__V_INTERP_P2_F32
9169 
9170  GPUStaticInst*
9172  {
9173  return new Inst_VINTRP__V_INTERP_MOV_F32(&iFmt->iFmt_VINTRP);
9174  } // decode_OP_VINTRP__V_INTERP_MOV_F32
9175 
9176  GPUStaticInst*
9178  {
9179  return new Inst_VOP1__V_NOP(&iFmt->iFmt_VOP1);
9180  } // decode_OP_VOP1__V_NOP
9181 
9182  GPUStaticInst*
9184  {
9185  return new Inst_VOP1__V_MOV_B32(&iFmt->iFmt_VOP1);
9186  } // decode_OP_VOP1__V_MOV_B32
9187 
9188  GPUStaticInst*
9190  {
9191  return new Inst_VOP1__V_READFIRSTLANE_B32(&iFmt->iFmt_VOP1);
9192  } // decode_OP_VOP1__V_READFIRSTLANE_B32
9193 
9194  GPUStaticInst*
9196  {
9197  return new Inst_VOP1__V_CVT_I32_F64(&iFmt->iFmt_VOP1);
9198  } // decode_OP_VOP1__V_CVT_I32_F64
9199 
9200  GPUStaticInst*
9202  {
9203  return new Inst_VOP1__V_CVT_F64_I32(&iFmt->iFmt_VOP1);
9204  } // decode_OP_VOP1__V_CVT_F64_I32
9205 
9206  GPUStaticInst*
9208  {
9209  return new Inst_VOP1__V_CVT_F32_I32(&iFmt->iFmt_VOP1);
9210  } // decode_OP_VOP1__V_CVT_F32_I32
9211 
9212  GPUStaticInst*
9214  {
9215  return new Inst_VOP1__V_CVT_F32_U32(&iFmt->iFmt_VOP1);
9216  } // decode_OP_VOP1__V_CVT_F32_U32
9217 
9218  GPUStaticInst*
9220  {
9221  return new Inst_VOP1__V_CVT_U32_F32(&iFmt->iFmt_VOP1);
9222  } // decode_OP_VOP1__V_CVT_U32_F32
9223 
9224  GPUStaticInst*
9226  {
9227  return new Inst_VOP1__V_CVT_I32_F32(&iFmt->iFmt_VOP1);
9228  } // decode_OP_VOP1__V_CVT_I32_F32
9229 
9230  GPUStaticInst*
9232  {
9233  return new Inst_VOP1__V_MOV_FED_B32(&iFmt->iFmt_VOP1);
9234  } // decode_OP_VOP1__V_MOV_FED_B32
9235 
9236  GPUStaticInst*
9238  {
9239  return new Inst_VOP1__V_CVT_F16_F32(&iFmt->iFmt_VOP1);
9240  } // decode_OP_VOP1__V_CVT_F16_F32
9241 
9242  GPUStaticInst*
9244  {
9245  return new Inst_VOP1__V_CVT_F32_F16(&iFmt->iFmt_VOP1);
9246  } // decode_OP_VOP1__V_CVT_F32_F16
9247 
9248  GPUStaticInst*
9250  {
9251  return new Inst_VOP1__V_CVT_RPI_I32_F32(&iFmt->iFmt_VOP1);
9252  } // decode_OP_VOP1__V_CVT_RPI_I32_F32
9253 
9254  GPUStaticInst*
9256  {
9257  return new Inst_VOP1__V_CVT_FLR_I32_F32(&iFmt->iFmt_VOP1);
9258  } // decode_OP_VOP1__V_CVT_FLR_I32_F32
9259 
9260  GPUStaticInst*
9262  {
9263  return new Inst_VOP1__V_CVT_OFF_F32_I4(&iFmt->iFmt_VOP1);
9264  } // decode_OP_VOP1__V_CVT_OFF_F32_I4
9265 
9266  GPUStaticInst*
9268  {
9269  return new Inst_VOP1__V_CVT_F32_F64(&iFmt->iFmt_VOP1);
9270  } // decode_OP_VOP1__V_CVT_F32_F64
9271 
9272  GPUStaticInst*
9274  {
9275  return new Inst_VOP1__V_CVT_F64_F32(&iFmt->iFmt_VOP1);
9276  } // decode_OP_VOP1__V_CVT_F64_F32
9277 
9278  GPUStaticInst*
9280  {
9281  return new Inst_VOP1__V_CVT_F32_UBYTE0(&iFmt->iFmt_VOP1);
9282  } // decode_OP_VOP1__V_CVT_F32_UBYTE0
9283 
9284  GPUStaticInst*
9286  {
9287  return new Inst_VOP1__V_CVT_F32_UBYTE1(&iFmt->iFmt_VOP1);
9288  } // decode_OP_VOP1__V_CVT_F32_UBYTE1
9289 
9290  GPUStaticInst*
9292  {
9293  return new Inst_VOP1__V_CVT_F32_UBYTE2(&iFmt->iFmt_VOP1);
9294  } // decode_OP_VOP1__V_CVT_F32_UBYTE2
9295 
9296  GPUStaticInst*
9298  {
9299  return new Inst_VOP1__V_CVT_F32_UBYTE3(&iFmt->iFmt_VOP1);
9300  } // decode_OP_VOP1__V_CVT_F32_UBYTE3
9301 
9302  GPUStaticInst*
9304  {
9305  return new Inst_VOP1__V_CVT_U32_F64(&iFmt->iFmt_VOP1);
9306  } // decode_OP_VOP1__V_CVT_U32_F64
9307 
9308  GPUStaticInst*
9310  {
9311  return new Inst_VOP1__V_CVT_F64_U32(&iFmt->iFmt_VOP1);
9312  } // decode_OP_VOP1__V_CVT_F64_U32
9313 
9314  GPUStaticInst*
9316  {
9317  return new Inst_VOP1__V_TRUNC_F64(&iFmt->iFmt_VOP1);
9318  } // decode_OP_VOP1__V_TRUNC_F64
9319 
9320  GPUStaticInst*
9322  {
9323  return new Inst_VOP1__V_CEIL_F64(&iFmt->iFmt_VOP1);
9324  } // decode_OP_VOP1__V_CEIL_F64
9325 
9326  GPUStaticInst*
9328  {
9329  return new Inst_VOP1__V_RNDNE_F64(&iFmt->iFmt_VOP1);
9330  } // decode_OP_VOP1__V_RNDNE_F64
9331 
9332  GPUStaticInst*
9334  {
9335  return new Inst_VOP1__V_FLOOR_F64(&iFmt->iFmt_VOP1);
9336  } // decode_OP_VOP1__V_FLOOR_F64
9337 
9338  GPUStaticInst*
9340  {
9341  return new Inst_VOP1__V_FRACT_F32(&iFmt->iFmt_VOP1);
9342  } // decode_OP_VOP1__V_FRACT_F32
9343 
9344  GPUStaticInst*
9346  {
9347  return new Inst_VOP1__V_TRUNC_F32(&iFmt->iFmt_VOP1);
9348  } // decode_OP_VOP1__V_TRUNC_F32
9349 
9350  GPUStaticInst*
9352  {
9353  return new Inst_VOP1__V_CEIL_F32(&iFmt->iFmt_VOP1);
9354  } // decode_OP_VOP1__V_CEIL_F32
9355 
9356  GPUStaticInst*
9358  {
9359  return new Inst_VOP1__V_RNDNE_F32(&iFmt->iFmt_VOP1);
9360  } // decode_OP_VOP1__V_RNDNE_F32
9361 
9362  GPUStaticInst*
9364  {
9365  return new Inst_VOP1__V_FLOOR_F32(&iFmt->iFmt_VOP1);
9366  } // decode_OP_VOP1__V_FLOOR_F32
9367 
9368  GPUStaticInst*
9370  {
9371  return new Inst_VOP1__V_EXP_F32(&iFmt->iFmt_VOP1);
9372  } // decode_OP_VOP1__V_EXP_F32
9373 
9374  GPUStaticInst*
9376  {
9377  return new Inst_VOP1__V_LOG_F32(&iFmt->iFmt_VOP1);
9378  } // decode_OP_VOP1__V_LOG_F32
9379 
9380  GPUStaticInst*
9382  {
9383  return new Inst_VOP1__V_RCP_F32(&iFmt->iFmt_VOP1);
9384  } // decode_OP_VOP1__V_RCP_F32
9385 
9386  GPUStaticInst*
9388  {
9389  return new Inst_VOP1__V_RCP_IFLAG_F32(&iFmt->iFmt_VOP1);
9390  } // decode_OP_VOP1__V_RCP_IFLAG_F32
9391 
9392  GPUStaticInst*
9394  {
9395  return new Inst_VOP1__V_RSQ_F32(&iFmt->iFmt_VOP1);
9396  } // decode_OP_VOP1__V_RSQ_F32
9397 
9398  GPUStaticInst*
9400  {
9401  return new Inst_VOP1__V_RCP_F64(&iFmt->iFmt_VOP1);
9402  } // decode_OP_VOP1__V_RCP_F64
9403 
9404  GPUStaticInst*
9406  {
9407  return new Inst_VOP1__V_RSQ_F64(&iFmt->iFmt_VOP1);
9408  } // decode_OP_VOP1__V_RSQ_F64
9409 
9410  GPUStaticInst*
9412  {
9413  return new Inst_VOP1__V_SQRT_F32(&iFmt->iFmt_VOP1);
9414  } // decode_OP_VOP1__V_SQRT_F32
9415 
9416  GPUStaticInst*
9418  {
9419  return new Inst_VOP1__V_SQRT_F64(&iFmt->iFmt_VOP1);
9420  } // decode_OP_VOP1__V_SQRT_F64
9421 
9422  GPUStaticInst*
9424  {
9425  return new Inst_VOP1__V_SIN_F32(&iFmt->iFmt_VOP1);
9426  } // decode_OP_VOP1__V_SIN_F32
9427 
9428  GPUStaticInst*
9430  {
9431  return new Inst_VOP1__V_COS_F32(&iFmt->iFmt_VOP1);
9432  } // decode_OP_VOP1__V_COS_F32
9433 
9434  GPUStaticInst*
9436  {
9437  return new Inst_VOP1__V_NOT_B32(&iFmt->iFmt_VOP1);
9438  } // decode_OP_VOP1__V_NOT_B32
9439 
9440  GPUStaticInst*
9442  {
9443  return new Inst_VOP1__V_BFREV_B32(&iFmt->iFmt_VOP1);
9444  } // decode_OP_VOP1__V_BFREV_B32
9445 
9446  GPUStaticInst*
9448  {
9449  return new Inst_VOP1__V_FFBH_U32(&iFmt->iFmt_VOP1);
9450  } // decode_OP_VOP1__V_FFBH_U32
9451 
9452  GPUStaticInst*
9454  {
9455  return new Inst_VOP1__V_FFBL_B32(&iFmt->iFmt_VOP1);
9456  } // decode_OP_VOP1__V_FFBL_B32
9457 
9458  GPUStaticInst*
9460  {
9461  return new Inst_VOP1__V_FFBH_I32(&iFmt->iFmt_VOP1);
9462  } // decode_OP_VOP1__V_FFBH_I32
9463 
9464  GPUStaticInst*
9466  {
9467  return new Inst_VOP1__V_FREXP_EXP_I32_F64(&iFmt->iFmt_VOP1);
9468  } // decode_OP_VOP1__V_FREXP_EXP_I32_F64
9469 
9470  GPUStaticInst*
9472  {
9473  return new Inst_VOP1__V_FREXP_MANT_F64(&iFmt->iFmt_VOP1);
9474  } // decode_OP_VOP1__V_FREXP_MANT_F64
9475 
9476  GPUStaticInst*
9478  {
9479  return new Inst_VOP1__V_FRACT_F64(&iFmt->iFmt_VOP1);
9480  } // decode_OP_VOP1__V_FRACT_F64
9481 
9482  GPUStaticInst*
9484  {
9485  return new Inst_VOP1__V_FREXP_EXP_I32_F32(&iFmt->iFmt_VOP1);
9486  } // decode_OP_VOP1__V_FREXP_EXP_I32_F32
9487 
9488  GPUStaticInst*
9490  {
9491  return new Inst_VOP1__V_FREXP_MANT_F32(&iFmt->iFmt_VOP1);
9492  } // decode_OP_VOP1__V_FREXP_MANT_F32
9493 
9494  GPUStaticInst*
9496  {
9497  return new Inst_VOP1__V_CLREXCP(&iFmt->iFmt_VOP1);
9498  } // decode_OP_VOP1__V_CLREXCP
9499 
9500  GPUStaticInst*
9502  {
9503  return new Inst_VOP1__V_CVT_F16_U16(&iFmt->iFmt_VOP1);
9504  } // decode_OP_VOP1__V_CVT_F16_U16
9505 
9506  GPUStaticInst*
9508  {
9509  return new Inst_VOP1__V_CVT_F16_I16(&iFmt->iFmt_VOP1);
9510  } // decode_OP_VOP1__V_CVT_F16_I16
9511 
9512  GPUStaticInst*
9514  {
9515  return new Inst_VOP1__V_CVT_U16_F16(&iFmt->iFmt_VOP1);
9516  } // decode_OP_VOP1__V_CVT_U16_F16
9517 
9518  GPUStaticInst*
9520  {
9521  return new Inst_VOP1__V_CVT_I16_F16(&iFmt->iFmt_VOP1);
9522  } // decode_OP_VOP1__V_CVT_I16_F16
9523 
9524  GPUStaticInst*
9526  {
9527  return new Inst_VOP1__V_RCP_F16(&iFmt->iFmt_VOP1);
9528  } // decode_OP_VOP1__V_RCP_F16
9529 
9530  GPUStaticInst*
9532  {
9533  return new Inst_VOP1__V_SQRT_F16(&iFmt->iFmt_VOP1);
9534  } // decode_OP_VOP1__V_SQRT_F16
9535 
9536  GPUStaticInst*
9538  {
9539  return new Inst_VOP1__V_RSQ_F16(&iFmt->iFmt_VOP1);
9540  } // decode_OP_VOP1__V_RSQ_F16
9541 
9542  GPUStaticInst*
9544  {
9545  return new Inst_VOP1__V_LOG_F16(&iFmt->iFmt_VOP1);
9546  } // decode_OP_VOP1__V_LOG_F16
9547 
9548  GPUStaticInst*
9550  {
9551  return new Inst_VOP1__V_EXP_F16(&iFmt->iFmt_VOP1);
9552  } // decode_OP_VOP1__V_EXP_F16
9553 
9554  GPUStaticInst*
9556  {
9557  return new Inst_VOP1__V_FREXP_MANT_F16(&iFmt->iFmt_VOP1);
9558  } // decode_OP_VOP1__V_FREXP_MANT_F16
9559 
9560  GPUStaticInst*
9562  {
9563  return new Inst_VOP1__V_FREXP_EXP_I16_F16(&iFmt->iFmt_VOP1);
9564  } // decode_OP_VOP1__V_FREXP_EXP_I16_F16
9565 
9566  GPUStaticInst*
9568  {
9569  return new Inst_VOP1__V_FLOOR_F16(&iFmt->iFmt_VOP1);
9570  } // decode_OP_VOP1__V_FLOOR_F16
9571 
9572  GPUStaticInst*
9574  {
9575  return new Inst_VOP1__V_CEIL_F16(&iFmt->iFmt_VOP1);
9576  } // decode_OP_VOP1__V_CEIL_F16
9577 
9578  GPUStaticInst*
9580  {
9581  return new Inst_VOP1__V_TRUNC_F16(&iFmt->iFmt_VOP1);
9582  } // decode_OP_VOP1__V_TRUNC_F16
9583 
9584  GPUStaticInst*
9586  {
9587  return new Inst_VOP1__V_RNDNE_F16(&iFmt->iFmt_VOP1);
9588  } // decode_OP_VOP1__V_RNDNE_F16
9589 
9590  GPUStaticInst*
9592  {
9593  return new Inst_VOP1__V_FRACT_F16(&iFmt->iFmt_VOP1);
9594  } // decode_OP_VOP1__V_FRACT_F16
9595 
9596  GPUStaticInst*
9598  {
9599  return new Inst_VOP1__V_SIN_F16(&iFmt->iFmt_VOP1);
9600  } // decode_OP_VOP1__V_SIN_F16
9601 
9602  GPUStaticInst*
9604  {
9605  return new Inst_VOP1__V_COS_F16(&iFmt->iFmt_VOP1);
9606  } // decode_OP_VOP1__V_COS_F16
9607 
9608  GPUStaticInst*
9610  {
9611  return new Inst_VOP1__V_EXP_LEGACY_F32(&iFmt->iFmt_VOP1);
9612  } // decode_OP_VOP1__V_EXP_LEGACY_F32
9613 
9614  GPUStaticInst*
9616  {
9617  return new Inst_VOP1__V_LOG_LEGACY_F32(&iFmt->iFmt_VOP1);
9618  } // decode_OP_VOP1__V_LOG_LEGACY_F32
9619 
9620  GPUStaticInst*
9622  {
9623  return new Inst_VOPC__V_CMP_CLASS_F32(&iFmt->iFmt_VOPC);
9624  } // decode_OP_VOPC__V_CMP_CLASS_F32
9625 
9626  GPUStaticInst*
9628  {
9629  return new Inst_VOPC__V_CMPX_CLASS_F32(&iFmt->iFmt_VOPC);
9630  } // decode_OP_VOPC__V_CMPX_CLASS_F32
9631 
9632  GPUStaticInst*
9634  {
9635  return new Inst_VOPC__V_CMP_CLASS_F64(&iFmt->iFmt_VOPC);
9636  } // decode_OP_VOPC__V_CMP_CLASS_F64
9637 
9638  GPUStaticInst*
9640  {
9641  return new Inst_VOPC__V_CMPX_CLASS_F64(&iFmt->iFmt_VOPC);
9642  } // decode_OP_VOPC__V_CMPX_CLASS_F64
9643 
9644  GPUStaticInst*
9646  {
9647  return new Inst_VOPC__V_CMP_CLASS_F16(&iFmt->iFmt_VOPC);
9648  } // decode_OP_VOPC__V_CMP_CLASS_F16
9649 
9650  GPUStaticInst*
9652  {
9653  return new Inst_VOPC__V_CMPX_CLASS_F16(&iFmt->iFmt_VOPC);
9654  } // decode_OP_VOPC__V_CMPX_CLASS_F16
9655 
9656  GPUStaticInst*
9658  {
9659  return new Inst_VOPC__V_CMP_F_F16(&iFmt->iFmt_VOPC);
9660  } // decode_OP_VOPC__V_CMP_F_F16
9661 
9662  GPUStaticInst*
9664  {
9665  return new Inst_VOPC__V_CMP_LT_F16(&iFmt->iFmt_VOPC);
9666  } // decode_OP_VOPC__V_CMP_LT_F16
9667 
9668  GPUStaticInst*
9670  {
9671  return new Inst_VOPC__V_CMP_EQ_F16(&iFmt->iFmt_VOPC);
9672  } // decode_OP_VOPC__V_CMP_EQ_F16
9673 
9674  GPUStaticInst*
9676  {
9677  return new Inst_VOPC__V_CMP_LE_F16(&iFmt->iFmt_VOPC);
9678  } // decode_OP_VOPC__V_CMP_LE_F16
9679 
9680  GPUStaticInst*
9682  {
9683  return new Inst_VOPC__V_CMP_GT_F16(&iFmt->iFmt_VOPC);
9684  } // decode_OP_VOPC__V_CMP_GT_F16
9685 
9686  GPUStaticInst*
9688  {
9689  return new Inst_VOPC__V_CMP_LG_F16(&iFmt->iFmt_VOPC);
9690  } // decode_OP_VOPC__V_CMP_LG_F16
9691 
9692  GPUStaticInst*
9694  {
9695  return new Inst_VOPC__V_CMP_GE_F16(&iFmt->iFmt_VOPC);
9696  } // decode_OP_VOPC__V_CMP_GE_F16
9697 
9698  GPUStaticInst*
9700  {
9701  return new Inst_VOPC__V_CMP_O_F16(&iFmt->iFmt_VOPC);
9702  } // decode_OP_VOPC__V_CMP_O_F16
9703 
9704  GPUStaticInst*
9706  {
9707  return new Inst_VOPC__V_CMP_U_F16(&iFmt->iFmt_VOPC);
9708  } // decode_OP_VOPC__V_CMP_U_F16
9709 
9710  GPUStaticInst*
9712  {
9713  return new Inst_VOPC__V_CMP_NGE_F16(&iFmt->iFmt_VOPC);
9714  } // decode_OP_VOPC__V_CMP_NGE_F16
9715 
9716  GPUStaticInst*
9718  {
9719  return new Inst_VOPC__V_CMP_NLG_F16(&iFmt->iFmt_VOPC);
9720  } // decode_OP_VOPC__V_CMP_NLG_F16
9721 
9722  GPUStaticInst*
9724  {
9725  return new Inst_VOPC__V_CMP_NGT_F16(&iFmt->iFmt_VOPC);
9726  } // decode_OP_VOPC__V_CMP_NGT_F16
9727 
9728  GPUStaticInst*
9730  {
9731  return new Inst_VOPC__V_CMP_NLE_F16(&iFmt->iFmt_VOPC);
9732  } // decode_OP_VOPC__V_CMP_NLE_F16
9733 
9734  GPUStaticInst*
9736  {
9737  return new Inst_VOPC__V_CMP_NEQ_F16(&iFmt->iFmt_VOPC);
9738  } // decode_OP_VOPC__V_CMP_NEQ_F16
9739 
9740  GPUStaticInst*
9742  {
9743  return new Inst_VOPC__V_CMP_NLT_F16(&iFmt->iFmt_VOPC);
9744  } // decode_OP_VOPC__V_CMP_NLT_F16
9745 
9746  GPUStaticInst*
9748  {
9749  return new Inst_VOPC__V_CMP_TRU_F16(&iFmt->iFmt_VOPC);
9750  } // decode_OP_VOPC__V_CMP_TRU_F16
9751 
9752  GPUStaticInst*
9754  {
9755  return new Inst_VOPC__V_CMPX_F_F16(&iFmt->iFmt_VOPC);
9756  } // decode_OP_VOPC__V_CMPX_F_F16
9757 
9758  GPUStaticInst*
9760  {
9761  return new Inst_VOPC__V_CMPX_LT_F16(&iFmt->iFmt_VOPC);
9762  } // decode_OP_VOPC__V_CMPX_LT_F16
9763 
9764  GPUStaticInst*
9766  {
9767  return new Inst_VOPC__V_CMPX_EQ_F16(&iFmt->iFmt_VOPC);
9768  } // decode_OP_VOPC__V_CMPX_EQ_F16
9769 
9770  GPUStaticInst*
9772  {
9773  return new Inst_VOPC__V_CMPX_LE_F16(&iFmt->iFmt_VOPC);
9774  } // decode_OP_VOPC__V_CMPX_LE_F16
9775 
9776  GPUStaticInst*
9778  {
9779  return new Inst_VOPC__V_CMPX_GT_F16(&iFmt->iFmt_VOPC);
9780  } // decode_OP_VOPC__V_CMPX_GT_F16
9781 
9782  GPUStaticInst*
9784  {
9785  return new Inst_VOPC__V_CMPX_LG_F16(&iFmt->iFmt_VOPC);
9786  } // decode_OP_VOPC__V_CMPX_LG_F16
9787 
9788  GPUStaticInst*
9790  {
9791  return new Inst_VOPC__V_CMPX_GE_F16(&iFmt->iFmt_VOPC);
9792  } // decode_OP_VOPC__V_CMPX_GE_F16
9793 
9794  GPUStaticInst*
9796  {
9797  return new Inst_VOPC__V_CMPX_O_F16(&iFmt->iFmt_VOPC);
9798  } // decode_OP_VOPC__V_CMPX_O_F16
9799 
9800  GPUStaticInst*
9802  {
9803  return new Inst_VOPC__V_CMPX_U_F16(&iFmt->iFmt_VOPC);
9804  } // decode_OP_VOPC__V_CMPX_U_F16
9805 
9806  GPUStaticInst*
9808  {
9809  return new Inst_VOPC__V_CMPX_NGE_F16(&iFmt->iFmt_VOPC);
9810  } // decode_OP_VOPC__V_CMPX_NGE_F16
9811 
9812  GPUStaticInst*
9814  {
9815  return new Inst_VOPC__V_CMPX_NLG_F16(&iFmt->iFmt_VOPC);
9816  } // decode_OP_VOPC__V_CMPX_NLG_F16
9817 
9818  GPUStaticInst*
9820  {
9821  return new Inst_VOPC__V_CMPX_NGT_F16(&iFmt->iFmt_VOPC);
9822  } // decode_OP_VOPC__V_CMPX_NGT_F16
9823 
9824  GPUStaticInst*
9826  {
9827  return new Inst_VOPC__V_CMPX_NLE_F16(&iFmt->iFmt_VOPC);
9828  } // decode_OP_VOPC__V_CMPX_NLE_F16
9829 
9830  GPUStaticInst*
9832  {
9833  return new Inst_VOPC__V_CMPX_NEQ_F16(&iFmt->iFmt_VOPC);
9834  } // decode_OP_VOPC__V_CMPX_NEQ_F16
9835 
9836  GPUStaticInst*
9838  {
9839  return new Inst_VOPC__V_CMPX_NLT_F16(&iFmt->iFmt_VOPC);
9840  } // decode_OP_VOPC__V_CMPX_NLT_F16
9841 
9842  GPUStaticInst*
9844  {
9845  return new Inst_VOPC__V_CMPX_TRU_F16(&iFmt->iFmt_VOPC);
9846  } // decode_OP_VOPC__V_CMPX_TRU_F16
9847 
9848  GPUStaticInst*
9850  {
9851  return new Inst_VOPC__V_CMP_F_F32(&iFmt->iFmt_VOPC);
9852  } // decode_OP_VOPC__V_CMP_F_F32
9853 
9854  GPUStaticInst*
9856  {
9857  return new Inst_VOPC__V_CMP_LT_F32(&iFmt->iFmt_VOPC);
9858  } // decode_OP_VOPC__V_CMP_LT_F32
9859 
9860  GPUStaticInst*
9862  {
9863  return new Inst_VOPC__V_CMP_EQ_F32(&iFmt->iFmt_VOPC);
9864  } // decode_OP_VOPC__V_CMP_EQ_F32
9865 
9866  GPUStaticInst*
9868  {
9869  return new Inst_VOPC__V_CMP_LE_F32(&iFmt->iFmt_VOPC);
9870  } // decode_OP_VOPC__V_CMP_LE_F32
9871 
9872  GPUStaticInst*
9874  {
9875  return new Inst_VOPC__V_CMP_GT_F32(&iFmt->iFmt_VOPC);
9876  } // decode_OP_VOPC__V_CMP_GT_F32
9877 
9878  GPUStaticInst*
9880  {
9881  return new Inst_VOPC__V_CMP_LG_F32(&iFmt->iFmt_VOPC);
9882  } // decode_OP_VOPC__V_CMP_LG_F32
9883 
9884  GPUStaticInst*
9886  {
9887  return new Inst_VOPC__V_CMP_GE_F32(&iFmt->iFmt_VOPC);
9888  } // decode_OP_VOPC__V_CMP_GE_F32
9889 
9890  GPUStaticInst*
9892  {
9893  return new Inst_VOPC__V_CMP_O_F32(&iFmt->iFmt_VOPC);
9894  } // decode_OP_VOPC__V_CMP_O_F32
9895 
9896  GPUStaticInst*
9898  {
9899  return new Inst_VOPC__V_CMP_U_F32(&iFmt->iFmt_VOPC);
9900  } // decode_OP_VOPC__V_CMP_U_F32
9901 
9902  GPUStaticInst*
9904  {
9905  return new Inst_VOPC__V_CMP_NGE_F32(&iFmt->iFmt_VOPC);
9906  } // decode_OP_VOPC__V_CMP_NGE_F32
9907 
9908  GPUStaticInst*
9910  {
9911  return new Inst_VOPC__V_CMP_NLG_F32(&iFmt->iFmt_VOPC);
9912  } // decode_OP_VOPC__V_CMP_NLG_F32
9913 
9914  GPUStaticInst*
9916  {
9917  return new Inst_VOPC__V_CMP_NGT_F32(&iFmt->iFmt_VOPC);
9918  } // decode_OP_VOPC__V_CMP_NGT_F32
9919 
9920  GPUStaticInst*
9922  {
9923  return new Inst_VOPC__V_CMP_NLE_F32(&iFmt->iFmt_VOPC);
9924  } // decode_OP_VOPC__V_CMP_NLE_F32
9925 
9926  GPUStaticInst*
9928  {
9929  return new Inst_VOPC__V_CMP_NEQ_F32(&iFmt->iFmt_VOPC);
9930  } // decode_OP_VOPC__V_CMP_NEQ_F32
9931 
9932  GPUStaticInst*
9934  {
9935  return new Inst_VOPC__V_CMP_NLT_F32(&iFmt->iFmt_VOPC);
9936  } // decode_OP_VOPC__V_CMP_NLT_F32
9937 
9938  GPUStaticInst*
9940  {
9941  return new Inst_VOPC__V_CMP_TRU_F32(&iFmt->iFmt_VOPC);
9942  } // decode_OP_VOPC__V_CMP_TRU_F32
9943 
9944  GPUStaticInst*
9946  {
9947  return new Inst_VOPC__V_CMPX_F_F32(&iFmt->iFmt_VOPC);
9948  } // decode_OP_VOPC__V_CMPX_F_F32
9949 
9950  GPUStaticInst*
9952  {
9953  return new Inst_VOPC__V_CMPX_LT_F32(&iFmt->iFmt_VOPC);
9954  } // decode_OP_VOPC__V_CMPX_LT_F32
9955 
9956  GPUStaticInst*
9958  {
9959  return new Inst_VOPC__V_CMPX_EQ_F32(&iFmt->iFmt_VOPC);
9960  } // decode_OP_VOPC__V_CMPX_EQ_F32
9961 
9962  GPUStaticInst*
9964  {
9965  return new Inst_VOPC__V_CMPX_LE_F32(&iFmt->iFmt_VOPC);
9966  } // decode_OP_VOPC__V_CMPX_LE_F32
9967 
9968  GPUStaticInst*
9970  {
9971  return new Inst_VOPC__V_CMPX_GT_F32(&iFmt->iFmt_VOPC);
9972  } // decode_OP_VOPC__V_CMPX_GT_F32
9973 
9974  GPUStaticInst*
9976  {
9977  return new Inst_VOPC__V_CMPX_LG_F32(&iFmt->iFmt_VOPC);
9978  } // decode_OP_VOPC__V_CMPX_LG_F32
9979 
9980  GPUStaticInst*
9982  {
9983  return new Inst_VOPC__V_CMPX_GE_F32(&iFmt->iFmt_VOPC);
9984  } // decode_OP_VOPC__V_CMPX_GE_F32
9985 
9986  GPUStaticInst*
9988  {
9989  return new Inst_VOPC__V_CMPX_O_F32(&iFmt->iFmt_VOPC);
9990  } // decode_OP_VOPC__V_CMPX_O_F32
9991 
9992  GPUStaticInst*
9994  {
9995  return new Inst_VOPC__V_CMPX_U_F32(&iFmt->iFmt_VOPC);
9996  } // decode_OP_VOPC__V_CMPX_U_F32
9997 
9998  GPUStaticInst*
10000  {
10001  return new Inst_VOPC__V_CMPX_NGE_F32(&iFmt->iFmt_VOPC);
10002  } // decode_OP_VOPC__V_CMPX_NGE_F32
10003 
10004  GPUStaticInst*
10006  {
10007  return new Inst_VOPC__V_CMPX_NLG_F32(&iFmt->iFmt_VOPC);
10008  } // decode_OP_VOPC__V_CMPX_NLG_F32
10009 
10010  GPUStaticInst*
10012  {
10013  return new Inst_VOPC__V_CMPX_NGT_F32(&iFmt->iFmt_VOPC);
10014  } // decode_OP_VOPC__V_CMPX_NGT_F32
10015 
10016  GPUStaticInst*
10018  {
10019  return new Inst_VOPC__V_CMPX_NLE_F32(&iFmt->iFmt_VOPC);
10020  } // decode_OP_VOPC__V_CMPX_NLE_F32
10021 
10022  GPUStaticInst*
10024  {
10025  return new Inst_VOPC__V_CMPX_NEQ_F32(&iFmt->iFmt_VOPC);
10026  } // decode_OP_VOPC__V_CMPX_NEQ_F32
10027 
10028  GPUStaticInst*
10030  {
10031  return new Inst_VOPC__V_CMPX_NLT_F32(&iFmt->iFmt_VOPC);
10032  } // decode_OP_VOPC__V_CMPX_NLT_F32
10033 
10034  GPUStaticInst*
10036  {
10037  return new Inst_VOPC__V_CMPX_TRU_F32(&iFmt->iFmt_VOPC);
10038  } // decode_OP_VOPC__V_CMPX_TRU_F32
10039 
10040  GPUStaticInst*
10042  {
10043  return new Inst_VOPC__V_CMP_F_F64(&iFmt->iFmt_VOPC);
10044  } // decode_OP_VOPC__V_CMP_F_F64
10045 
10046  GPUStaticInst*
10048  {
10049  return new Inst_VOPC__V_CMP_LT_F64(&iFmt->iFmt_VOPC);
10050  } // decode_OP_VOPC__V_CMP_LT_F64
10051 
10052  GPUStaticInst*
10054  {
10055  return new Inst_VOPC__V_CMP_EQ_F64(&iFmt->iFmt_VOPC);
10056  } // decode_OP_VOPC__V_CMP_EQ_F64
10057 
10058  GPUStaticInst*
10060  {
10061  return new Inst_VOPC__V_CMP_LE_F64(&iFmt->iFmt_VOPC);
10062  } // decode_OP_VOPC__V_CMP_LE_F64
10063 
10064  GPUStaticInst*
10066  {
10067  return new Inst_VOPC__V_CMP_GT_F64(&iFmt->iFmt_VOPC);
10068  } // decode_OP_VOPC__V_CMP_GT_F64
10069 
10070  GPUStaticInst*
10072  {
10073  return new Inst_VOPC__V_CMP_LG_F64(&iFmt->iFmt_VOPC);
10074  } // decode_OP_VOPC__V_CMP_LG_F64
10075 
10076  GPUStaticInst*
10078  {
10079  return new Inst_VOPC__V_CMP_GE_F64(&iFmt->iFmt_VOPC);
10080  } // decode_OP_VOPC__V_CMP_GE_F64
10081 
10082  GPUStaticInst*
10084  {
10085  return new Inst_VOPC__V_CMP_O_F64(&iFmt->iFmt_VOPC);
10086  } // decode_OP_VOPC__V_CMP_O_F64
10087 
10088  GPUStaticInst*
10090  {
10091  return new Inst_VOPC__V_CMP_U_F64(&iFmt->iFmt_VOPC);
10092  } // decode_OP_VOPC__V_CMP_U_F64
10093 
10094  GPUStaticInst*
10096  {
10097  return new Inst_VOPC__V_CMP_NGE_F64(&iFmt->iFmt_VOPC);
10098  } // decode_OP_VOPC__V_CMP_NGE_F64
10099 
10100  GPUStaticInst*
10102  {
10103  return new Inst_VOPC__V_CMP_NLG_F64(&iFmt->iFmt_VOPC);
10104  } // decode_OP_VOPC__V_CMP_NLG_F64
10105 
10106  GPUStaticInst*
10108  {
10109  return new Inst_VOPC__V_CMP_NGT_F64(&iFmt->iFmt_VOPC);
10110  } // decode_OP_VOPC__V_CMP_NGT_F64
10111 
10112  GPUStaticInst*
10114  {
10115  return new Inst_VOPC__V_CMP_NLE_F64(&iFmt->iFmt_VOPC);
10116  } // decode_OP_VOPC__V_CMP_NLE_F64
10117 
10118  GPUStaticInst*
10120  {
10121  return new Inst_VOPC__V_CMP_NEQ_F64(&iFmt->iFmt_VOPC);
10122  } // decode_OP_VOPC__V_CMP_NEQ_F64
10123 
10124  GPUStaticInst*
10126  {
10127  return new Inst_VOPC__V_CMP_NLT_F64(&iFmt->iFmt_VOPC);
10128  } // decode_OP_VOPC__V_CMP_NLT_F64
10129 
10130  GPUStaticInst*
10132  {
10133  return new Inst_VOPC__V_CMP_TRU_F64(&iFmt->iFmt_VOPC);
10134  } // decode_OP_VOPC__V_CMP_TRU_F64
10135 
10136  GPUStaticInst*
10138  {
10139  return new Inst_VOPC__V_CMPX_F_F64(&iFmt->iFmt_VOPC);
10140  } // decode_OP_VOPC__V_CMPX_F_F64
10141 
10142  GPUStaticInst*
10144  {
10145  return new Inst_VOPC__V_CMPX_LT_F64(&iFmt->iFmt_VOPC);
10146  } // decode_OP_VOPC__V_CMPX_LT_F64
10147 
10148  GPUStaticInst*
10150  {
10151  return new Inst_VOPC__V_CMPX_EQ_F64(&iFmt->iFmt_VOPC);
10152  } // decode_OP_VOPC__V_CMPX_EQ_F64
10153 
10154  GPUStaticInst*
10156  {
10157  return new Inst_VOPC__V_CMPX_LE_F64(&iFmt->iFmt_VOPC);
10158  } // decode_OP_VOPC__V_CMPX_LE_F64
10159 
10160  GPUStaticInst*
10162  {
10163  return new Inst_VOPC__V_CMPX_GT_F64(&iFmt->iFmt_VOPC);
10164  } // decode_OP_VOPC__V_CMPX_GT_F64
10165 
10166  GPUStaticInst*
10168  {
10169  return new Inst_VOPC__V_CMPX_LG_F64(&iFmt->iFmt_VOPC);
10170  } // decode_OP_VOPC__V_CMPX_LG_F64
10171 
10172  GPUStaticInst*
10174  {
10175  return new Inst_VOPC__V_CMPX_GE_F64(&iFmt->iFmt_VOPC);
10176  } // decode_OP_VOPC__V_CMPX_GE_F64
10177 
10178  GPUStaticInst*
10180  {
10181  return new Inst_VOPC__V_CMPX_O_F64(&iFmt->iFmt_VOPC);
10182  } // decode_OP_VOPC__V_CMPX_O_F64
10183 
10184  GPUStaticInst*
10186  {
10187  return new Inst_VOPC__V_CMPX_U_F64(&iFmt->iFmt_VOPC);
10188  } // decode_OP_VOPC__V_CMPX_U_F64
10189 
10190  GPUStaticInst*
10192  {
10193  return new Inst_VOPC__V_CMPX_NGE_F64(&iFmt->iFmt_VOPC);
10194  } // decode_OP_VOPC__V_CMPX_NGE_F64
10195 
10196  GPUStaticInst*
10198  {
10199  return new Inst_VOPC__V_CMPX_NLG_F64(&iFmt->iFmt_VOPC);
10200  } // decode_OP_VOPC__V_CMPX_NLG_F64
10201 
10202  GPUStaticInst*
10204  {
10205  return new Inst_VOPC__V_CMPX_NGT_F64(&iFmt->iFmt_VOPC);
10206  } // decode_OP_VOPC__V_CMPX_NGT_F64
10207 
10208  GPUStaticInst*
10210  {
10211  return new Inst_VOPC__V_CMPX_NLE_F64(&iFmt->iFmt_VOPC);
10212  } // decode_OP_VOPC__V_CMPX_NLE_F64
10213 
10214  GPUStaticInst*
10216  {
10217  return new Inst_VOPC__V_CMPX_NEQ_F64(&iFmt->iFmt_VOPC);
10218  } // decode_OP_VOPC__V_CMPX_NEQ_F64
10219 
10220  GPUStaticInst*
10222  {
10223  return new Inst_VOPC__V_CMPX_NLT_F64(&iFmt->iFmt_VOPC);
10224  } // decode_OP_VOPC__V_CMPX_NLT_F64
10225 
10226  GPUStaticInst*
10228  {
10229  return new Inst_VOPC__V_CMPX_TRU_F64(&iFmt->iFmt_VOPC);
10230  } // decode_OP_VOPC__V_CMPX_TRU_F64
10231 
10232  GPUStaticInst*
10234  {
10235  return new Inst_VOPC__V_CMP_F_I16(&iFmt->iFmt_VOPC);
10236  } // decode_OP_VOPC__V_CMP_F_I16
10237 
10238  GPUStaticInst*
10240  {
10241  return new Inst_VOPC__V_CMP_LT_I16(&iFmt->iFmt_VOPC);
10242  } // decode_OP_VOPC__V_CMP_LT_I16
10243 
10244  GPUStaticInst*
10246  {
10247  return new Inst_VOPC__V_CMP_EQ_I16(&iFmt->iFmt_VOPC);
10248  } // decode_OP_VOPC__V_CMP_EQ_I16
10249 
10250  GPUStaticInst*
10252  {
10253  return new Inst_VOPC__V_CMP_LE_I16(&iFmt->iFmt_VOPC);
10254  } // decode_OP_VOPC__V_CMP_LE_I16
10255 
10256  GPUStaticInst*
10258  {
10259  return new Inst_VOPC__V_CMP_GT_I16(&iFmt->iFmt_VOPC);
10260  } // decode_OP_VOPC__V_CMP_GT_I16
10261 
10262  GPUStaticInst*
10264  {
10265  return new Inst_VOPC__V_CMP_NE_I16(&iFmt->iFmt_VOPC);
10266  } // decode_OP_VOPC__V_CMP_NE_I16
10267 
10268  GPUStaticInst*
10270  {
10271  return new Inst_VOPC__V_CMP_GE_I16(&iFmt->iFmt_VOPC);
10272  } // decode_OP_VOPC__V_CMP_GE_I16
10273 
10274  GPUStaticInst*
10276  {
10277  return new Inst_VOPC__V_CMP_T_I16(&iFmt->iFmt_VOPC);
10278  } // decode_OP_VOPC__V_CMP_T_I16
10279 
10280  GPUStaticInst*
10282  {
10283  return new Inst_VOPC__V_CMP_F_U16(&iFmt->iFmt_VOPC);
10284  } // decode_OP_VOPC__V_CMP_F_U16
10285 
10286  GPUStaticInst*
10288  {
10289  return new Inst_VOPC__V_CMP_LT_U16(&iFmt->iFmt_VOPC);
10290  } // decode_OP_VOPC__V_CMP_LT_U16
10291 
10292  GPUStaticInst*
10294  {
10295  return new Inst_VOPC__V_CMP_EQ_U16(&iFmt->iFmt_VOPC);
10296  } // decode_OP_VOPC__V_CMP_EQ_U16
10297 
10298  GPUStaticInst*
10300  {
10301  return new Inst_VOPC__V_CMP_LE_U16(&iFmt->iFmt_VOPC);
10302  } // decode_OP_VOPC__V_CMP_LE_U16
10303 
10304  GPUStaticInst*
10306  {
10307  return new Inst_VOPC__V_CMP_GT_U16(&iFmt->iFmt_VOPC);
10308  } // decode_OP_VOPC__V_CMP_GT_U16
10309 
10310  GPUStaticInst*
10312  {
10313  return new Inst_VOPC__V_CMP_NE_U16(&iFmt->iFmt_VOPC);
10314  } // decode_OP_VOPC__V_CMP_NE_U16
10315 
10316  GPUStaticInst*
10318  {
10319  return new Inst_VOPC__V_CMP_GE_U16(&iFmt->iFmt_VOPC);
10320  } // decode_OP_VOPC__V_CMP_GE_U16
10321 
10322  GPUStaticInst*
10324  {
10325  return new Inst_VOPC__V_CMP_T_U16(&iFmt->iFmt_VOPC);
10326  } // decode_OP_VOPC__V_CMP_T_U16
10327 
10328  GPUStaticInst*
10330  {
10331  return new Inst_VOPC__V_CMPX_F_I16(&iFmt->iFmt_VOPC);
10332  } // decode_OP_VOPC__V_CMPX_F_I16
10333 
10334  GPUStaticInst*
10336  {
10337  return new Inst_VOPC__V_CMPX_LT_I16(&iFmt->iFmt_VOPC);
10338  } // decode_OP_VOPC__V_CMPX_LT_I16
10339 
10340  GPUStaticInst*
10342  {
10343  return new Inst_VOPC__V_CMPX_EQ_I16(&iFmt->iFmt_VOPC);
10344  } // decode_OP_VOPC__V_CMPX_EQ_I16
10345 
10346  GPUStaticInst*
10348  {
10349  return new Inst_VOPC__V_CMPX_LE_I16(&iFmt->iFmt_VOPC);
10350  } // decode_OP_VOPC__V_CMPX_LE_I16
10351 
10352  GPUStaticInst*
10354  {
10355  return new Inst_VOPC__V_CMPX_GT_I16(&iFmt->iFmt_VOPC);
10356  } // decode_OP_VOPC__V_CMPX_GT_I16
10357 
10358  GPUStaticInst*
10360  {
10361  return new Inst_VOPC__V_CMPX_NE_I16(&iFmt->iFmt_VOPC);
10362  } // decode_OP_VOPC__V_CMPX_NE_I16
10363 
10364  GPUStaticInst*
10366  {
10367  return new Inst_VOPC__V_CMPX_GE_I16(&iFmt->iFmt_VOPC);
10368  } // decode_OP_VOPC__V_CMPX_GE_I16
10369 
10370  GPUStaticInst*
10372  {
10373  return new Inst_VOPC__V_CMPX_T_I16(&iFmt->iFmt_VOPC);
10374  } // decode_OP_VOPC__V_CMPX_T_I16
10375 
10376  GPUStaticInst*
10378  {
10379  return new Inst_VOPC__V_CMPX_F_U16(&iFmt->iFmt_VOPC);
10380  } // decode_OP_VOPC__V_CMPX_F_U16
10381 
10382  GPUStaticInst*
10384  {
10385  return new Inst_VOPC__V_CMPX_LT_U16(&iFmt->iFmt_VOPC);
10386  } // decode_OP_VOPC__V_CMPX_LT_U16
10387 
10388  GPUStaticInst*
10390  {
10391  return new Inst_VOPC__V_CMPX_EQ_U16(&iFmt->iFmt_VOPC);
10392  } // decode_OP_VOPC__V_CMPX_EQ_U16
10393 
10394  GPUStaticInst*
10396  {
10397  return new Inst_VOPC__V_CMPX_LE_U16(&iFmt->iFmt_VOPC);
10398  } // decode_OP_VOPC__V_CMPX_LE_U16
10399 
10400  GPUStaticInst*
10402  {
10403  return new Inst_VOPC__V_CMPX_GT_U16(&iFmt->iFmt_VOPC);
10404  } // decode_OP_VOPC__V_CMPX_GT_U16
10405 
10406  GPUStaticInst*
10408  {
10409  return new Inst_VOPC__V_CMPX_NE_U16(&iFmt->iFmt_VOPC);
10410  } // decode_OP_VOPC__V_CMPX_NE_U16
10411 
10412  GPUStaticInst*
10414  {
10415  return new Inst_VOPC__V_CMPX_GE_U16(&iFmt->iFmt_VOPC);
10416  } // decode_OP_VOPC__V_CMPX_GE_U16
10417 
10418  GPUStaticInst*
10420  {
10421  return new Inst_VOPC__V_CMPX_T_U16(&iFmt->iFmt_VOPC);
10422  } // decode_OP_VOPC__V_CMPX_T_U16
10423 
10424  GPUStaticInst*
10426  {
10427  return new Inst_VOPC__V_CMP_F_I32(&iFmt->iFmt_VOPC);
10428  } // decode_OP_VOPC__V_CMP_F_I32
10429 
10430  GPUStaticInst*
10432  {
10433  return new Inst_VOPC__V_CMP_LT_I32(&iFmt->iFmt_VOPC);
10434  } // decode_OP_VOPC__V_CMP_LT_I32
10435 
10436  GPUStaticInst*
10438  {
10439  return new Inst_VOPC__V_CMP_EQ_I32(&iFmt->iFmt_VOPC);
10440  } // decode_OP_VOPC__V_CMP_EQ_I32
10441 
10442  GPUStaticInst*
10444  {
10445  return new Inst_VOPC__V_CMP_LE_I32(&iFmt->iFmt_VOPC);
10446  } // decode_OP_VOPC__V_CMP_LE_I32
10447 
10448  GPUStaticInst*
10450  {
10451  return new Inst_VOPC__V_CMP_GT_I32(&iFmt->iFmt_VOPC);
10452  } // decode_OP_VOPC__V_CMP_GT_I32
10453 
10454  GPUStaticInst*
10456  {
10457  return new Inst_VOPC__V_CMP_NE_I32(&iFmt->iFmt_VOPC);
10458  } // decode_OP_VOPC__V_CMP_NE_I32
10459 
10460  GPUStaticInst*
10462  {
10463  return new Inst_VOPC__V_CMP_GE_I32(&iFmt->iFmt_VOPC);
10464  } // decode_OP_VOPC__V_CMP_GE_I32
10465 
10466  GPUStaticInst*
10468  {
10469  return new Inst_VOPC__V_CMP_T_I32(&iFmt->iFmt_VOPC);
10470  } // decode_OP_VOPC__V_CMP_T_I32
10471 
10472  GPUStaticInst*
10474  {
10475  return new Inst_VOPC__V_CMP_F_U32(&iFmt->iFmt_VOPC);
10476  } // decode_OP_VOPC__V_CMP_F_U32
10477 
10478  GPUStaticInst*
10480  {
10481  return new Inst_VOPC__V_CMP_LT_U32(&iFmt->iFmt_VOPC);
10482  } // decode_OP_VOPC__V_CMP_LT_U32
10483 
10484  GPUStaticInst*
10486  {
10487  return new Inst_VOPC__V_CMP_EQ_U32(&iFmt->iFmt_VOPC);
10488  } // decode_OP_VOPC__V_CMP_EQ_U32
10489 
10490  GPUStaticInst*
10492  {
10493  return new Inst_VOPC__V_CMP_LE_U32(&iFmt->iFmt_VOPC);
10494  } // decode_OP_VOPC__V_CMP_LE_U32
10495 
10496  GPUStaticInst*
10498  {
10499  return new Inst_VOPC__V_CMP_GT_U32(&iFmt->iFmt_VOPC);
10500  } // decode_OP_VOPC__V_CMP_GT_U32
10501 
10502  GPUStaticInst*
10504  {
10505  return new Inst_VOPC__V_CMP_NE_U32(&iFmt->iFmt_VOPC);
10506  } // decode_OP_VOPC__V_CMP_NE_U32
10507 
10508  GPUStaticInst*
10510  {
10511  return new Inst_VOPC__V_CMP_GE_U32(&iFmt->iFmt_VOPC);
10512  } // decode_OP_VOPC__V_CMP_GE_U32
10513 
10514  GPUStaticInst*
10516  {
10517  return new Inst_VOPC__V_CMP_T_U32(&iFmt->iFmt_VOPC);
10518  } // decode_OP_VOPC__V_CMP_T_U32
10519 
10520  GPUStaticInst*
10522  {
10523  return new Inst_VOPC__V_CMPX_F_I32(&iFmt->iFmt_VOPC);
10524  } // decode_OP_VOPC__V_CMPX_F_I32
10525 
10526  GPUStaticInst*
10528  {
10529  return new Inst_VOPC__V_CMPX_LT_I32(&iFmt->iFmt_VOPC);
10530  } // decode_OP_VOPC__V_CMPX_LT_I32
10531 
10532  GPUStaticInst*
10534  {
10535  return new Inst_VOPC__V_CMPX_EQ_I32(&iFmt->iFmt_VOPC);
10536  } // decode_OP_VOPC__V_CMPX_EQ_I32
10537 
10538  GPUStaticInst*
10540  {
10541  return new Inst_VOPC__V_CMPX_LE_I32(&iFmt->iFmt_VOPC);
10542  } // decode_OP_VOPC__V_CMPX_LE_I32
10543 
10544  GPUStaticInst*
10546  {
10547  return new Inst_VOPC__V_CMPX_GT_I32(&iFmt->iFmt_VOPC);
10548  } // decode_OP_VOPC__V_CMPX_GT_I32
10549 
10550  GPUStaticInst*
10552  {
10553  return new Inst_VOPC__V_CMPX_NE_I32(&iFmt->iFmt_VOPC);
10554  } // decode_OP_VOPC__V_CMPX_NE_I32
10555 
10556  GPUStaticInst*
10558  {
10559  return new Inst_VOPC__V_CMPX_GE_I32(&iFmt->iFmt_VOPC);
10560  } // decode_OP_VOPC__V_CMPX_GE_I32
10561 
10562  GPUStaticInst*
10564  {
10565  return new Inst_VOPC__V_CMPX_T_I32(&iFmt->iFmt_VOPC);
10566  } // decode_OP_VOPC__V_CMPX_T_I32
10567 
10568  GPUStaticInst*
10570  {
10571  return new Inst_VOPC__V_CMPX_F_U32(&iFmt->iFmt_VOPC);
10572  } // decode_OP_VOPC__V_CMPX_F_U32
10573 
10574  GPUStaticInst*
10576  {
10577  return new Inst_VOPC__V_CMPX_LT_U32(&iFmt->iFmt_VOPC);
10578  } // decode_OP_VOPC__V_CMPX_LT_U32
10579 
10580  GPUStaticInst*
10582  {
10583  return new Inst_VOPC__V_CMPX_EQ_U32(&iFmt->iFmt_VOPC);
10584  } // decode_OP_VOPC__V_CMPX_EQ_U32
10585 
10586  GPUStaticInst*
10588  {
10589  return new Inst_VOPC__V_CMPX_LE_U32(&iFmt->iFmt_VOPC);
10590  } // decode_OP_VOPC__V_CMPX_LE_U32
10591 
10592  GPUStaticInst*
10594  {
10595  return new Inst_VOPC__V_CMPX_GT_U32(&iFmt->iFmt_VOPC);
10596  } // decode_OP_VOPC__V_CMPX_GT_U32
10597 
10598  GPUStaticInst*
10600  {
10601  return new Inst_VOPC__V_CMPX_NE_U32(&iFmt->iFmt_VOPC);
10602  } // decode_OP_VOPC__V_CMPX_NE_U32
10603 
10604  GPUStaticInst*
10606  {
10607  return new Inst_VOPC__V_CMPX_GE_U32(&iFmt->iFmt_VOPC);
10608  } // decode_OP_VOPC__V_CMPX_GE_U32
10609 
10610  GPUStaticInst*
10612  {
10613  return new Inst_VOPC__V_CMPX_T_U32(&iFmt->iFmt_VOPC);
10614  } // decode_OP_VOPC__V_CMPX_T_U32
10615 
10616  GPUStaticInst*
10618  {
10619  return new Inst_VOPC__V_CMP_F_I64(&iFmt->iFmt_VOPC);
10620  } // decode_OP_VOPC__V_CMP_F_I64
10621 
10622  GPUStaticInst*
10624  {
10625  return new Inst_VOPC__V_CMP_LT_I64(&iFmt->iFmt_VOPC);
10626  } // decode_OP_VOPC__V_CMP_LT_I64
10627 
10628  GPUStaticInst*
10630  {
10631  return new Inst_VOPC__V_CMP_EQ_I64(&iFmt->iFmt_VOPC);
10632  } // decode_OP_VOPC__V_CMP_EQ_I64
10633 
10634  GPUStaticInst*
10636  {
10637  return new Inst_VOPC__V_CMP_LE_I64(&iFmt->iFmt_VOPC);
10638  } // decode_OP_VOPC__V_CMP_LE_I64
10639 
10640  GPUStaticInst*
10642  {
10643  return new Inst_VOPC__V_CMP_GT_I64(&iFmt->iFmt_VOPC);
10644  } // decode_OP_VOPC__V_CMP_GT_I64
10645 
10646  GPUStaticInst*
10648  {
10649  return new Inst_VOPC__V_CMP_NE_I64(&iFmt->iFmt_VOPC);
10650  } // decode_OP_VOPC__V_CMP_NE_I64
10651 
10652  GPUStaticInst*
10654  {
10655  return new Inst_VOPC__V_CMP_GE_I64(&iFmt->iFmt_VOPC);
10656  } // decode_OP_VOPC__V_CMP_GE_I64
10657 
10658  GPUStaticInst*
10660  {
10661  return new Inst_VOPC__V_CMP_T_I64(&iFmt->iFmt_VOPC);
10662  } // decode_OP_VOPC__V_CMP_T_I64
10663 
10664  GPUStaticInst*
10666  {
10667  return new Inst_VOPC__V_CMP_F_U64(&iFmt->iFmt_VOPC);
10668  } // decode_OP_VOPC__V_CMP_F_U64
10669 
10670  GPUStaticInst*
10672  {
10673  return new Inst_VOPC__V_CMP_LT_U64(&iFmt->iFmt_VOPC);
10674  } // decode_OP_VOPC__V_CMP_LT_U64
10675 
10676  GPUStaticInst*
10678  {
10679  return new Inst_VOPC__V_CMP_EQ_U64(&iFmt->iFmt_VOPC);
10680  } // decode_OP_VOPC__V_CMP_EQ_U64
10681 
10682  GPUStaticInst*
10684  {
10685  return new Inst_VOPC__V_CMP_LE_U64(&iFmt->iFmt_VOPC);
10686  } // decode_OP_VOPC__V_CMP_LE_U64
10687 
10688  GPUStaticInst*
10690  {
10691  return new Inst_VOPC__V_CMP_GT_U64(&iFmt->iFmt_VOPC);
10692  } // decode_OP_VOPC__V_CMP_GT_U64
10693 
10694  GPUStaticInst*
10696  {
10697  return new Inst_VOPC__V_CMP_NE_U64(&iFmt->iFmt_VOPC);
10698  } // decode_OP_VOPC__V_CMP_NE_U64
10699 
10700  GPUStaticInst*
10702  {
10703  return new Inst_VOPC__V_CMP_GE_U64(&iFmt->iFmt_VOPC);
10704  } // decode_OP_VOPC__V_CMP_GE_U64
10705 
10706  GPUStaticInst*
10708  {
10709  return new Inst_VOPC__V_CMP_T_U64(&iFmt->iFmt_VOPC);
10710  } // decode_OP_VOPC__V_CMP_T_U64
10711 
10712  GPUStaticInst*
10714  {
10715  return new Inst_VOPC__V_CMPX_F_I64(&iFmt->iFmt_VOPC);
10716  } // decode_OP_VOPC__V_CMPX_F_I64
10717 
10718  GPUStaticInst*
10720  {
10721  return new Inst_VOPC__V_CMPX_LT_I64(&iFmt->iFmt_VOPC);
10722  } // decode_OP_VOPC__V_CMPX_LT_I64
10723 
10724  GPUStaticInst*
10726  {
10727  return new Inst_VOPC__V_CMPX_EQ_I64(&iFmt->iFmt_VOPC);
10728  } // decode_OP_VOPC__V_CMPX_EQ_I64
10729 
10730  GPUStaticInst*
10732  {
10733  return new Inst_VOPC__V_CMPX_LE_I64(&iFmt->iFmt_VOPC);
10734  } // decode_OP_VOPC__V_CMPX_LE_I64
10735 
10736  GPUStaticInst*
10738  {
10739  return new Inst_VOPC__V_CMPX_GT_I64(&iFmt->iFmt_VOPC);
10740  } // decode_OP_VOPC__V_CMPX_GT_I64
10741 
10742  GPUStaticInst*
10744  {
10745  return new Inst_VOPC__V_CMPX_NE_I64(&iFmt->iFmt_VOPC);
10746  } // decode_OP_VOPC__V_CMPX_NE_I64
10747 
10748  GPUStaticInst*
10750  {
10751  return new Inst_VOPC__V_CMPX_GE_I64(&iFmt->iFmt_VOPC);
10752  } // decode_OP_VOPC__V_CMPX_GE_I64
10753 
10754  GPUStaticInst*
10756  {
10757  return new Inst_VOPC__V_CMPX_T_I64(&iFmt->iFmt_VOPC);
10758  } // decode_OP_VOPC__V_CMPX_T_I64
10759 
10760  GPUStaticInst*
10762  {
10763  return new Inst_VOPC__V_CMPX_F_U64(&iFmt->iFmt_VOPC);
10764  } // decode_OP_VOPC__V_CMPX_F_U64
10765 
10766  GPUStaticInst*
10768  {
10769  return new Inst_VOPC__V_CMPX_LT_U64(&iFmt->iFmt_VOPC);
10770  } // decode_OP_VOPC__V_CMPX_LT_U64
10771 
10772  GPUStaticInst*
10774  {
10775  return new Inst_VOPC__V_CMPX_EQ_U64(&iFmt->iFmt_VOPC);
10776  } // decode_OP_VOPC__V_CMPX_EQ_U64
10777 
10778  GPUStaticInst*
10780  {
10781  return new Inst_VOPC__V_CMPX_LE_U64(&iFmt->iFmt_VOPC);
10782  } // decode_OP_VOPC__V_CMPX_LE_U64
10783 
10784  GPUStaticInst*
10786  {
10787  return new Inst_VOPC__V_CMPX_GT_U64(&iFmt->iFmt_VOPC);
10788  } // decode_OP_VOPC__V_CMPX_GT_U64
10789 
10790  GPUStaticInst*
10792  {
10793  return new Inst_VOPC__V_CMPX_NE_U64(&iFmt->iFmt_VOPC);
10794  } // decode_OP_VOPC__V_CMPX_NE_U64
10795 
10796  GPUStaticInst*
10798  {
10799  return new Inst_VOPC__V_CMPX_GE_U64(&iFmt->iFmt_VOPC);
10800  } // decode_OP_VOPC__V_CMPX_GE_U64
10801 
10802  GPUStaticInst*
10804  {
10805  return new Inst_VOPC__V_CMPX_T_U64(&iFmt->iFmt_VOPC);
10806  } // decode_OP_VOPC__V_CMPX_T_U64
10807 
10808  GPUStaticInst*
10810  {
10811  fatal("Invalid opcode encountered: %#x\n", iFmt->imm_u32);
10812 
10813  return nullptr;
10814  }
10815 } // namespace Gcn3ISA
10816 } // namespace gem5
gem5::Gcn3ISA::Inst_VOP3__V_MAX_U32
Definition: instructions.hh:24371
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_O_F16
Definition: instructions.hh:18113
gem5::Gcn3ISA::Inst_VOP1__V_FREXP_EXP_I16_F16
Definition: instructions.hh:9973
gem5::Gcn3ISA::Inst_DS__DS_MAX_F64
Definition: instructions.hh:33139
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NLE_F64
Definition: instructions.hh:19915
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U32(MachInst)
Definition: decoder.cc:10593
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_LG_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_U32(MachInst)
Definition: decoder.cc:8901
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_I16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_I16_F16(MachInst)
Definition: decoder.cc:9519
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_EQ_U32
Definition: instructions.hh:15733
gem5::Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW
Definition: instructions.hh:37785
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I64(MachInst)
Definition: decoder.cc:5036
gem5::Gcn3ISA::Inst_VOP3__V_BFM_B32
Definition: instructions.hh:30459
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_WRITE_SRC2_B64(MachInst)
Definition: decoder.cc:7148
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X(MachInst)
Definition: decoder.cc:8133
gem5::Gcn3ISA::Inst_VOP3__V_MUL_U32_U24
Definition: instructions.hh:24133
gem5::Gcn3ISA::Inst_DS__DS_CMPST_F32
Definition: instructions.hh:31217
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_AND_X2
Definition: instructions.hh:42549
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_T_U16
Definition: instructions.hh:21649
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_OR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_OR_RTN_B32(MachInst)
Definition: decoder.cc:6530
gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX3
Definition: instructions.hh:41545
gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_INC
Definition: instructions.hh:38895
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F32(MachInst)
Definition: decoder.cc:9915
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F32(MachInst)
Definition: decoder.cc:9963
gem5::Gcn3ISA::Inst_DS__DS_CONSUME
Definition: instructions.hh:34653
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F64(MachInst)
Definition: decoder.cc:10173
gem5::Gcn3ISA::Inst_VOP3__V_CMP_F_F32
Definition: instructions.hh:18419
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_O(MachInst)
Definition: decoder.cc:7940
gem5::Gcn3ISA::Inst_DS__DS_XOR_RTN_B64
Definition: instructions.hh:33545
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_SHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_SHORT(MachInst)
Definition: decoder.cc:8211
gem5::Gcn3ISA::Inst_VOP3__V_MAC_F16
Definition: instructions.hh:25001
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NE_I16
Definition: instructions.hh:21309
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LT_I16
Definition: instructions.hh:21173
gem5::Gcn3ISA::Inst_SOPC__S_CMP_LE_I32
Definition: instructions.hh:3941
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_CL_O
Definition: instructions.hh:39575
gem5::Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ(MachInst)
Definition: decoder.cc:8000
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F64(MachInst)
Definition: decoder.cc:4460
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NLT_F64
Definition: instructions.hh:20527
gem5::Gcn3ISA::Inst_SOP1__S_NOT_B64
Definition: instructions.hh:2343
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::Gcn3ISA::Inst_VOP3__V_CMP_F_I32
Definition: instructions.hh:21683
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_T_I32
Definition: instructions.hh:15631
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NLG_F64
Definition: instructions.hh:13557
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MAX_F32
GPUStaticInst * decode_OP_VOP2__V_MAX_F32(MachInst)
Definition: decoder.cc:3302
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_L
Definition: instructions.hh:40187
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LG_F16
Definition: instructions.hh:11211
gem5::Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:8042
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FLOOR_F64
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F64(MachInst)
Definition: decoder.cc:5564
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:8403
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE_B32
GPUStaticInst * decode_OP_DS__DS_WRITE_B32(MachInst)
Definition: decoder.cc:6404
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I16(MachInst)
Definition: decoder.cc:10335
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NE_U64
Definition: instructions.hh:16379
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_UMIN_X2
Definition: instructions.hh:42447
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_B_CL_O
Definition: instructions.hh:40691
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_ADD_F32
GPUStaticInst * decode_OP_VOP2__V_ADD_F32(MachInst)
Definition: decoder.cc:3242
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LT_F16
Definition: instructions.hh:17909
gem5::Gcn3ISA::Inst_SOPP__S_ENDPGM
Definition: instructions.hh:4451
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U64(MachInst)
Definition: decoder.cc:5120
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I64(MachInst)
Definition: decoder.cc:10719
gem5::Gcn3ISA::Decoder::subDecode_OP_MIMG
GPUStaticInst * subDecode_OP_MIMG(MachInst)
Definition: decoder.cc:3228
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NEQ_F64
Definition: instructions.hh:13115
gem5::Gcn3ISA::Inst_VOP2__V_MUL_LEGACY_F32
Definition: instructions.hh:6279
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I16(MachInst)
Definition: decoder.cc:4550
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F16(MachInst)
Definition: decoder.cc:9675
gem5::Gcn3ISA::Inst_VOP3__V_SUB_U16
Definition: instructions.hh:25069
gem5::Gcn3ISA::Inst_DS__DS_SUB_RTN_U32
Definition: instructions.hh:31477
gem5::Gcn3ISA::Inst_VOP3__V_EXP_F16
Definition: instructions.hh:27455
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
Definition: instructions.hh:35905
gpu_decoder.hh
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GT_U64
Definition: instructions.hh:23179
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE_B128
GPUStaticInst * decode_OP_DS__DS_WRITE_B128(MachInst)
Definition: decoder.cc:7172
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U32(MachInst)
Definition: decoder.cc:4898
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F64(MachInst)
Definition: decoder.cc:4412
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_SET_GPR_IDX_OFF
GPUStaticInst * decode_OP_SOPP__S_SET_GPR_IDX_OFF(MachInst)
Definition: decoder.cc:9147
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I32(MachInst)
Definition: decoder.cc:10443
gem5::Gcn3ISA::Inst_SMEM__S_DCACHE_INV
Definition: instructions.hh:5901
gem5::Gcn3ISA::Inst_DS__DS_RSUB_RTN_U32
Definition: instructions.hh:31511
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_CMPST_RTN_B64
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_B64(MachInst)
Definition: decoder.cc:6878
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_SUBREV_F16
GPUStaticInst * decode_OP_VOP2__V_SUBREV_F16(MachInst)
Definition: decoder.cc:3434
gem5::Gcn3ISA::Inst_DS__DS_MAX_U64
Definition: instructions.hh:32781
gem5::Gcn3ISA::Inst_VOPC__V_CMP_T_U16
Definition: instructions.hh:14271
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F64(MachInst)
Definition: decoder.cc:10227
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MSKOR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_MSKOR_RTN_B64(MachInst)
Definition: decoder.cc:6854
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NGE_F32
Definition: instructions.hh:18725
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_T_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U64(MachInst)
Definition: decoder.cc:10707
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUBREV_F16
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_F16(MachInst)
Definition: decoder.cc:5312
gem5::Gcn3ISA::Inst_VOP3__V_MUL_F32
Definition: instructions.hh:24031
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NGT_F16
Definition: instructions.hh:17705
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:7382
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MUL_U32_U24(MachInst)
Definition: decoder.cc:5174
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_SQRT_F64
GPUStaticInst * decode_OP_VOP1__V_SQRT_F64(MachInst)
Definition: decoder.cc:9417
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX2
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:8187
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U16(MachInst)
Definition: decoder.cc:10395
gem5::Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
Definition: instructions.hh:38051
gem5::Gcn3ISA::Inst_VOP3__V_CMP_F_U32
Definition: instructions.hh:21955
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER(MachInst)
Definition: decoder.cc:9135
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_LE_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LE_U32(MachInst)
Definition: decoder.cc:8925
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_AND_B32
GPUStaticInst * decode_OP_VOP2__V_AND_B32(MachInst)
Definition: decoder.cc:3350
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F64(MachInst)
Definition: decoder.cc:4502
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NEQ_F64
Definition: instructions.hh:13659
gem5::Gcn3ISA::Inst_VOP2__V_ADDC_U32
Definition: instructions.hh:7101
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F16_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_F32(MachInst)
Definition: decoder.cc:9237
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE0
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE0(MachInst)
Definition: decoder.cc:5510
gem5::Gcn3ISA::Inst_SOP1__S_BCNT0_I32_B64
Definition: instructions.hh:2535
gem5::Gcn3ISA::Inst_VOP2__V_MAC_F16
Definition: instructions.hh:7351
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GE_I64
Definition: instructions.hh:16141
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD(MachInst)
Definition: decoder.cc:7916
gem5::Gcn3ISA::InstFormat::iFmt_VINTRP
InFmt_VINTRP iFmt_VINTRP
Definition: gpu_decoder.hh:1663
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_CL
Definition: instructions.hh:39287
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:7412
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U16(MachInst)
Definition: decoder.cc:4628
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U32(MachInst)
Definition: decoder.cc:10509
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F32(MachInst)
Definition: decoder.cc:9867
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B(MachInst)
Definition: decoder.cc:7604
gem5::Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX16
Definition: instructions.hh:5649
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F64(MachInst)
Definition: decoder.cc:10119
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_BFM_B64
GPUStaticInst * decode_OP_SOP2__S_BFM_B64(MachInst)
Definition: decoder.cc:3758
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F64_U32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_U32(MachInst)
Definition: decoder.cc:9309
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE_B96
GPUStaticInst * decode_OP_DS__DS_WRITE_B96(MachInst)
Definition: decoder.cc:7166
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUBREV_F32
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_F32(MachInst)
Definition: decoder.cc:5144
gem5::Gcn3ISA::Inst_SOPP__S_SLEEP
Definition: instructions.hh:4845
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GE_F64
Definition: instructions.hh:12877
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F32(MachInst)
Definition: decoder.cc:9999
gem5::Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:8048
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_B_CL_O
Definition: instructions.hh:39755
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_CL
Definition: instructions.hh:40367
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_CL
Definition: instructions.hh:41123
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRAP_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRAP_RTN_B32(MachInst)
Definition: decoder.cc:6590
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GT_I16
Definition: instructions.hh:14441
gem5::Gcn3ISA::Inst_VOP1__V_RCP_F32
Definition: instructions.hh:9017
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_XOR_B32
GPUStaticInst * decode_OP_VOP2__V_XOR_B32(MachInst)
Definition: decoder.cc:3362
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LE_I32
Definition: instructions.hh:15495
gem5::Gcn3ISA::Inst_SOP1__S_ANDN2_SAVEEXEC_B64
Definition: instructions.hh:3301
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U16(MachInst)
Definition: decoder.cc:4616
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_BCNT_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_BCNT_U32_B32(MachInst)
Definition: decoder.cc:6248
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U32(MachInst)
Definition: decoder.cc:10569
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_GETPC_B64
GPUStaticInst * decode_OP_SOP1__S_GETPC_B64(MachInst)
Definition: decoder.cc:8727
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_RCP_F16
GPUStaticInst * decode_OP_VOP1__V_RCP_F16(MachInst)
Definition: decoder.cc:9525
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NE_U32
Definition: instructions.hh:22125
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LT_U32
Definition: instructions.hh:21989
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_ADDC_U32
GPUStaticInst * decode_OP_SOP2__S_ADDC_U32(MachInst)
Definition: decoder.cc:3572
gem5::Gcn3ISA::Inst_VOP3__V_CVT_PKRTZ_F16_F32
Definition: instructions.hh:30561
gem5::Gcn3ISA::Inst_VOPC__V_CMP_U_F64
Definition: instructions.hh:12945
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GT_F16
Definition: instructions.hh:11177
gem5::Gcn3ISA::Inst_VOP2__V_MUL_F32
Definition: instructions.hh:6313
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CL(MachInst)
Definition: decoder.cc:7580
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LE_F32
Definition: instructions.hh:12231
gem5::Gcn3ISA::Inst_VOP2__V_ASHRREV_I32
Definition: instructions.hh:6721
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NGE_F16
Definition: instructions.hh:11347
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_FLOOR_F64
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F64(MachInst)
Definition: decoder.cc:9333
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MBCNT_LO_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_MBCNT_LO_U32_B32(MachInst)
Definition: decoder.cc:6254
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_INC_RTN_U64
GPUStaticInst * decode_OP_DS__DS_INC_RTN_U64(MachInst)
Definition: decoder.cc:6800
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX_I32
GPUStaticInst * decode_OPU_VOP3__V_MAX_I32(MachInst)
Definition: decoder.cc:5204
gem5::Gcn3ISA::Inst_VOP3__V_FRACT_F32
Definition: instructions.hh:26339
gem5::Gcn3ISA::Inst_VOPC__V_CMP_EQ_U64
Definition: instructions.hh:16277
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_LZ_O(MachInst)
Definition: decoder.cc:7868
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U64(MachInst)
Definition: decoder.cc:5108
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_LT_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LT_U32(MachInst)
Definition: decoder.cc:3884
gem5::Gcn3ISA::Inst_DS__DS_RSUB_U64
Definition: instructions.hh:32589
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F16(MachInst)
Definition: decoder.cc:3992
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_SRC2_F64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_F64(MachInst)
Definition: decoder.cc:7154
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I16(MachInst)
Definition: decoder.cc:10251
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SSHORT
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SSHORT(MachInst)
Definition: decoder.cc:7208
gem5::Gcn3ISA::Inst_VOP3__V_MIN3_U32
Definition: instructions.hh:28487
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U16(MachInst)
Definition: decoder.cc:10287
gem5::Gcn3ISA::Decoder::tableDecodePrimary
static IsaDecodeMethod tableDecodePrimary[512]
Definition: gpu_decoder.hh:63
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F64(MachInst)
Definition: decoder.cc:4496
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MAX_F16
GPUStaticInst * decode_OP_VOP2__V_MAX_F16(MachInst)
Definition: decoder.cc:3506
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D(MachInst)
Definition: decoder.cc:7586
gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORD
Definition: instructions.hh:41477
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F16(MachInst)
Definition: decoder.cc:4082
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_O(MachInst)
Definition: decoder.cc:7682
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F64(MachInst)
Definition: decoder.cc:4442
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_SUBB_U32
GPUStaticInst * decode_OP_VOP2__V_SUBB_U32(MachInst)
Definition: decoder.cc:3410
gem5::Gcn3ISA::Inst_VOP3__V_CMP_EQ_U16
Definition: instructions.hh:20935
gem5::Gcn3ISA::Inst_VOP1__V_FREXP_MANT_F32
Definition: instructions.hh:9593
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GE_U16
Definition: instructions.hh:14781
gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_DEC
Definition: instructions.hh:38929
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_BCNT0_I32_B64
GPUStaticInst * decode_OP_SOP1__S_BCNT0_I32_B64(MachInst)
Definition: decoder.cc:8625
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_CSELECT_B32
GPUStaticInst * decode_OP_SOP2__S_CSELECT_B32(MachInst)
Definition: decoder.cc:3608
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRXCHG2_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG2_RTN_B64(MachInst)
Definition: decoder.cc:6866
gem5::Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
Definition: instructions.hh:37823
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GT_U32
Definition: instructions.hh:22091
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_B_O
Definition: instructions.hh:40871
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:8373
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I16(MachInst)
Definition: decoder.cc:10329
gem5::Gcn3ISA::Inst_VOP1__V_EXP_F16
Definition: instructions.hh:9909
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
Definition: instructions.hh:35867
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_LOAD_USHORT
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_USHORT(MachInst)
Definition: decoder.cc:7202
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F64_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_U32(MachInst)
Definition: decoder.cc:5540
gem5::Gcn3ISA::Inst_VOP2__V_MADAK_F16
Definition: instructions.hh:7421
gem5::Gcn3ISA::Inst_VOP3__V_CVT_F32_F16
Definition: instructions.hh:25827
gem5::Gcn3ISA::Inst_VOP3__V_CVT_OFF_F32_I4
Definition: instructions.hh:25923
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F32
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F32(MachInst)
Definition: decoder.cc:9489
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE2
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE2(MachInst)
Definition: decoder.cc:5522
gem5::Gcn3ISA::Inst_VOP1__V_CVT_F32_F16
Definition: instructions.hh:8281
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_U32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_U32_F32(MachInst)
Definition: decoder.cc:5450
gem5::Gcn3ISA::Inst_SOPC__S_CMP_LE_U32
Definition: instructions.hh:4133
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NE_U64
Definition: instructions.hh:16923
gem5::Gcn3ISA::Inst_DS__DS_DEC_U32
Definition: instructions.hh:30791
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
Definition: instructions.hh:35753
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I32_F64
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I32_F64(MachInst)
Definition: decoder.cc:9465
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FLOOR_F32
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F32(MachInst)
Definition: decoder.cc:5594
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_O(MachInst)
Definition: decoder.cc:7730
gem5::Gcn3ISA::Inst_VOP3__V_FFBL_B32
Definition: instructions.hh:26947
gem5::Gcn3ISA::Inst_VOP3__V_MQSAD_PK_U16_U8
Definition: instructions.hh:29213
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW(MachInst)
Definition: decoder.cc:8079
gem5::Gcn3ISA::Inst_VOP2__V_SUBBREV_U32
Definition: instructions.hh:7177
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NLT_F32
Definition: instructions.hh:12061
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_PK_I16_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_I16_I32(MachInst)
Definition: decoder.cc:6320
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F32(MachInst)
Definition: decoder.cc:4166
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I16(MachInst)
Definition: decoder.cc:10269
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SUB
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SUB(MachInst)
Definition: decoder.cc:8277
gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_UBYTE
Definition: instructions.hh:41341
gem5::Gcn3ISA::InFmt_SOPP
Definition: gpu_decoder.hh:1539
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_O
Definition: instructions.hh:41231
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2
Definition: instructions.hh:37231
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_BCNT1_I32_B32
GPUStaticInst * decode_OP_SOP1__S_BCNT1_I32_B32(MachInst)
Definition: decoder.cc:8631
gem5::Gcn3ISA::Inst_SOP1__S_MOVRELS_B64
Definition: instructions.hh:3557
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GT_U16
Definition: instructions.hh:21547
gem5::Gcn3ISA::Inst_SOP1__S_NAND_SAVEEXEC_B64
Definition: instructions.hh:3365
gem5::Gcn3ISA::Inst_VOP3__V_LSHRREV_B32
Definition: instructions.hh:24405
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_SETPRIO
GPUStaticInst * decode_OP_SOPP__S_SETPRIO(MachInst)
Definition: decoder.cc:9069
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:8115
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NLG_F32
Definition: instructions.hh:19303
gem5::Gcn3ISA::Inst_VOPC__V_CMP_TRU_F16
Definition: instructions.hh:11007
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_LDEXP_F16
GPUStaticInst * decode_OP_VOP2__V_LDEXP_F16(MachInst)
Definition: decoder.cc:3542
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I64(MachInst)
Definition: decoder.cc:10647
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U32(MachInst)
Definition: decoder.cc:4904
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U32(MachInst)
Definition: decoder.cc:4892
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I32(MachInst)
Definition: decoder.cc:10461
gem5::Gcn3ISA::Inst_VOP3__V_RSQ_F32
Definition: instructions.hh:26627
gem5::Gcn3ISA::Inst_DS__DS_MIN_RTN_I64
Definition: instructions.hh:33341
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U64(MachInst)
Definition: decoder.cc:5114
gem5::Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
Definition: instructions.hh:37595
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_F32
GPUStaticInst * decode_OP_DS__DS_MAX_F32(MachInst)
Definition: decoder.cc:6440
gem5::Gcn3ISA::Decoder::decode_invalid
GPUStaticInst * decode_invalid(MachInst)
Definition: decoder.cc:10809
gem5::Gcn3ISA::Inst_DS__DS_MAX_SRC2_I32
Definition: instructions.hh:34167
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_UMIN
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:7526
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_SHORT
Definition: instructions.hh:36301
gem5::Gcn3ISA::Inst_VOP3__V_MAD_U16
Definition: instructions.hh:29397
gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_SHORT
Definition: instructions.hh:41647
gem5::Gcn3ISA::Inst_VOP3__V_INTERP_P2_F16
Definition: instructions.hh:29811
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_BITCMP1_B64
GPUStaticInst * decode_OP_SOPC__S_BITCMP1_B64(MachInst)
Definition: decoder.cc:8949
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_B
Definition: instructions.hh:40439
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GE_I64
Definition: instructions.hh:22975
gem5::Gcn3ISA::Inst_VOP2__V_ASHRREV_I16
Definition: instructions.hh:7661
gem5::Gcn3ISA::Inst_SMEM__S_DCACHE_INV_VOL
Definition: instructions.hh:5957
gem5::Gcn3ISA::Inst_DS__DS_MIN_RTN_F64
Definition: instructions.hh:33783
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_LOG_F32
GPUStaticInst * decode_OP_VOP1__V_LOG_F32(MachInst)
Definition: decoder.cc:9375
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_U32
GPUStaticInst * decode_OP_DS__DS_MIN_U32(MachInst)
Definition: decoder.cc:6368
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I16(MachInst)
Definition: decoder.cc:4568
gem5::Gcn3ISA::Inst_SOPK__S_CMPK_GE_U32
Definition: instructions.hh:1895
gem5::Gcn3ISA::IsaDecodeMethod
GPUStaticInst *(Decoder::*)(MachInst) IsaDecodeMethod
Definition: gpu_decoder.hh:52
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I32(MachInst)
Definition: decoder.cc:4754
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_SUB_F16
GPUStaticInst * decode_OP_VOP2__V_SUB_F16(MachInst)
Definition: decoder.cc:3428
gem5::Gcn3ISA::Decoder::subDecode_OP_VOPC
GPUStaticInst * subDecode_OP_VOPC(MachInst)
Definition: decoder.cc:3132
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CUBEMA_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBEMA_F32(MachInst)
Definition: decoder.cc:5894
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GE_F64
Definition: instructions.hh:19711
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U32(MachInst)
Definition: decoder.cc:4796
gem5::Gcn3ISA::Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER
Definition: instructions.hh:5205
gem5::Gcn3ISA::Inst_VOPC__V_CMP_CLASS_F16
Definition: instructions.hh:10429
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_MOV_FED_B32
GPUStaticInst * decode_OP_VOP1__V_MOV_FED_B32(MachInst)
Definition: decoder.cc:9231
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F32(MachInst)
Definition: decoder.cc:4316
gem5::Gcn3ISA::Inst_DS__DS_MAX_SRC2_F32
Definition: instructions.hh:34407
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F64(MachInst)
Definition: decoder.cc:4520
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F64(MachInst)
Definition: decoder.cc:10125
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_LOAD
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD(MachInst)
Definition: decoder.cc:7430
gem5::Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:8030
gem5::Gcn3ISA::Inst_SOPK__S_GETREG_B32
Definition: instructions.hh:2087
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:8265
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GT_U32
Definition: instructions.hh:15801
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MOV_FED_B32
GPUStaticInst * decode_OPU_VOP3__V_MOV_FED_B32(MachInst)
Definition: decoder.cc:5462
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_ADD_F32
GPUStaticInst * decode_OPU_VOP3__V_ADD_F32(MachInst)
Definition: decoder.cc:5132
gem5::Gcn3ISA::Inst_SOP1__S_FLBIT_I32_B64
Definition: instructions.hh:2791
gem5::Gcn3ISA::Inst_SMEM__S_BUFFER_STORE_DWORD
Definition: instructions.hh:5793
gem5::Gcn3ISA::Inst_SOP2__S_ANDN2_B64
Definition: instructions.hh:693
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LE_U16
Definition: instructions.hh:14679
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GT_I16
Definition: instructions.hh:21275
gem5::Gcn3ISA::Inst_VOP3__V_LSHRREV_B64
Definition: instructions.hh:30357
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MUL_I32_I24
GPUStaticInst * decode_OP_VOP2__V_MUL_I32_I24(MachInst)
Definition: decoder.cc:3272
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MAX_I16
GPUStaticInst * decode_OP_VOP2__V_MAX_I16(MachInst)
Definition: decoder.cc:3524
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F32(MachInst)
Definition: decoder.cc:4286
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SQRT_F32
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F32(MachInst)
Definition: decoder.cc:5642
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U16(MachInst)
Definition: decoder.cc:4706
gem5::Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
Definition: instructions.hh:37861
gem5::Gcn3ISA::Inst_DS__DS_WRITE_SRC2_B32
Definition: instructions.hh:34347
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_AND
Definition: instructions.hh:42097
gem5::Gcn3ISA::Inst_SOP1__S_NOT_B32
Definition: instructions.hh:2311
gem5::Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X(MachInst)
Definition: decoder.cc:8036
gem5::Gcn3ISA::Inst_VOP2__V_MADAK_F32
Definition: instructions.hh:6959
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GT_F16
Definition: instructions.hh:18011
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LG_F32
Definition: instructions.hh:19133
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_O(MachInst)
Definition: decoder.cc:7856
gem5::Gcn3ISA::Inst_SOP1__S_FLBIT_I32_I64
Definition: instructions.hh:2855
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X
Definition: instructions.hh:35791
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NEQ_F64
Definition: instructions.hh:19949
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_D_CL
Definition: instructions.hh:39359
gem5::Gcn3ISA::Inst_VOP1__V_SQRT_F64
Definition: instructions.hh:9209
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_FRACT_F64
GPUStaticInst * decode_OP_VOP1__V_FRACT_F64(MachInst)
Definition: decoder.cc:9477
gem5::Gcn3ISA::Inst_VOPC__V_CMP_O_F32
Definition: instructions.hh:11823
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_GWS_BARRIER
GPUStaticInst * decode_OP_DS__DS_GWS_BARRIER(MachInst)
Definition: decoder.cc:7052
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NEQ_F32
Definition: instructions.hh:12027
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_XOR_B64
GPUStaticInst * decode_OP_SOP2__S_XOR_B64(MachInst)
Definition: decoder.cc:3650
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_ATC_PROBE
GPUStaticInst * decode_OP_SMEM__S_ATC_PROBE(MachInst)
Definition: decoder.cc:8547
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NLT_F16
Definition: instructions.hh:10973
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F64(MachInst)
Definition: decoder.cc:4514
gem5::Gcn3ISA::Inst_VOP3__V_CVT_PKACCUM_U8_F32
Definition: instructions.hh:29605
gem5::Gcn3ISA::Inst_SOP2__S_MAX_I32
Definition: instructions.hh:319
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F32(MachInst)
Definition: decoder.cc:10011
gem5::Gcn3ISA::Inst_VOP3__V_LERP_U8
Definition: instructions.hh:28307
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX2
Definition: instructions.hh:36141
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F16(MachInst)
Definition: decoder.cc:4046
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_B_O
Definition: instructions.hh:39719
gem5::Gcn3ISA::Inst_SOP1__S_FLBIT_I32_B32
Definition: instructions.hh:2759
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORD
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORD(MachInst)
Definition: decoder.cc:8493
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_T_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U64(MachInst)
Definition: decoder.cc:10803
gem5::Gcn3ISA::Inst_DS__DS_ADD_F32
Definition: instructions.hh:31343
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F16(MachInst)
Definition: decoder.cc:4076
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SUB
Definition: instructions.hh:41925
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRXCHG_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG_RTN_B32(MachInst)
Definition: decoder.cc:6548
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I16(MachInst)
Definition: decoder.cc:10347
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F32(MachInst)
Definition: decoder.cc:9921
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_TRU_F32
Definition: instructions.hh:19473
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NGT_F32
Definition: instructions.hh:19337
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MUL_I32_I24(MachInst)
Definition: decoder.cc:5162
gem5::Gcn3ISA::Inst_VOP3__V_CVT_F16_U16
Definition: instructions.hh:27199
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_OR_X2
Definition: instructions.hh:42583
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NLG_F16
Definition: instructions.hh:18215
gem5::Gcn3ISA::InstFormat::iFmt_VOP3_SDST_ENC
InFmt_VOP3_SDST_ENC iFmt_VOP3_SDST_ENC
Definition: gpu_decoder.hh:1668
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F16(MachInst)
Definition: decoder.cc:9681
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F32(MachInst)
Definition: decoder.cc:4226
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ(MachInst)
Definition: decoder.cc:8097
gem5::Gcn3ISA::Inst_VOP1__V_CVT_F16_U16
Definition: instructions.hh:9653
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_FF0_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FF0_I32_B64(MachInst)
Definition: decoder.cc:8649
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN3_I32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_I32(MachInst)
Definition: decoder.cc:5954
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U32(MachInst)
Definition: decoder.cc:4820
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O(MachInst)
Definition: decoder.cc:7952
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F32(MachInst)
Definition: decoder.cc:4196
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_BARRIER
GPUStaticInst * decode_OP_SOPP__S_BARRIER(MachInst)
Definition: decoder.cc:9039
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_SETREG_IMM32_B32
GPUStaticInst * decode_OP_SOPK__S_SETREG_IMM32_B32(MachInst)
Definition: decoder.cc:3926
gem5::Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
Definition: instructions.hh:38089
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_MAX_I32
GPUStaticInst * decode_OP_SOP2__S_MAX_I32(MachInst)
Definition: decoder.cc:3596
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F32(MachInst)
Definition: decoder.cc:9981
gem5::Gcn3ISA::Inst_VOP3__V_LDEXP_F16
Definition: instructions.hh:25477
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_INC_X2
Definition: instructions.hh:42651
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I64(MachInst)
Definition: decoder.cc:4940
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_CLASS_F64
Definition: instructions.hh:17229
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_CMOVK_I32
GPUStaticInst * decode_OP_SOPK__S_CMOVK_I32(MachInst)
Definition: decoder.cc:3818
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NLG_F32
Definition: instructions.hh:11925
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F64(MachInst)
Definition: decoder.cc:10059
gem5::Gcn3ISA::Inst_VOP1__V_RSQ_F32
Definition: instructions.hh:9081
gem5::Gcn3ISA::Inst_SOPP__S_CBRANCH_CDBGUSER
Definition: instructions.hh:5145
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F16(MachInst)
Definition: decoder.cc:9837
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F32_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_F16(MachInst)
Definition: decoder.cc:5474
gem5::Gcn3ISA::Inst_VOP1__V_CVT_F32_UBYTE2
Definition: instructions.hh:8537
gem5::Gcn3ISA::Inst_SOPP__S_SENDMSG
Definition: instructions.hh:4905
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX4
Definition: instructions.hh:36453
gem5::Gcn3ISA::Inst_VOP3__V_MUL_LO_U32
Definition: instructions.hh:30017
gem5::Gcn3ISA::Inst_DS__DS_XOR_SRC2_B32
Definition: instructions.hh:34317
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_RCP_F64
GPUStaticInst * decode_OP_VOP1__V_RCP_F64(MachInst)
Definition: decoder.cc:9399
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_LSHRREV_B16
GPUStaticInst * decode_OP_VOP2__V_LSHRREV_B16(MachInst)
Definition: decoder.cc:3494
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MAD_U32_U24(MachInst)
Definition: decoder.cc:5870
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
Definition: instructions.hh:35715
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F32(MachInst)
Definition: decoder.cc:10017
gem5::Gcn3ISA::Inst_VOP3__V_LSHLREV_B32
Definition: instructions.hh:24473
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_LZ
Definition: instructions.hh:39503
gem5::Gcn3ISA::Inst_VOP3__V_CVT_F32_F64
Definition: instructions.hh:25955
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_RCP_F32
GPUStaticInst * decode_OP_VOP1__V_RCP_F32(MachInst)
Definition: decoder.cc:9381
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_MUL_I32
GPUStaticInst * decode_OP_SOP2__S_MUL_I32(MachInst)
Definition: decoder.cc:3764
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX2
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX2(MachInst)
Definition: decoder.cc:8223
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_NOP
GPUStaticInst * decode_OP_DS__DS_NOP(MachInst)
Definition: decoder.cc:6446
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F64(MachInst)
Definition: decoder.cc:4526
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LT_U64
Definition: instructions.hh:16243
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN_F16
GPUStaticInst * decode_OPU_VOP3__V_MIN_F16(MachInst)
Definition: decoder.cc:5378
gem5::Gcn3ISA::Inst_VOP1__V_FREXP_EXP_I32_F64
Definition: instructions.hh:9465
gem5::Gcn3ISA::Inst_VOP1__V_CVT_F32_F64
Definition: instructions.hh:8409
gem5::Gcn3ISA::Inst_VOP3__V_CEIL_F64
Definition: instructions.hh:26243
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_SMAX
Definition: instructions.hh:36799
gem5::Gcn3ISA::Inst_DS__DS_ADD_U32
Definition: instructions.hh:30663
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_T_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U32(MachInst)
Definition: decoder.cc:4832
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F64(MachInst)
Definition: decoder.cc:10161
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GET_RESINFO
Definition: instructions.hh:38487
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F32_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_F16(MachInst)
Definition: decoder.cc:9243
gem5::Gcn3ISA::Inst_SOP1__S_BCNT1_I32_B32
Definition: instructions.hh:2567
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F32(MachInst)
Definition: decoder.cc:9939
gem5::Gcn3ISA::Inst_SOPP__S_SET_GPR_IDX_OFF
Definition: instructions.hh:5265
gem5::Gcn3ISA::Inst_SMEM__S_STORE_DWORD
Definition: instructions.hh:5685
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_ADD
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_ADD(MachInst)
Definition: decoder.cc:7508
gem5::Gcn3ISA::Inst_VOP1__V_FREXP_EXP_I32_F32
Definition: instructions.hh:9561
gem5::Gcn3ISA::InFmt_VOPC
Definition: gpu_decoder.hh:1601
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_LSHLREV_B16
GPUStaticInst * decode_OP_VOP2__V_LSHLREV_B16(MachInst)
Definition: decoder.cc:3488
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_SUB_U64
GPUStaticInst * decode_OP_DS__DS_SUB_U64(MachInst)
Definition: decoder.cc:6668
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_T_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I64(MachInst)
Definition: decoder.cc:4976
gem5::Gcn3ISA::Inst_SOPC__S_CMP_GE_I32
Definition: instructions.hh:3877
gem5::Gcn3ISA::Inst_VOP3__V_MAD_I32_I24
Definition: instructions.hh:27911
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_APPEND
GPUStaticInst * decode_OP_DS__DS_APPEND(MachInst)
Definition: decoder.cc:7064
gem5::Gcn3ISA::Inst_DS__DS_WRITE_B96
Definition: instructions.hh:35199
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_MOVRELD_B64
GPUStaticInst * decode_OP_SOP1__S_MOVRELD_B64(MachInst)
Definition: decoder.cc:8829
gem5::Gcn3ISA::Inst_SOP2__S_NAND_B32
Definition: instructions.hh:795
gem5::Gcn3ISA::Inst_SOP2__S_XNOR_B32
Definition: instructions.hh:931
gem5::Gcn3ISA::Inst_VOPC__V_CMP_TRU_F64
Definition: instructions.hh:13183
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LE_U32
Definition: instructions.hh:15223
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_SUB_RTN_U32
GPUStaticInst * decode_OP_DS__DS_SUB_RTN_U32(MachInst)
Definition: decoder.cc:6476
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
Definition: instructions.hh:37087
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_TRAP
GPUStaticInst * decode_OP_SOPP__S_TRAP(MachInst)
Definition: decoder.cc:9087
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I16(MachInst)
Definition: decoder.cc:4580
gem5::Gcn3ISA::Inst_VOP3__V_LSHLREV_B64
Definition: instructions.hh:30323
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_B
Definition: instructions.hh:40223
gem5::Gcn3ISA::Inst_DS__DS_WRITE2_B64
Definition: instructions.hh:32975
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NEQ_F16
Definition: instructions.hh:18317
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F64(MachInst)
Definition: decoder.cc:4358
gem5::Gcn3ISA::InstFormat::iFmt_VOP3
InFmt_VOP3 iFmt_VOP3
Definition: gpu_decoder.hh:1666
gem5::Gcn3ISA::Inst_SMEM__S_MEMTIME
Definition: instructions.hh:6013
gem5::Gcn3ISA::Inst_SOPP__S_WAITCNT
Definition: instructions.hh:4785
gem5::Gcn3ISA::Inst_DS__DS_READ2ST64_B64
Definition: instructions.hh:33919
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MSAD_U8
GPUStaticInst * decode_OPU_VOP3__V_MSAD_U8(MachInst)
Definition: decoder.cc:6068
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD(MachInst)
Definition: decoder.cc:7928
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_D_O
Definition: instructions.hh:39899
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F16(MachInst)
Definition: decoder.cc:9747
gem5::Gcn3ISA::Inst_SOPK__S_CMOVK_I32
Definition: instructions.hh:1575
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_EXP_F16
GPUStaticInst * decode_OP_VOP1__V_EXP_F16(MachInst)
Definition: decoder.cc:9549
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_EQ_I32
Definition: instructions.hh:15461
gem5::Gcn3ISA::Inst_VOPC__V_CMP_T_I32
Definition: instructions.hh:15087
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CEIL_F32
GPUStaticInst * decode_OP_VOP1__V_CEIL_F32(MachInst)
Definition: decoder.cc:9351
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:8421
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_MOV_FED_B32
GPUStaticInst * decode_OP_SOP1__S_MOV_FED_B32(MachInst)
Definition: decoder.cc:8847
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GE_U64
Definition: instructions.hh:23247
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_RNDNE_F64
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F64(MachInst)
Definition: decoder.cc:5558
gem5::Gcn3ISA::Inst_VOP3__V_MAD_U32_U24
Definition: instructions.hh:27947
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U16(MachInst)
Definition: decoder.cc:10311
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRXCHG2_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG2_RTN_B32(MachInst)
Definition: decoder.cc:6554
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U64(MachInst)
Definition: decoder.cc:5090
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN_I16
GPUStaticInst * decode_OPU_VOP3__V_MIN_I16(MachInst)
Definition: decoder.cc:5402
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NLG_F16
Definition: instructions.hh:10837
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_EQ_F32
Definition: instructions.hh:12197
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_ANDN2_B32
GPUStaticInst * decode_OP_SOP2__S_ANDN2_B32(MachInst)
Definition: decoder.cc:3656
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_U_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F64(MachInst)
Definition: decoder.cc:10185
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U32(MachInst)
Definition: decoder.cc:10599
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C(MachInst)
Definition: decoder.cc:7622
gem5::Gcn3ISA::Inst_VOP3__V_FREXP_MANT_F32
Definition: instructions.hh:27139
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F32(MachInst)
Definition: decoder.cc:3944
gem5::Gcn3ISA::Inst_VOP3__V_TRUNC_F32
Definition: instructions.hh:26371
gem5::Gcn3ISA::Inst_VOP2__V_SUBREV_F32
Definition: instructions.hh:6245
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LE_U32
Definition: instructions.hh:22601
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_WRITELANE_B32
GPUStaticInst * decode_OPU_VOP3__V_WRITELANE_B32(MachInst)
Definition: decoder.cc:6242
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NLE_F32
Definition: instructions.hh:19371
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O(MachInst)
Definition: decoder.cc:7754
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NE_I64
Definition: instructions.hh:16107
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_CD_CL
Definition: instructions.hh:41051
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_F32
GPUStaticInst * decode_OP_DS__DS_ADD_F32(MachInst)
Definition: decoder.cc:6452
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_O(MachInst)
Definition: decoder.cc:7670
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_TRUNC_F16
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F16(MachInst)
Definition: decoder.cc:5810
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F64(MachInst)
Definition: decoder.cc:4532
gem5::Gcn3ISA::Inst_VOP3__V_CMP_TRU_F16
Definition: instructions.hh:17841
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U16(MachInst)
Definition: decoder.cc:10299
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_F16
GPUStaticInst * decode_OPU_VOP3__V_MUL_F16(MachInst)
Definition: decoder.cc:5318
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SMIN
Definition: instructions.hh:41961
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_XNOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_XNOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:8793
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NGE_F16
Definition: instructions.hh:18181
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SMAX_X2
Definition: instructions.hh:42481
gem5::Gcn3ISA::Inst_SOPP__S_CBRANCH_EXECZ
Definition: instructions.hh:4665
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_B_O
Definition: instructions.hh:40655
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN_U16
GPUStaticInst * decode_OPU_VOP3__V_MIN_U16(MachInst)
Definition: decoder.cc:5396
gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_SMIN
Definition: instructions.hh:38657
gem5::Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX2
Definition: instructions.hh:5361
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U16(MachInst)
Definition: decoder.cc:10281
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_DCACHE_WB_VOL
GPUStaticInst * decode_OP_SMEM__S_DCACHE_WB_VOL(MachInst)
Definition: decoder.cc:8529
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_BITSET0_B32
GPUStaticInst * decode_OP_SOP1__S_BITSET0_B32(MachInst)
Definition: decoder.cc:8703
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F32(MachInst)
Definition: decoder.cc:9861
gem5::Gcn3ISA::Inst_SOP1__S_FF0_I32_B64
Definition: instructions.hh:2663
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I64(MachInst)
Definition: decoder.cc:4934
gem5::Gcn3ISA::Inst_VOP3__V_CVT_PK_U16_U32
Definition: instructions.hh:30595
gem5::Gcn3ISA::Inst_DS__DS_MIN_I32
Definition: instructions.hh:30823
gem5::Gcn3ISA::Inst_SOP2__S_MAX_U32
Definition: instructions.hh:353
gem5::Gcn3ISA::Inst_VOP2__V_SUBB_U32
Definition: instructions.hh:7139
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U16(MachInst)
Definition: decoder.cc:4700
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:7370
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F64(MachInst)
Definition: decoder.cc:10095
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_RSUB_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_U64(MachInst)
Definition: decoder.cc:6674
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_XOR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_XOR_RTN_B64(MachInst)
Definition: decoder.cc:6848
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I16(MachInst)
Definition: decoder.cc:10365
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_READ_B32
GPUStaticInst * decode_OP_DS__DS_READ_B32(MachInst)
Definition: decoder.cc:6602
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CLREXCP
GPUStaticInst * decode_OPU_VOP3__V_CLREXCP(MachInst)
Definition: decoder.cc:5726
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I32(MachInst)
Definition: decoder.cc:10527
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORD
Definition: instructions.hh:36339
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2
Definition: instructions.hh:37267
gem5::Gcn3ISA::Inst_VOP3__V_SAD_U16
Definition: instructions.hh:28811
gem5::Gcn3ISA::InstFormat::iFmt_SOPP
InFmt_SOPP iFmt_SOPP
Definition: gpu_decoder.hh:1662
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_U32
GPUStaticInst * decode_OP_DS__DS_MAX_U32(MachInst)
Definition: decoder.cc:6374
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F32(MachInst)
Definition: decoder.cc:4244
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_LERP_U8
GPUStaticInst * decode_OPU_VOP3__V_LERP_U8(MachInst)
Definition: decoder.cc:5930
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_XOR
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_XOR(MachInst)
Definition: decoder.cc:8319
gem5::Gcn3ISA::Inst_DS__DS_MIN_F32
Definition: instructions.hh:31249
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F64(MachInst)
Definition: decoder.cc:4370
gem5::Gcn3ISA::Inst_VOP3__V_MIN_F16
Definition: instructions.hh:25307
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NGT_F64
Definition: instructions.hh:20425
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_OR_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:7406
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_T_I32
Definition: instructions.hh:22465
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F32(MachInst)
Definition: decoder.cc:9957
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_UMAX
Definition: instructions.hh:36835
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_B_CL_O
Definition: instructions.hh:40907
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_U64(MachInst)
Definition: decoder.cc:7124
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LE_I32
Definition: instructions.hh:22329
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U64(MachInst)
Definition: decoder.cc:10665
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B32
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B32(MachInst)
Definition: decoder.cc:5222
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:8409
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_F_U32
Definition: instructions.hh:15665
gem5::Gcn3ISA::Inst_VOP3__V_SUB_F32
Definition: instructions.hh:23929
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_SWAPPC_B64
GPUStaticInst * decode_OP_SOP1__S_SWAPPC_B64(MachInst)
Definition: decoder.cc:8739
gem5::Gcn3ISA::Inst_VOP3__V_CVT_F32_U32
Definition: instructions.hh:25667
gem5::Gcn3ISA::Inst_VOP3__V_MIN_I16
Definition: instructions.hh:25443
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_AND_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:7400
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_F32
GPUStaticInst * decode_OPU_VOP3__V_MUL_F32(MachInst)
Definition: decoder.cc:5156
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_I16
GPUStaticInst * decode_OPU_VOP3__V_MAD_I16(MachInst)
Definition: decoder.cc:6116
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U64(MachInst)
Definition: decoder.cc:4988
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I32(MachInst)
Definition: decoder.cc:10533
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_WQM_B64
GPUStaticInst * decode_OP_SOP1__S_WQM_B64(MachInst)
Definition: decoder.cc:8601
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SAD_HI_U8
GPUStaticInst * decode_OPU_VOP3__V_SAD_HI_U8(MachInst)
Definition: decoder.cc:6008
gem5::Gcn3ISA::Inst_SOPP__S_NOP
Definition: instructions.hh:4421
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_OFF_F32_I4
GPUStaticInst * decode_OP_VOP1__V_CVT_OFF_F32_I4(MachInst)
Definition: decoder.cc:9261
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F32_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_U32(MachInst)
Definition: decoder.cc:5444
gem5::Gcn3ISA::Inst_VOP1__V_CVT_F32_U32
Definition: instructions.hh:8121
gem5::Gcn3ISA::Inst_DS__DS_XOR_B64
Definition: instructions.hh:32877
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_XOR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_XOR_RTN_B32(MachInst)
Definition: decoder.cc:6536
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_B_CL
Definition: instructions.hh:39467
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_L
Definition: instructions.hh:40403
gem5::Gcn3ISA::Inst_VOP3__V_MUL_F64
Definition: instructions.hh:29881
gem5::Gcn3ISA::Inst_VOP3__V_FMA_F32
Definition: instructions.hh:28235
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LE_F32
Definition: instructions.hh:19065
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_I16_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_I16_F16(MachInst)
Definition: decoder.cc:5750
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U32(MachInst)
Definition: decoder.cc:4790
gem5::Gcn3ISA::Inst_DS__DS_MAX_SRC2_U64
Definition: instructions.hh:34989
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_FLBIT_I32
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32(MachInst)
Definition: decoder.cc:8679
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_OR_X2
Definition: instructions.hh:37375
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_CMPST_RTN_F32
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_F32(MachInst)
Definition: decoder.cc:6572
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F16
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F16(MachInst)
Definition: decoder.cc:9555
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:7376
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_MEMREALTIME
GPUStaticInst * decode_OP_SMEM__S_MEMREALTIME(MachInst)
Definition: decoder.cc:8541
gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX4
Definition: instructions.hh:41579
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_F32(MachInst)
Definition: decoder.cc:5852
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_F64
GPUStaticInst * decode_OP_DS__DS_MAX_F64(MachInst)
Definition: decoder.cc:6776
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_LO_U16
GPUStaticInst * decode_OPU_VOP3__V_MUL_LO_U16(MachInst)
Definition: decoder.cc:5348
gem5::Gcn3ISA::Inst_SOPC__S_CMP_LG_U64
Definition: instructions.hh:4389
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NEQ_F32
Definition: instructions.hh:18861
gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_USHORT
Definition: instructions.hh:41409
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NGT_F16
Definition: instructions.hh:10871
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SMIN
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:7520
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_CL(MachInst)
Definition: decoder.cc:7772
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_CBRANCH_G_FORK
GPUStaticInst * decode_OP_SOP2__S_CBRANCH_G_FORK(MachInst)
Definition: decoder.cc:3794
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I16_F16
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I16_F16(MachInst)
Definition: decoder.cc:5792
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_UMAX
Definition: instructions.hh:42063
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_F_I32
Definition: instructions.hh:15393
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NGE_F64
Definition: instructions.hh:13523
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U64(MachInst)
Definition: decoder.cc:10767
gem5::Gcn3ISA::Inst_DS__DS_MIN_U32
Definition: instructions.hh:30887
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_NAND_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_NAND_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:8781
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NE_U16
Definition: instructions.hh:14203
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LT_U16
Definition: instructions.hh:14067
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NLE_F16
Definition: instructions.hh:18283
gem5::Gcn3ISA::Inst_DS__DS_MIN_I64
Definition: instructions.hh:32685
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_NAND_B64
GPUStaticInst * decode_OP_SOP2__S_NAND_B64(MachInst)
Definition: decoder.cc:3686
gem5::Gcn3ISA::Inst_VOPC__V_CMP_EQ_I64
Definition: instructions.hh:16005
gem5::Gcn3ISA::Inst_VOP2__V_MIN_F16
Definition: instructions.hh:7729
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_CL(MachInst)
Definition: decoder.cc:7790
gem5::Gcn3ISA::Inst_VINTRP__V_INTERP_P1_F32
Definition: instructions.hh:17025
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_OR_B64
GPUStaticInst * decode_OP_SOP2__S_OR_B64(MachInst)
Definition: decoder.cc:3638
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_GE_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GE_I32(MachInst)
Definition: decoder.cc:3842
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F32(MachInst)
Definition: decoder.cc:3938
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_INTERP_P2_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P2_F16(MachInst)
Definition: decoder.cc:6176
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_F_F32
Definition: instructions.hh:12129
gem5::Gcn3ISA::Inst_SOPC__S_CMP_GE_U32
Definition: instructions.hh:4069
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_GE_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_GE_U32(MachInst)
Definition: decoder.cc:8913
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CEIL_F32
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F32(MachInst)
Definition: decoder.cc:5582
gem5::Gcn3ISA::Inst_DS__DS_WRITE2_B32
Definition: instructions.hh:31113
gem5::Gcn3ISA::Inst_VOP2__V_SUB_F32
Definition: instructions.hh:6211
gem5::Gcn3ISA::Decoder::subDecode_OP_DS
GPUStaticInst * subDecode_OP_DS(MachInst)
Definition: decoder.cc:3196
gem5::Gcn3ISA::Inst_VOP2__V_MIN_I16
Definition: instructions.hh:7865
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_RTN_I32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_I32(MachInst)
Definition: decoder.cc:6500
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN_F32
GPUStaticInst * decode_OPU_VOP3__V_MIN_F32(MachInst)
Definition: decoder.cc:5186
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I64(MachInst)
Definition: decoder.cc:10635
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SMAX
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:7532
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORDX2(MachInst)
Definition: decoder.cc:8499
gem5::Gcn3ISA::Inst_DS__DS_MIN_F64
Definition: instructions.hh:33107
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I32(MachInst)
Definition: decoder.cc:4772
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_T_U32
Definition: instructions.hh:22737
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_OR
Definition: instructions.hh:42131
gem5::Gcn3ISA::Inst_VOPC__V_CMP_EQ_F64
Definition: instructions.hh:12741
gem5::Gcn3ISA::Inst_DS__DS_WRXCHG2ST64_RTN_B32
Definition: instructions.hh:31953
gem5::Gcn3ISA::Inst_SOP2__S_NAND_B64
Definition: instructions.hh:829
gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX2
Definition: instructions.hh:41511
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE_B16
GPUStaticInst * decode_OP_DS__DS_WRITE_B16(MachInst)
Definition: decoder.cc:6464
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NLG_F32
Definition: instructions.hh:18759
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U32(MachInst)
Definition: decoder.cc:10485
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GE_I16
Definition: instructions.hh:14509
gem5::Gcn3ISA::Inst_VOP2__V_OR_B32
Definition: instructions.hh:6823
gem5::Gcn3ISA::Inst_SOP2__S_OR_B64
Definition: instructions.hh:557
gem5::Gcn3ISA::Inst_VOP3__V_OR_B32
Definition: instructions.hh:24541
gem5::Gcn3ISA::Inst_VOP3__V_CVT_F32_UBYTE2
Definition: instructions.hh:26083
gem5::Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
Definition: instructions.hh:37937
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_ADDC_U32
GPUStaticInst * decode_OP_VOP2__V_ADDC_U32(MachInst)
Definition: decoder.cc:3404
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRXCHG_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG_RTN_B64(MachInst)
Definition: decoder.cc:6860
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_MULK_I32
GPUStaticInst * decode_OP_SOPK__S_MULK_I32(MachInst)
Definition: decoder.cc:3902
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE3
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE3(MachInst)
Definition: decoder.cc:5528
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_T_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I32(MachInst)
Definition: decoder.cc:10467
gem5::Gcn3ISA::Inst_VOP3__V_MIN_F32
Definition: instructions.hh:24201
gem5::Gcn3ISA::Inst_VOP3__V_CMP_CLASS_F64
Definition: instructions.hh:17195
gem5::Gcn3ISA::Decoder::tableSubDecode_OP_MUBUF
static IsaDecodeMethod tableSubDecode_OP_MUBUF[128]
Definition: gpu_decoder.hh:69
gem5::Gcn3ISA::Inst_SOP1__S_BITSET0_B64
Definition: instructions.hh:2983
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMIN
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:8289
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_PKNORM_U16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKNORM_U16_F32(MachInst)
Definition: decoder.cc:6302
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U32(MachInst)
Definition: decoder.cc:4916
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_F32(MachInst)
Definition: decoder.cc:7016
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I16(MachInst)
Definition: decoder.cc:4646
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LG_F32
Definition: instructions.hh:11755
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FRACT_F32
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F32(MachInst)
Definition: decoder.cc:5570
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_CONSUME
GPUStaticInst * decode_OP_DS__DS_CONSUME(MachInst)
Definition: decoder.cc:7058
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_DIV_FMAS_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_FMAS_F32(MachInst)
Definition: decoder.cc:6056
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GE_F16
Definition: instructions.hh:11245
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_CL(MachInst)
Definition: decoder.cc:7610
gem5::Gcn3ISA::Inst_VOP3__V_MIN_I32
Definition: instructions.hh:24269
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NE_I64
Definition: instructions.hh:22941
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U64(MachInst)
Definition: decoder.cc:5084
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NE_I64
Definition: instructions.hh:16651
gem5::Gcn3ISA::Inst_VOP3__V_DIV_FMAS_F32
Definition: instructions.hh:29067
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX3_F32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_F32(MachInst)
Definition: decoder.cc:5966
gem5::Gcn3ISA::Inst_SOPP__S_SET_GPR_IDX_MODE
Definition: instructions.hh:5295
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F32(MachInst)
Definition: decoder.cc:4340
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I32(MachInst)
Definition: decoder.cc:4868
gem5::Gcn3ISA::Inst_VOPC__V_CMP_F_I32
Definition: instructions.hh:14849
gem5::Gcn3ISA::Inst_VOP3__V_EXP_F32
Definition: instructions.hh:26499
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUB_F16
GPUStaticInst * decode_OPU_VOP3__V_SUB_F16(MachInst)
Definition: decoder.cc:5306
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_VCCNZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_VCCNZ(MachInst)
Definition: decoder.cc:9021
gem5::Gcn3ISA::Inst_DS__DS_DEC_RTN_U32
Definition: instructions.hh:31579
gem5::Gcn3ISA::Inst_VOP3__V_FMA_F16
Definition: instructions.hh:29533
gem5::Gcn3ISA::Inst_DS__DS_MIN_SRC2_U64
Definition: instructions.hh:34959
gem5::Gcn3ISA::InFmt_VINTRP::OP
unsigned int OP
Definition: gpu_decoder.hh:1551
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_U_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F16(MachInst)
Definition: decoder.cc:9705
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_EQ_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_U32(MachInst)
Definition: decoder.cc:8895
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_LOG_F16
GPUStaticInst * decode_OPU_VOP3__V_LOG_F16(MachInst)
Definition: decoder.cc:5774
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX2
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX2(MachInst)
Definition: decoder.cc:7256
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MUL_LO_U16
GPUStaticInst * decode_OP_VOP2__V_MUL_LO_U16(MachInst)
Definition: decoder.cc:3482
gem5::Gcn3ISA::Inst_SOPC__S_BITCMP1_B32
Definition: instructions.hh:4197
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_WBINVL1
Definition: instructions.hh:36523
gem5::Gcn3ISA::Inst_VOPC__V_CMP_T_U32
Definition: instructions.hh:15359
gem5::Gcn3ISA::Inst_VOPC__V_CMP_F_F32
Definition: instructions.hh:11585
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F16(MachInst)
Definition: decoder.cc:9819
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_U_F64
Definition: instructions.hh:13489
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GT_U16
Definition: instructions.hh:14169
gem5::Gcn3ISA::Inst_VOP3__V_ADDC_U32
Definition: instructions.hh:24751
gem5::Gcn3ISA::Inst_DS__DS_READ_I8
Definition: instructions.hh:32293
gem5::Gcn3ISA::Inst_DS__DS_MIN_U64
Definition: instructions.hh:32749
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_SRC2_I32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_I32(MachInst)
Definition: decoder.cc:6956
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NGT_F32
Definition: instructions.hh:18793
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX3
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX3(MachInst)
Definition: decoder.cc:8229
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_XOR
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_XOR(MachInst)
Definition: decoder.cc:7556
gem5::Gcn3ISA::Inst_VOP1__V_BFREV_B32
Definition: instructions.hh:9337
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F32(MachInst)
Definition: decoder.cc:9909
gem5::Gcn3ISA::Inst_VOP1__V_FFBL_B32
Definition: instructions.hh:9401
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F32(MachInst)
Definition: decoder.cc:10029
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_LOG_F32
GPUStaticInst * decode_OPU_VOP3__V_LOG_F32(MachInst)
Definition: decoder.cc:5606
gem5::Gcn3ISA::Inst_VOP3__V_CVT_PK_I16_I32
Definition: instructions.hh:30629
gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_SBYTE
Definition: instructions.hh:41375
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_EQ_U16
Definition: instructions.hh:14645
gem5::Gcn3ISA::Inst_VOP3__V_CMP_TRU_F64
Definition: instructions.hh:20017
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_U64
GPUStaticInst * decode_OP_DS__DS_MAX_U64(MachInst)
Definition: decoder.cc:6710
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_READ2_B32
GPUStaticInst * decode_OP_DS__DS_READ2_B32(MachInst)
Definition: decoder.cc:6608
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_O_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F16(MachInst)
Definition: decoder.cc:9699
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_O_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F64(MachInst)
Definition: decoder.cc:4400
gem5::Gcn3ISA::Inst_DS__DS_READ_B96
Definition: instructions.hh:35267
gem5::Gcn3ISA::Inst_VOP3__V_FFBH_I32
Definition: instructions.hh:26979
gem5::Gcn3ISA::Decoder::tableSubDecode_OPU_VOP3
static IsaDecodeMethod tableSubDecode_OPU_VOP3[768]
Definition: gpu_decoder.hh:64
gem5::Gcn3ISA::Inst_VOP3__V_TRIG_PREOP_F64
Definition: instructions.hh:30425
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SWAP
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:8259
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_BCNT1_I32_B64
GPUStaticInst * decode_OP_SOP1__S_BCNT1_I32_B64(MachInst)
Definition: decoder.cc:8637
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CUBETC_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBETC_F32(MachInst)
Definition: decoder.cc:5888
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F16(MachInst)
Definition: decoder.cc:9771
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_O(MachInst)
Definition: decoder.cc:7718
gem5::Gcn3ISA::Inst_VOP3__V_ALIGNBIT_B32
Definition: instructions.hh:28343
gem5::Gcn3ISA::Inst_VOP2__V_MIN_F32
Definition: instructions.hh:6483
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NGT_F16
Definition: instructions.hh:11415
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_SUBB_U32
GPUStaticInst * decode_OP_SOP2__S_SUBB_U32(MachInst)
Definition: decoder.cc:3578
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_B_CL
Definition: instructions.hh:40259
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F64(MachInst)
Definition: decoder.cc:10155
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_I32_F32(MachInst)
Definition: decoder.cc:9225
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F64(MachInst)
Definition: decoder.cc:10215
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F16(MachInst)
Definition: decoder.cc:9765
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_INTERP_P2_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P2_F32(MachInst)
Definition: decoder.cc:6152
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F64(MachInst)
Definition: decoder.cc:4436
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X
Definition: instructions.hh:35639
gem5::Gcn3ISA::Inst_DS__DS_INC_RTN_U32
Definition: instructions.hh:31545
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F32_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_I32(MachInst)
Definition: decoder.cc:5438
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_XOR_B32
GPUStaticInst * decode_OP_SOP2__S_XOR_B32(MachInst)
Definition: decoder.cc:3644
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX16
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX16(MachInst)
Definition: decoder.cc:8439
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F16(MachInst)
Definition: decoder.cc:4118
gem5::Gcn3ISA::Inst_VOP2__V_MIN_I32
Definition: instructions.hh:6551
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I64(MachInst)
Definition: decoder.cc:10653
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F16(MachInst)
Definition: decoder.cc:4040
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_DEC
Definition: instructions.hh:37015
gem5::Gcn3ISA::Inst_VOP2__V_MUL_HI_I32_I24
Definition: instructions.hh:6381
gem5::Gcn3ISA::Inst_DS__DS_SUB_SRC2_U64
Definition: instructions.hh:34779
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GT_I32
Definition: instructions.hh:15529
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MED3_F32
GPUStaticInst * decode_OPU_VOP3__V_MED3_F32(MachInst)
Definition: decoder.cc:5984
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LE_I16
Definition: instructions.hh:14407
gem5::Gcn3ISA::InFmt_VOPC::OP
unsigned int OP
Definition: gpu_decoder.hh:1605
gem5::GPUStaticInst
Definition: gpu_static_inst.hh:63
gem5::Gcn3ISA::Inst_SOP2__S_ADD_I32
Definition: instructions.hh:115
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_U16_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_U16_F16(MachInst)
Definition: decoder.cc:5744
gem5::Gcn3ISA::Inst_VOP3__V_BCNT_U32_B32
Definition: instructions.hh:30221
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER(MachInst)
Definition: decoder.cc:9129
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NLG_F16
Definition: instructions.hh:17671
gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_SMAX
Definition: instructions.hh:38725
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_LG_U64
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_U64(MachInst)
Definition: decoder.cc:8973
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX_F32
GPUStaticInst * decode_OPU_VOP3__V_MAX_F32(MachInst)
Definition: decoder.cc:5192
gem5::Gcn3ISA::Inst_DS__DS_MIN_RTN_U32
Definition: instructions.hh:31681
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_INC
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_INC(MachInst)
Definition: decoder.cc:7340
gem5::Gcn3ISA::Inst_SOP1__S_XNOR_SAVEEXEC_B64
Definition: instructions.hh:3429
gem5::Gcn3ISA::InstFormat::iFmt_SOP1
InFmt_SOP1 iFmt_SOP1
Definition: gpu_decoder.hh:1658
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F32(MachInst)
Definition: decoder.cc:9849
gem5::Gcn3ISA::Inst_VOP1__V_TRUNC_F32
Definition: instructions.hh:8825
gem5::Gcn3ISA::Inst_SOP2__S_ABSDIFF_I32
Definition: instructions.hh:1475
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_CMPST_B32
GPUStaticInst * decode_OP_DS__DS_CMPST_B32(MachInst)
Definition: decoder.cc:6422
gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_ADD
Definition: instructions.hh:38589
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_LOAD_UBYTE
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_UBYTE(MachInst)
Definition: decoder.cc:7190
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE2ST64_B64
GPUStaticInst * decode_OP_DS__DS_WRITE2ST64_B64(MachInst)
Definition: decoder.cc:6752
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U16(MachInst)
Definition: decoder.cc:4724
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FMA_F64
GPUStaticInst * decode_OPU_VOP3__V_FMA_F64(MachInst)
Definition: decoder.cc:5924
gem5::Gcn3ISA::Decoder::subDecode_OP_MTBUF
GPUStaticInst * subDecode_OP_MTBUF(MachInst)
Definition: decoder.cc:3220
gem5::Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X
Definition: instructions.hh:37975
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U32(MachInst)
Definition: decoder.cc:10575
gem5::Gcn3ISA::Inst_VOP1__V_CLREXCP
Definition: instructions.hh:9625
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GT_F32
Definition: instructions.hh:12265
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_MOV_B32
GPUStaticInst * decode_OP_SOP1__S_MOV_B32(MachInst)
Definition: decoder.cc:8559
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LE_F16
Definition: instructions.hh:11143
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_RNDNE_F16
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F16(MachInst)
Definition: decoder.cc:5816
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_U_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F64(MachInst)
Definition: decoder.cc:10089
gem5::Gcn3ISA::Inst_SOP1__S_CBRANCH_JOIN
Definition: instructions.hh:3653
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_MAX_U32
GPUStaticInst * decode_OP_SOP2__S_MAX_U32(MachInst)
Definition: decoder.cc:3602
gem5::Gcn3ISA::Inst_VOP3__V_CLREXCP
Definition: instructions.hh:27171
gem5::Gcn3ISA::Inst_SOP1__S_GETPC_B64
Definition: instructions.hh:3079
gem5::Gcn3ISA::Inst_VOP3__V_FRACT_F16
Definition: instructions.hh:27679
gem5::Gcn3ISA::Inst_SOP2__S_SUB_I32
Definition: instructions.hh:149
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_ORDERED_COUNT
GPUStaticInst * decode_OP_DS__DS_ORDERED_COUNT(MachInst)
Definition: decoder.cc:7070
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_GE_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GE_U32(MachInst)
Definition: decoder.cc:3878
gem5::Gcn3ISA::Inst_VOP3__V_MOV_B32
Definition: instructions.hh:25539
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_RFE_RESTORE_B64
GPUStaticInst * decode_OP_SOP2__S_RFE_RESTORE_B64(MachInst)
Definition: decoder.cc:3806
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_AND
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_AND(MachInst)
Definition: decoder.cc:8307
gem5::Gcn3ISA::Inst_VOP3__V_CMP_EQ_I64
Definition: instructions.hh:22839
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_WAITCNT
GPUStaticInst * decode_OP_SOPP__S_WAITCNT(MachInst)
Definition: decoder.cc:9051
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_ORN2_B64
GPUStaticInst * decode_OP_SOP2__S_ORN2_B64(MachInst)
Definition: decoder.cc:3674
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LG_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F16(MachInst)
Definition: decoder.cc:9687
gem5::Gcn3ISA::Decoder::tableSubDecode_OP_FLAT
static IsaDecodeMethod tableSubDecode_OP_FLAT[128]
Definition: gpu_decoder.hh:66
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_PCK(MachInst)
Definition: decoder.cc:7442
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_RTN_U32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_U32(MachInst)
Definition: decoder.cc:6512
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U16(MachInst)
Definition: decoder.cc:10293
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2
Definition: instructions.hh:37303
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_NOR_B32
GPUStaticInst * decode_OP_SOP2__S_NOR_B32(MachInst)
Definition: decoder.cc:3692
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_GWS_SEMA_V
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_V(MachInst)
Definition: decoder.cc:7034
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_LZ
Definition: instructions.hh:39215
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I16(MachInst)
Definition: decoder.cc:10341
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_CLASS_F16
Definition: instructions.hh:10463
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F16(MachInst)
Definition: decoder.cc:9789
gem5::Gcn3ISA::Inst_VOP3__V_CMP_EQ_F64
Definition: instructions.hh:19575
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_LOAD_DWORD
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORD(MachInst)
Definition: decoder.cc:8415
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_ADD_X2
Definition: instructions.hh:42341
gem5::Gcn3ISA::Inst_SOP2__S_CSELECT_B32
Definition: instructions.hh:387
gem5::Gcn3ISA::Inst_VOP3__V_FFBH_U32
Definition: instructions.hh:26915
gem5::Gcn3ISA::Inst_VOP1__V_FLOOR_F64
Definition: instructions.hh:8761
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY(MachInst)
Definition: decoder.cc:8067
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_RTN_F32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_F32(MachInst)
Definition: decoder.cc:6578
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_BFI_B32
GPUStaticInst * decode_OPU_VOP3__V_BFI_B32(MachInst)
Definition: decoder.cc:5912
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_MOVRELD_B32
GPUStaticInst * decode_OP_SOP1__S_MOVRELD_B32(MachInst)
Definition: decoder.cc:8823
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_F16
GPUStaticInst * decode_OPU_VOP3__V_MAD_F16(MachInst)
Definition: decoder.cc:6104
gem5::Gcn3ISA::Inst_VOP3__V_LOG_LEGACY_F32
Definition: instructions.hh:27807
gem5::Gcn3ISA::InstFormat::iFmt_VOP2
InFmt_VOP2 iFmt_VOP2
Definition: gpu_decoder.hh:1665
gem5::Gcn3ISA::Inst_DS__DS_AND_SRC2_B64
Definition: instructions.hh:35019
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_RTN_I64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_I64(MachInst)
Definition: decoder.cc:6818
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE_B8
GPUStaticInst * decode_OP_DS__DS_WRITE_B8(MachInst)
Definition: decoder.cc:6458
gem5::Gcn3ISA::Inst_VOP1__V_EXP_LEGACY_F32
Definition: instructions.hh:10229
gem5::Gcn3ISA::Inst_VOP2__V_MIN_U16
Definition: instructions.hh:7831
gem5::Gcn3ISA::Inst_VOP1__V_EXP_F32
Definition: instructions.hh:8953
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SWAP
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:7274
gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_CMPSWAP
Definition: instructions.hh:38555
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CEIL_F16
GPUStaticInst * decode_OP_VOP1__V_CEIL_F16(MachInst)
Definition: decoder.cc:9573
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_F64(MachInst)
Definition: decoder.cc:5498
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LG_F32
Definition: instructions.hh:18589
gem5::Gcn3ISA::Inst_SOP1__S_BITSET0_B32
Definition: instructions.hh:2951
gem5::Gcn3ISA::Inst_VOP2__V_SUB_U32
Definition: instructions.hh:7029
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_AND_B64
GPUStaticInst * decode_OP_SOP2__S_AND_B64(MachInst)
Definition: decoder.cc:3626
gem5::Gcn3ISA::Inst_VOP3__V_SIN_F16
Definition: instructions.hh:27711
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_U_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F16(MachInst)
Definition: decoder.cc:4022
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MIN_U16
GPUStaticInst * decode_OP_VOP2__V_MIN_U16(MachInst)
Definition: decoder.cc:3530
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_O_F32
Definition: instructions.hh:12367
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U16(MachInst)
Definition: decoder.cc:4634
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_RTN_U64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_U64(MachInst)
Definition: decoder.cc:6824
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_LOG_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_LOG_LEGACY_F32(MachInst)
Definition: decoder.cc:5846
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_ALIGNBYTE_B32
GPUStaticInst * decode_OPU_VOP3__V_ALIGNBYTE_B32(MachInst)
Definition: decoder.cc:5942
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LT_U64
Definition: instructions.hh:16787
gem5::Gcn3ISA::Inst_VOP3__V_CVT_F16_I16
Definition: instructions.hh:27231
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_EQ_U32
Definition: instructions.hh:22567
gem5::Gcn3ISA::Inst_DS__DS_XOR_RTN_B32
Definition: instructions.hh:31817
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_ADD_U32
GPUStaticInst * decode_OP_VOP2__V_ADD_U32(MachInst)
Definition: decoder.cc:3386
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_INC
Definition: instructions.hh:42199
gem5::Gcn3ISA::Inst_DS__DS_BPERMUTE_B32
Definition: instructions.hh:32491
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_FF1_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FF1_I32_B64(MachInst)
Definition: decoder.cc:8661
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GT_U64
Definition: instructions.hh:16889
gem5::Gcn3ISA::Inst_VOP1__V_CVT_F16_I16
Definition: instructions.hh:9685
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_FRACT_F16
GPUStaticInst * decode_OP_VOP1__V_FRACT_F16(MachInst)
Definition: decoder.cc:9591
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_L
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_L(MachInst)
Definition: decoder.cc:7778
gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_SSHORT
Definition: instructions.hh:41443
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GE_U32
Definition: instructions.hh:15325
gem5::Gcn3ISA::Inst_SOP2__S_CBRANCH_G_FORK
Definition: instructions.hh:1441
gem5::Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X(MachInst)
Definition: decoder.cc:7964
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GT_U32
Definition: instructions.hh:22635
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_LDEXP_F32
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F32(MachInst)
Definition: decoder.cc:6230
gem5::Gcn3ISA::Inst_VOP3__V_CMP_U_F64
Definition: instructions.hh:19779
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SQRT_F16
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F16(MachInst)
Definition: decoder.cc:5762
gem5::Gcn3ISA::Inst_VOP3__V_LSHRREV_B16
Definition: instructions.hh:25205
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORD
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORD(MachInst)
Definition: decoder.cc:7250
gem5::Gcn3ISA::Decoder::subDecode_OP_SOPP
GPUStaticInst * subDecode_OP_SOPP(MachInst)
Definition: decoder.cc:3164
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SQRT_F64
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F64(MachInst)
Definition: decoder.cc:5648
gem5::Gcn3ISA::Decoder::tableSubDecode_OP_SMEM
static IsaDecodeMethod tableSubDecode_OP_SMEM[64]
Definition: gpu_decoder.hh:70
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MQSAD_U32_U8
GPUStaticInst * decode_OPU_VOP3__V_MQSAD_U32_U8(MachInst)
Definition: decoder.cc:6086
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MAX_I32
GPUStaticInst * decode_OP_VOP2__V_MAX_I32(MachInst)
Definition: decoder.cc:3314
gem5::Gcn3ISA::Decoder::subDecode_OP_FLAT
GPUStaticInst * subDecode_OP_FLAT(MachInst)
Definition: decoder.cc:3204
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U64(MachInst)
Definition: decoder.cc:4982
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LT_I64
Definition: instructions.hh:15971
gem5::Gcn3ISA::Inst_SOP1__S_FLBIT_I32
Definition: instructions.hh:2823
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F32(MachInst)
Definition: decoder.cc:4346
gem5::Gcn3ISA::InstFormat::iFmt_MIMG
InFmt_MIMG iFmt_MIMG
Definition: gpu_decoder.hh:1650
gem5::Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:8018
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP
Definition: instructions.hh:41853
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_I64
GPUStaticInst * decode_OP_DS__DS_MIN_I64(MachInst)
Definition: decoder.cc:6692
gem5::Gcn3ISA::Inst_DS__DS_APPEND
Definition: instructions.hh:34685
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O(MachInst)
Definition: decoder.cc:7904
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_EXP_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_EXP_LEGACY_F32(MachInst)
Definition: decoder.cc:5840
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_OR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_OR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:8757
gem5::Gcn3ISA::Inst_VOP3__V_XOR_B32
Definition: instructions.hh:24575
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MAD_I32_I24(MachInst)
Definition: decoder.cc:5864
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_SENDMSG
GPUStaticInst * decode_OP_SOPP__S_SENDMSG(MachInst)
Definition: decoder.cc:9075
gem5::Gcn3ISA::Inst_VOP3__V_MIN_U16
Definition: instructions.hh:25409
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_D_CL_O
Definition: instructions.hh:39647
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_DCACHE_WB
GPUStaticInst * decode_OP_SMEM__S_DCACHE_WB(MachInst)
Definition: decoder.cc:8517
gem5::Gcn3ISA::Inst_SOP1__S_ORN2_SAVEEXEC_B64
Definition: instructions.hh:3333
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_XOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_XOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:8763
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ
Definition: instructions.hh:35411
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LT_F64
Definition: instructions.hh:12707
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NE_U64
Definition: instructions.hh:23213
gem5::Gcn3ISA::Inst_VOP3__V_INTERP_P1_F32
Definition: instructions.hh:29639
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_O(MachInst)
Definition: decoder.cc:7700
gem5::Gcn3ISA::Inst_VOP3__V_NOP
Definition: instructions.hh:25511
gem5::Gcn3ISA::Inst_SOP2__S_LSHL_B64
Definition: instructions.hh:1033
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_GT_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GT_U32(MachInst)
Definition: decoder.cc:3872
gem5::Gcn3ISA::Inst_VOPC__V_CMP_CLASS_F32
Definition: instructions.hh:10293
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMIN
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:8283
gem5::Gcn3ISA::Inst_VOP3__V_SUB_U32
Definition: instructions.hh:24679
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_EQ_I32
Definition: instructions.hh:22295
gem5::Gcn3ISA::Inst_DS__DS_WRITE_B64
Definition: instructions.hh:32941
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_STORE_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORDX4(MachInst)
Definition: decoder.cc:8487
gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_OR
Definition: instructions.hh:38827
gem5::Gcn3ISA::Inst_DS__DS_READ_B32
Definition: instructions.hh:32191
gem5::Gcn3ISA::Inst_VOP1__V_CEIL_F64
Definition: instructions.hh:8697
gem5::Gcn3ISA::Inst_VOP3__V_FREXP_EXP_I16_F16
Definition: instructions.hh:27519
gem5::Gcn3ISA::Inst_VOPC__V_CMP_F_U32
Definition: instructions.hh:15121
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_GE_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_GE_I32(MachInst)
Definition: decoder.cc:8877
gem5::Gcn3ISA::Inst_VOP3__V_CVT_FLR_I32_F32
Definition: instructions.hh:25891
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I32(MachInst)
Definition: decoder.cc:4766
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I16(MachInst)
Definition: decoder.cc:10233
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_SMIN
Definition: instructions.hh:36727
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LE_I32
Definition: instructions.hh:14951
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_READ_U8
GPUStaticInst * decode_OP_DS__DS_READ_U8(MachInst)
Definition: decoder.cc:6626
gem5::Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:8024
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F32(MachInst)
Definition: decoder.cc:9927
gem5::Gcn3ISA::InFmt_SOPC
Definition: gpu_decoder.hh:1523
gem5::Gcn3ISA::Inst_DS__DS_WRXCHG2ST64_RTN_B64
Definition: instructions.hh:33681
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GT_I32
Definition: instructions.hh:22363
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I16(MachInst)
Definition: decoder.cc:4574
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_AND
Definition: instructions.hh:36871
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_LT_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LT_I32(MachInst)
Definition: decoder.cc:8883
gem5::Gcn3ISA::Decoder::decode_OP_VINTRP__V_INTERP_P2_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_P2_F32(MachInst)
Definition: decoder.cc:9165
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_CL_O(MachInst)
Definition: decoder.cc:7880
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_NOR_B64
GPUStaticInst * decode_OP_SOP2__S_NOR_B64(MachInst)
Definition: decoder.cc:3698
gem5::Gcn3ISA::Inst_DS__DS_READ_B64
Definition: instructions.hh:33851
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U64(MachInst)
Definition: decoder.cc:10797
gem5::Gcn3ISA::Inst_VOP1__V_MOV_B32
Definition: instructions.hh:7961
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NEQ_F64
Definition: instructions.hh:20493
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I16(MachInst)
Definition: decoder.cc:4676
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NLG_F64
Definition: instructions.hh:20391
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_EQ_F32
Definition: instructions.hh:19031
gem5::Gcn3ISA::Inst_VOPC__V_CMP_F_I64
Definition: instructions.hh:15937
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_SETPC_B64
GPUStaticInst * decode_OP_SOP1__S_SETPC_B64(MachInst)
Definition: decoder.cc:8733
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SMIN_X2
Definition: instructions.hh:42413
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_ICACHE_INV
GPUStaticInst * decode_OP_SOPP__S_ICACHE_INV(MachInst)
Definition: decoder.cc:9093
gem5::Gcn3ISA::Decoder::decode_OP_EXP
GPUStaticInst * decode_OP_EXP(MachInst)
Definition: decoder.cc:3932
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_GWS_INIT
GPUStaticInst * decode_OP_DS__DS_GWS_INIT(MachInst)
Definition: decoder.cc:7028
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U64(MachInst)
Definition: decoder.cc:5018
gem5::Gcn3ISA::Inst_SOPC__S_BITCMP1_B64
Definition: instructions.hh:4261
gem5::Gcn3ISA::Inst_VOP2__V_MIN_U32
Definition: instructions.hh:6619
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U32(MachInst)
Definition: decoder.cc:10491
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LE_F32
Definition: instructions.hh:11687
gem5::Gcn3ISA::Inst_VOP3__V_CVT_F64_U32
Definition: instructions.hh:26179
gem5::Gcn3ISA::Inst_VOPC__V_CMP_O_F64
Definition: instructions.hh:12911
gem5::Gcn3ISA::Inst_VOPC__V_CMP_F_F64
Definition: instructions.hh:12673
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GT_F32
Definition: instructions.hh:19099
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_BYTE
Definition: instructions.hh:36255
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_BFE_U64
GPUStaticInst * decode_OP_SOP2__S_BFE_U64(MachInst)
Definition: decoder.cc:3782
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LG_F16
Definition: instructions.hh:18045
gem5::Gcn3ISA::Inst_DS__DS_WRXCHG_RTN_B32
Definition: instructions.hh:31885
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX3_I32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_I32(MachInst)
Definition: decoder.cc:5972
gem5::Gcn3ISA::Inst_VOP1__V_CVT_F64_U32
Definition: instructions.hh:8633
gem5::Gcn3ISA::Inst_SOP2__S_ADD_U32
Definition: instructions.hh:47
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_DEC_U32
GPUStaticInst * decode_OP_DS__DS_DEC_U32(MachInst)
Definition: decoder.cc:6350
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F64(MachInst)
Definition: decoder.cc:4364
gem5::Gcn3ISA::InFmt_VOP1::OP
unsigned int OP
Definition: gpu_decoder.hh:1559
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_ORN2_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ORN2_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:8775
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_CLASS_F16
Definition: instructions.hh:17297
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_INTERP_P1LL_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1LL_F16(MachInst)
Definition: decoder.cc:6164
gem5::Gcn3ISA::InstFormat::iFmt_FLAT
InFmt_FLAT iFmt_FLAT
Definition: gpu_decoder.hh:1647
gem5::Gcn3ISA::Inst_VOP2__V_XOR_B32
Definition: instructions.hh:6857
gem5::Gcn3ISA::Inst_VOP1__V_RNDNE_F32
Definition: instructions.hh:8889
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:7352
gem5::Gcn3ISA::Inst_VOP3__V_FLOOR_F64
Definition: instructions.hh:26307
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_O_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F64(MachInst)
Definition: decoder.cc:10179
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I32_F32
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I32_F32(MachInst)
Definition: decoder.cc:9483
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_LE_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LE_I32(MachInst)
Definition: decoder.cc:8889
gem5::Gcn3ISA::Inst_SOPC__S_CMP_EQ_I32
Definition: instructions.hh:3781
gem5::Gcn3ISA::InFmt_VOP3::OP
unsigned int OP
Definition: gpu_decoder.hh:1579
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_OR
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_OR(MachInst)
Definition: decoder.cc:8313
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U64(MachInst)
Definition: decoder.cc:5096
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U64(MachInst)
Definition: decoder.cc:10779
gem5::Gcn3ISA::Inst_VOP3__V_NOT_B32
Definition: instructions.hh:26851
gem5::Gcn3ISA::Inst_VOP1__V_SIN_F16
Definition: instructions.hh:10165
gem5::Gcn3ISA::Inst_SOP2__S_ADDC_U32
Definition: instructions.hh:183
gem5::Gcn3ISA::Inst_VOP1__V_CVT_F32_UBYTE1
Definition: instructions.hh:8505
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NGE_F64
Definition: instructions.hh:20357
gem5::Gcn3ISA::Inst_VOP3__V_SAD_U8
Definition: instructions.hh:28739
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F64(MachInst)
Definition: decoder.cc:10149
gem5::Gcn3ISA::Inst_SOP1__S_FF1_I32_B32
Definition: instructions.hh:2695
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F64_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_F32(MachInst)
Definition: decoder.cc:5504
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_CMPST_B64
GPUStaticInst * decode_OP_DS__DS_CMPST_B64(MachInst)
Definition: decoder.cc:6758
gem5::Gcn3ISA::Inst_SOPK__S_CMPK_LG_I32
Definition: instructions.hh:1639
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_OR_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_OR_SRC2_B64(MachInst)
Definition: decoder.cc:7136
gem5::Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW(MachInst)
Definition: decoder.cc:8006
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_BYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_BYTE(MachInst)
Definition: decoder.cc:8205
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NEQ_F32
Definition: instructions.hh:12571
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F16(MachInst)
Definition: decoder.cc:9711
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I64
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I64(MachInst)
Definition: decoder.cc:6278
gem5::Gcn3ISA::Inst_SOPP__S_CBRANCH_SCC1
Definition: instructions.hh:4571
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F64(MachInst)
Definition: decoder.cc:3950
gem5::Gcn3ISA::Inst_VOP2__V_SUBREV_U32
Definition: instructions.hh:7065
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_T_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I16(MachInst)
Definition: decoder.cc:10371
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_INC_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_INC_SRC2_U32(MachInst)
Definition: decoder.cc:6944
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_FRACT_F32
GPUStaticInst * decode_OP_VOP1__V_FRACT_F32(MachInst)
Definition: decoder.cc:9339
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_SRC2_I64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_I64(MachInst)
Definition: decoder.cc:7112
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U64(MachInst)
Definition: decoder.cc:10701
gem5::Gcn3ISA::Inst_VOP3__V_WRITELANE_B32
Definition: instructions.hh:30187
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_U_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F16(MachInst)
Definition: decoder.cc:9801
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U32(MachInst)
Definition: decoder.cc:10581
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I64(MachInst)
Definition: decoder.cc:4964
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_LSHRREV_B32
GPUStaticInst * decode_OP_VOP2__V_LSHRREV_B32(MachInst)
Definition: decoder.cc:3332
gem5::Gcn3ISA::Inst_VOP3__V_MIN_U32
Definition: instructions.hh:24337
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_RTN_I32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_I32(MachInst)
Definition: decoder.cc:6506
gem5::Gcn3ISA::Inst_SOPK__S_ADDK_I32
Definition: instructions.hh:1991
gem5::Gcn3ISA::Inst_SOP2__S_SUB_U32
Definition: instructions.hh:81
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F64(MachInst)
Definition: decoder.cc:10053
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:8367
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NLT_F64
Definition: instructions.hh:19983
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX3_U32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_U32(MachInst)
Definition: decoder.cc:5978
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I64(MachInst)
Definition: decoder.cc:10623
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE2
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE2(MachInst)
Definition: decoder.cc:9291
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I32(MachInst)
Definition: decoder.cc:10521
gem5::Gcn3ISA::Inst_VOP3__V_CMP_EQ_U64
Definition: instructions.hh:23111
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SUB_X2
Definition: instructions.hh:42377
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I64(MachInst)
Definition: decoder.cc:5048
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_BREV_B32
GPUStaticInst * decode_OP_SOP1__S_BREV_B32(MachInst)
Definition: decoder.cc:8607
gem5::Gcn3ISA::Inst_VOP2__V_MADMK_F32
Definition: instructions.hh:6925
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GE_U64
Definition: instructions.hh:16957
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_DEC_U64
GPUStaticInst * decode_OP_DS__DS_DEC_U64(MachInst)
Definition: decoder.cc:6686
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MQSAD_PK_U16_U8
GPUStaticInst * decode_OPU_VOP3__V_MQSAD_PK_U16_U8(MachInst)
Definition: decoder.cc:6080
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_U32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_U32_F64(MachInst)
Definition: decoder.cc:5534
gem5::Gcn3ISA::Decoder::tableSubDecode_OP_MTBUF
static IsaDecodeMethod tableSubDecode_OP_MTBUF[16]
Definition: gpu_decoder.hh:68
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_EXECZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_EXECZ(MachInst)
Definition: decoder.cc:9027
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_EXP_F32
GPUStaticInst * decode_OPU_VOP3__V_EXP_F32(MachInst)
Definition: decoder.cc:5600
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_GWS_SEMA_BR
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_BR(MachInst)
Definition: decoder.cc:7040
gem5::Gcn3ISA::Inst_VOP3__V_AND_B32
Definition: instructions.hh:24507
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I64(MachInst)
Definition: decoder.cc:10629
gem5::Gcn3ISA::Inst_VOP3__V_MAX_F16
Definition: instructions.hh:25273
gem5::Gcn3ISA::Inst_DS__DS_WRXCHG2_RTN_B64
Definition: instructions.hh:33647
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_INCPERFLEVEL
GPUStaticInst * decode_OP_SOPP__S_INCPERFLEVEL(MachInst)
Definition: decoder.cc:9099
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_LT_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LT_I32(MachInst)
Definition: decoder.cc:3848
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GE_U16
Definition: instructions.hh:21615
gem5::Gcn3ISA::Inst_VOP3__V_SQRT_F16
Definition: instructions.hh:27359
gem5::Gcn3ISA::Inst_VOP3__V_LSHLREV_B16
Definition: instructions.hh:25171
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_PK_U8_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_U8_F32(MachInst)
Definition: decoder.cc:6026
gem5::Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ
Definition: instructions.hh:37747
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUBREV_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_U32(MachInst)
Definition: decoder.cc:5276
gem5::Gcn3ISA::Inst_VOP1__V_FREXP_MANT_F16
Definition: instructions.hh:9941
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_LZ(MachInst)
Definition: decoder.cc:7664
gem5::Gcn3ISA::Inst_VOP3__V_BFE_I32
Definition: instructions.hh:28163
gem5::Gcn3ISA::Inst_DS__DS_DEC_RTN_U64
Definition: instructions.hh:33307
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_READ2ST64_B32
GPUStaticInst * decode_OP_DS__DS_READ2ST64_B32(MachInst)
Definition: decoder.cc:6614
gem5::Gcn3ISA::Inst_VOP3__V_MAX_I16
Definition: instructions.hh:25375
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F32(MachInst)
Definition: decoder.cc:6032
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F16(MachInst)
Definition: decoder.cc:9831
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:8457
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U64(MachInst)
Definition: decoder.cc:10773
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_AND_X2
Definition: instructions.hh:37339
gem5::Gcn3ISA::Inst_VOP1__V_RNDNE_F64
Definition: instructions.hh:8729
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LT_I64
Definition: instructions.hh:22805
gem5::Gcn3ISA::Inst_DS__DS_MAX_SRC2_I64
Definition: instructions.hh:34929
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRXCHG2ST64_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG2ST64_RTN_B32(MachInst)
Definition: decoder.cc:6560
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_BITSET1_B64
GPUStaticInst * decode_OP_SOP1__S_BITSET1_B64(MachInst)
Definition: decoder.cc:8721
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X(MachInst)
Definition: decoder.cc:8061
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_UMIN
Definition: instructions.hh:36763
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_O_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F32(MachInst)
Definition: decoder.cc:9891
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_DEC
Definition: instructions.hh:42235
gem5::Gcn3ISA::Inst_DS__DS_MSKOR_RTN_B64
Definition: instructions.hh:33579
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I32(MachInst)
Definition: decoder.cc:10557
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NE_U64
Definition: instructions.hh:23757
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_GT_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GT_I32(MachInst)
Definition: decoder.cc:3836
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LT_F64
Definition: instructions.hh:19541
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_F_U64
Definition: instructions.hh:16753
gem5::Gcn3ISA::Inst_VOP3__V_MSAD_U8
Definition: instructions.hh:29141
gem5::Gcn3ISA::Inst_SOP1__S_SEXT_I32_I8
Definition: instructions.hh:2887
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C(MachInst)
Definition: decoder.cc:7802
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B(MachInst)
Definition: decoder.cc:7784
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MSKOR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_MSKOR_RTN_B32(MachInst)
Definition: decoder.cc:6542
gem5::Gcn3ISA::Inst_VOP3__V_CVT_F32_I32
Definition: instructions.hh:25635
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O
Definition: instructions.hh:41267
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_U_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F32(MachInst)
Definition: decoder.cc:4214
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:8397
gem5::Gcn3ISA::Inst_DS__DS_MAX_SRC2_F64
Definition: instructions.hh:35169
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I32(MachInst)
Definition: decoder.cc:4874
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_F32
GPUStaticInst * decode_OP_DS__DS_MIN_F32(MachInst)
Definition: decoder.cc:6434
gem5::Gcn3ISA::Inst_VOP1__V_CVT_F32_I32
Definition: instructions.hh:8089
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_BITSET1_B32
GPUStaticInst * decode_OP_SOP1__S_BITSET1_B32(MachInst)
Definition: decoder.cc:8715
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_T_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I32(MachInst)
Definition: decoder.cc:4784
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS(MachInst)
Definition: decoder.cc:9117
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_WAKEUP
GPUStaticInst * decode_OP_SOPP__S_WAKEUP(MachInst)
Definition: decoder.cc:8997
gem5::Gcn3ISA::Inst_VOP1__V_FRACT_F64
Definition: instructions.hh:9529
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_BITCMP0_B64
GPUStaticInst * decode_OP_SOPC__S_BITCMP0_B64(MachInst)
Definition: decoder.cc:8943
gem5::Gcn3ISA::Inst_VOP1__V_LOG_LEGACY_F32
Definition: instructions.hh:10261
gem5::Gcn3ISA::Inst_SOP1__S_WQM_B64
Definition: instructions.hh:2407
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_LZ_O
Definition: instructions.hh:39791
gem5::Gcn3ISA::Inst_DS__DS_DEC_SRC2_U32
Definition: instructions.hh:34107
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NE_I16
Definition: instructions.hh:13931
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LT_I16
Definition: instructions.hh:13795
gem5::Gcn3ISA::Inst_VOP3__V_CVT_PKNORM_I16_F32
Definition: instructions.hh:30493
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LE_I32
Definition: instructions.hh:21785
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B16
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B16(MachInst)
Definition: decoder.cc:5354
gem5::Gcn3ISA::Inst_SOP1__S_SWAPPC_B64
Definition: instructions.hh:3141
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GE_I16
Definition: instructions.hh:21343
gem5::Gcn3ISA::Inst_VOPC__V_CMP_T_I64
Definition: instructions.hh:16175
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_T_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U32(MachInst)
Definition: decoder.cc:10515
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_RFE_B64
GPUStaticInst * decode_OP_SOP1__S_RFE_B64(MachInst)
Definition: decoder.cc:8745
gem5::Gcn3ISA::Inst_VOP3__V_SUBREV_F32
Definition: instructions.hh:23963
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FRACT_F64
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F64(MachInst)
Definition: decoder.cc:5708
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_L_O(MachInst)
Definition: decoder.cc:7694
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_ABS_I32
GPUStaticInst * decode_OP_SOP1__S_ABS_I32(MachInst)
Definition: decoder.cc:8841
gem5::Gcn3ISA::Inst_VOP3__V_SUBB_U32
Definition: instructions.hh:24789
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I64(MachInst)
Definition: decoder.cc:10713
gem5::Gcn3ISA::InFmt_FLAT::OP
unsigned int OP
Definition: gpu_decoder.hh:1399
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_COS_F32
GPUStaticInst * decode_OPU_VOP3__V_COS_F32(MachInst)
Definition: decoder.cc:5660
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MSKOR_B64
GPUStaticInst * decode_OP_DS__DS_MSKOR_B64(MachInst)
Definition: decoder.cc:6734
gem5::Gcn3ISA::Inst_VOP2__V_AND_B32
Definition: instructions.hh:6789
gem5::Gcn3ISA::Decoder::decode_OP_VINTRP__V_INTERP_MOV_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_MOV_F32(MachInst)
Definition: decoder.cc:9171
gem5::Gcn3ISA::Inst_DS__DS_RSUB_SRC2_U32
Definition: instructions.hh:34047
gem5::Gcn3ISA::Inst_VOP2__V_MAX_F16
Definition: instructions.hh:7695
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LE_F32
Definition: instructions.hh:18521
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I32(MachInst)
Definition: decoder.cc:4742
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_RTN_F64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_F64(MachInst)
Definition: decoder.cc:6890
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LT_F16
Definition: instructions.hh:10531
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_FF1_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FF1_I32_B32(MachInst)
Definition: decoder.cc:8655
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GE_F16
Definition: instructions.hh:18079
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_NOT_B32
GPUStaticInst * decode_OPU_VOP3__V_NOT_B32(MachInst)
Definition: decoder.cc:5666
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUB_F32
GPUStaticInst * decode_OPU_VOP3__V_SUB_F32(MachInst)
Definition: decoder.cc:5138
gem5::Gcn3ISA::Inst_VOP2__V_MAX_I16
Definition: instructions.hh:7797
gem5::Gcn3ISA::Inst_VOP3__V_ASHRREV_I32
Definition: instructions.hh:24439
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NE_I64
Definition: instructions.hh:23485
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_F_I64
Definition: instructions.hh:16481
gem5::Gcn3ISA::Inst_DS__DS_MAX_I32
Definition: instructions.hh:30855
gem5::Gcn3ISA::Inst_VOP1__V_NOT_B32
Definition: instructions.hh:9305
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F16(MachInst)
Definition: decoder.cc:4148
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_DEC
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_DEC(MachInst)
Definition: decoder.cc:8331
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_T_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U32(MachInst)
Definition: decoder.cc:10611
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_NOP
GPUStaticInst * decode_OP_SOPP__S_NOP(MachInst)
Definition: decoder.cc:8979
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_CD_CL_O
Definition: instructions.hh:41195
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_SUB_RTN_U64
GPUStaticInst * decode_OP_DS__DS_SUB_RTN_U64(MachInst)
Definition: decoder.cc:6788
gem5::Gcn3ISA::Inst_DS__DS_MSKOR_B32
Definition: instructions.hh:31047
gem5::Gcn3ISA::InFmt_SOP1::ENCODING
unsigned int ENCODING
Definition: gpu_decoder.hh:1511
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NLE_F32
Definition: instructions.hh:11993
gem5::Gcn3ISA::Inst_SOPC__S_SETVSKIP
Definition: instructions.hh:4293
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUBREV_U16
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_U16(MachInst)
Definition: decoder.cc:5342
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_F32(MachInst)
Definition: decoder.cc:7010
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F16(MachInst)
Definition: decoder.cc:4094
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_F_F64
Definition: instructions.hh:13217
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_UBYTE
Definition: instructions.hh:35943
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_SUBREV_F32
GPUStaticInst * decode_OP_VOP2__V_SUBREV_F32(MachInst)
Definition: decoder.cc:3254
gem5::Gcn3ISA::Inst_VOP3__V_MBCNT_HI_U32_B32
Definition: instructions.hh:30289
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_FFBL_B32
GPUStaticInst * decode_OP_VOP1__V_FFBL_B32(MachInst)
Definition: decoder.cc:9453
gem5::Gcn3ISA::Inst_SOPK__S_MULK_I32
Definition: instructions.hh:2023
gem5::Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X(MachInst)
Definition: decoder.cc:7988
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F32(MachInst)
Definition: decoder.cc:4238
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NGE_F16
Definition: instructions.hh:10803
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U64(MachInst)
Definition: decoder.cc:10677
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_SUB_U16
GPUStaticInst * decode_OP_VOP2__V_SUB_U16(MachInst)
Definition: decoder.cc:3470
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_U64_U32
GPUStaticInst * decode_OPU_VOP3__V_MAD_U64_U32(MachInst)
Definition: decoder.cc:6092
gem5::Gcn3ISA::Inst_DS__DS_MAX_F32
Definition: instructions.hh:31281
gem5::Gcn3ISA::Inst_VOP2__V_SUBREV_F16
Definition: instructions.hh:7283
gem5::Gcn3ISA::Inst_DS__DS_WRITE_SRC2_B64
Definition: instructions.hh:35109
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LE_U16
Definition: instructions.hh:21513
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_I32
Definition: instructions.hh:22227
gem5::Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_X
Definition: instructions.hh:37519
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN_I32
GPUStaticInst * decode_OPU_VOP3__V_MIN_I32(MachInst)
Definition: decoder.cc:5198
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_RPI_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_RPI_I32_F32(MachInst)
Definition: decoder.cc:9249
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SIN_F32
GPUStaticInst * decode_OPU_VOP3__V_SIN_F32(MachInst)
Definition: decoder.cc:5654
gem5::Gcn3ISA::Inst_VOP3__V_DIV_SCALE_F32
Definition: instructions.hh:28991
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_O_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F32(MachInst)
Definition: decoder.cc:9987
gem5::Gcn3ISA::Inst_SOP2__S_RFE_RESTORE_B64
Definition: instructions.hh:1509
gem5::Gcn3ISA::Inst_DS__DS_XOR_B32
Definition: instructions.hh:31015
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_STORE_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_PCK(MachInst)
Definition: decoder.cc:7478
gem5::Gcn3ISA::Inst_SOP2__S_LSHL_B32
Definition: instructions.hh:999
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F64(MachInst)
Definition: decoder.cc:4424
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_TRUNC_F32
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F32(MachInst)
Definition: decoder.cc:9345
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_X
Definition: instructions.hh:35487
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U64(MachInst)
Definition: decoder.cc:5078
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX4
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX4(MachInst)
Definition: decoder.cc:7268
gem5::Gcn3ISA::Inst_VOPC__V_CMP_F_U64
Definition: instructions.hh:16209
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:7394
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_X(MachInst)
Definition: decoder.cc:8085
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_NOP
GPUStaticInst * decode_OP_VOP1__V_NOP(MachInst)
Definition: decoder.cc:9177
gem5::Gcn3ISA::Inst_DS__DS_MIN_SRC2_I64
Definition: instructions.hh:34899
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_F32
Definition: instructions.hh:18963
gem5::Gcn3ISA::Inst_SOPC__S_CMP_EQ_U32
Definition: instructions.hh:3973
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_B_O
Definition: instructions.hh:40007
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I32(MachInst)
Definition: decoder.cc:10449
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_U_F16
Definition: instructions.hh:11313
gem5::Gcn3ISA::Inst_VOP3__V_ASHRREV_I64
Definition: instructions.hh:30391
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GT_I16
Definition: instructions.hh:13897
gem5::Gcn3ISA::Inst_SMEM__S_STORE_DWORDX2
Definition: instructions.hh:5721
gem5::Gcn3ISA::Inst_SOP2__S_BFE_I64
Definition: instructions.hh:1407
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F64(MachInst)
Definition: decoder.cc:10113
gem5::Gcn3ISA::Inst_MIMG__IMAGE_LOAD_MIP_PCK
Definition: instructions.hh:38271
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I16(MachInst)
Definition: decoder.cc:10257
gem5::Gcn3ISA::Inst_VOP1__V_CVT_FLR_I32_F32
Definition: instructions.hh:8345
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_CL(MachInst)
Definition: decoder.cc:7826
gem5::Gcn3ISA::Inst_DS__DS_MAX_RTN_U64
Definition: instructions.hh:33443
gem5::Gcn3ISA::Inst_VOP3__V_COS_F16
Definition: instructions.hh:27743
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U16(MachInst)
Definition: decoder.cc:10413
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F32_U32
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_U32(MachInst)
Definition: decoder.cc:9213
gem5::Gcn3ISA::Inst_DS__DS_MIN_SRC2_F64
Definition: instructions.hh:35139
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U16(MachInst)
Definition: decoder.cc:4712
gem5::Gcn3ISA::Inst_SOP1__S_BCNT1_I32_B64
Definition: instructions.hh:2599
gem5::Gcn3ISA::Inst_DS__DS_SUB_RTN_U64
Definition: instructions.hh:33205
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_MUL_LEGACY_F32(MachInst)
Definition: decoder.cc:5150
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_EQ_I16
Definition: instructions.hh:14373
gem5::Gcn3ISA::Inst_VOP3__V_SUBBREV_U32
Definition: instructions.hh:24827
gem5::Gcn3ISA::Inst_SOP1__S_SETPC_B64
Definition: instructions.hh:3109
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_CBRANCH_I_FORK
GPUStaticInst * decode_OP_SOPK__S_CBRANCH_I_FORK(MachInst)
Definition: decoder.cc:3908
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LE_I16
Definition: instructions.hh:21241
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GT_F16
Definition: instructions.hh:10633
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMAX
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:7316
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_SETVSKIP
GPUStaticInst * decode_OP_SOPC__S_SETVSKIP(MachInst)
Definition: decoder.cc:8955
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX_F64
GPUStaticInst * decode_OPU_VOP3__V_MAX_F64(MachInst)
Definition: decoder.cc:6200
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NLE_F64
Definition: instructions.hh:20459
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_XOR_B32
GPUStaticInst * decode_OP_DS__DS_XOR_B32(MachInst)
Definition: decoder.cc:6392
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_OFF_F32_I4
GPUStaticInst * decode_OPU_VOP3__V_CVT_OFF_F32_I4(MachInst)
Definition: decoder.cc:5492
gem5::Gcn3ISA::Inst_MIMG__IMAGE_LOAD_PCK
Definition: instructions.hh:38199
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NE_U32
Definition: instructions.hh:15835
gem5::Gcn3ISA::InFmt_SMEM::OP
unsigned int OP
Definition: gpu_decoder.hh:1497
gem5::Gcn3ISA::Inst_DS__DS_MAX_U32
Definition: instructions.hh:30919
gem5::Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORD
Definition: instructions.hh:5505
gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_XOR
Definition: instructions.hh:38861
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:8361
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_BRANCH
GPUStaticInst * decode_OP_SOPP__S_BRANCH(MachInst)
Definition: decoder.cc:8991
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_EQ_F16
Definition: instructions.hh:11109
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LE_F16
Definition: instructions.hh:17977
gem5::Gcn3ISA::Inst_VOP1__V_FFBH_I32
Definition: instructions.hh:9433
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_NAND_B32
GPUStaticInst * decode_OP_SOP2__S_NAND_B32(MachInst)
Definition: decoder.cc:3680
gem5::Gcn3ISA::InstFormat::iFmt_SOPC
InFmt_SOPC iFmt_SOPC
Definition: gpu_decoder.hh:1660
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_XOR_B32
GPUStaticInst * decode_OPU_VOP3__V_XOR_B32(MachInst)
Definition: decoder.cc:5252
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_DEC
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_DEC(MachInst)
Definition: decoder.cc:7568
gem5::Gcn3ISA::Decoder::tableSubDecode_OP_MIMG
static IsaDecodeMethod tableSubDecode_OP_MIMG[128]
Definition: gpu_decoder.hh:67
gem5::Gcn3ISA::Inst_VOP3__V_PERM_B32
Definition: instructions.hh:29469
gem5::Gcn3ISA::Inst_SOP1__S_NOR_SAVEEXEC_B64
Definition: instructions.hh:3397
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_BFE_U32
GPUStaticInst * decode_OP_SOP2__S_BFE_U32(MachInst)
Definition: decoder.cc:3770
gem5::Gcn3ISA::Inst_VOP3__V_RNDNE_F32
Definition: instructions.hh:26435
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U32(MachInst)
Definition: decoder.cc:10497
gem5::Gcn3ISA::Inst_DS__DS_NOP
Definition: instructions.hh:31313
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LG_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F32(MachInst)
Definition: decoder.cc:9879
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_LT_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LT_U32(MachInst)
Definition: decoder.cc:8919
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B16
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B16(MachInst)
Definition: decoder.cc:5360
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_U32
Definition: instructions.hh:22499
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_U16
GPUStaticInst * decode_OPU_VOP3__V_MAD_U16(MachInst)
Definition: decoder.cc:6110
gem5::Gcn3ISA::Inst_DS__DS_READ_U8
Definition: instructions.hh:32325
gem5::Gcn3ISA::Inst_DS__DS_READ2ST64_B32
Definition: instructions.hh:32259
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_CL
Definition: instructions.hh:38999
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_EQ_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_EQ_I32(MachInst)
Definition: decoder.cc:3824
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NGT_F32
Definition: instructions.hh:11959
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_U_F64
Definition: instructions.hh:20323
gem5::Gcn3ISA::Inst_DS__DS_MIN_RTN_I32
Definition: instructions.hh:31613
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:8427
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NLE_F16
Definition: instructions.hh:10905
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_ADDK_I32
GPUStaticInst * decode_OP_SOPK__S_ADDK_I32(MachInst)
Definition: decoder.cc:3896
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I16(MachInst)
Definition: decoder.cc:4664
gem5::Gcn3ISA::Inst_SOPP__S_CBRANCH_VCCZ
Definition: instructions.hh:4601
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_ASHR_I64
GPUStaticInst * decode_OP_SOP2__S_ASHR_I64(MachInst)
Definition: decoder.cc:3746
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_HI_U32
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_U32(MachInst)
Definition: decoder.cc:6218
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I16(MachInst)
Definition: decoder.cc:10239
gem5::Gcn3ISA::Inst_DS__DS_SUB_U64
Definition: instructions.hh:32557
gem5::Gcn3ISA::Inst_VOP3__V_CVT_F32_UBYTE1
Definition: instructions.hh:26051
gem5::Gcn3ISA::Inst_DS__DS_MIN_RTN_F32
Definition: instructions.hh:32055
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_O_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F32(MachInst)
Definition: decoder.cc:4208
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_OR_B32
GPUStaticInst * decode_OP_SOP2__S_OR_B32(MachInst)
Definition: decoder.cc:3632
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE1
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE1(MachInst)
Definition: decoder.cc:5516
gem5::Gcn3ISA::Inst_VOP3__V_MAD_F32
Definition: instructions.hh:27875
gem5::Gcn3ISA::Inst_VOP3__V_RCP_IFLAG_F32
Definition: instructions.hh:26595
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_CMPST_RTN_B32
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_B32(MachInst)
Definition: decoder.cc:6566
gem5::Gcn3ISA::Inst_SOPK__S_SETREG_IMM32_B32
Definition: instructions.hh:2151
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_EQ_U64
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_U64(MachInst)
Definition: decoder.cc:8967
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U16(MachInst)
Definition: decoder.cc:10389
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_RTN_I64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_I64(MachInst)
Definition: decoder.cc:6812
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NE_I16
Definition: instructions.hh:20765
gem5::Gcn3ISA::Decoder::subDecode_OP_SOPC
GPUStaticInst * subDecode_OP_SOPC(MachInst)
Definition: decoder.cc:3156
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LT_I16
Definition: instructions.hh:20629
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_SET_GPR_IDX_MODE
GPUStaticInst * decode_OP_SOPP__S_SET_GPR_IDX_MODE(MachInst)
Definition: decoder.cc:9153
gem5::Gcn3ISA::Inst_SOPK__S_CMPK_LE_I32
Definition: instructions.hh:1767
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SBYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SBYTE(MachInst)
Definition: decoder.cc:8163
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_F64
GPUStaticInst * decode_OPU_VOP3__V_MUL_F64(MachInst)
Definition: decoder.cc:6188
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_ADD_X2
Definition: instructions.hh:37123
gem5::Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XY
Definition: instructions.hh:37709
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U32(MachInst)
Definition: decoder.cc:4928
gem5::Gcn3ISA::Inst_SMEM__S_BUFFER_STORE_DWORDX2
Definition: instructions.hh:5829
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F16(MachInst)
Definition: decoder.cc:9693
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_OR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_OR_RTN_B64(MachInst)
Definition: decoder.cc:6842
gem5::Gcn3ISA::Inst_SOP1__S_RFE_B64
Definition: instructions.hh:3173
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MIN_I16
GPUStaticInst * decode_OP_VOP2__V_MIN_I16(MachInst)
Definition: decoder.cc:3536
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LT_F16
Definition: instructions.hh:17365
gem5::Gcn3ISA::Inst_VOP3__V_TRUNC_F64
Definition: instructions.hh:26211
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8(MachInst)
Definition: decoder.cc:8463
gem5::Gcn3ISA::Inst_DS__DS_GWS_BARRIER
Definition: instructions.hh:34621
gem5::Gcn3ISA::InFmt_MUBUF::OP
unsigned int OP
Definition: gpu_decoder.hh:1475
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LT_U64
Definition: instructions.hh:23077
gem5::Gcn3ISA::Inst_SOP1__S_MOVRELD_B32
Definition: instructions.hh:3589
gem5::Gcn3ISA::Inst_SOP1__S_CMOV_B32
Definition: instructions.hh:2247
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_ADD_U32
GPUStaticInst * decode_OPU_VOP3__V_ADD_U32(MachInst)
Definition: decoder.cc:5264
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CL(MachInst)
Definition: decoder.cc:7628
gem5::Gcn3ISA::Inst_SOPP__S_WAKEUP
Definition: instructions.hh:4511
gem5::Gcn3ISA::Inst_SOP2__S_NOR_B64
Definition: instructions.hh:897
gem5::Gcn3ISA::Inst_SOPP__S_TTRACEDATA
Definition: instructions.hh:5085
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F16(MachInst)
Definition: decoder.cc:9663
gem5::Gcn3ISA::Inst_VOP1__V_RCP_IFLAG_F32
Definition: instructions.hh:9049
gem5::Gcn3ISA::Inst_SOP2__S_XOR_B32
Definition: instructions.hh:591
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX3
Definition: instructions.hh:36179
gem5::Gcn3ISA::Inst_VOP1__V_FFBH_U32
Definition: instructions.hh:9369
gem5::Gcn3ISA::Inst_SOPP__S_SETKILL
Definition: instructions.hh:4755
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:8127
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_ASHRREV_I32
GPUStaticInst * decode_OP_VOP2__V_ASHRREV_I32(MachInst)
Definition: decoder.cc:3338
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F64(MachInst)
Definition: decoder.cc:10077
gem5::Gcn3ISA::Inst_VOP3__V_LOG_F32
Definition: instructions.hh:26531
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SSHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SSHORT(MachInst)
Definition: decoder.cc:8175
gem5::Gcn3ISA::Inst_VOP2__V_MAX_U16
Definition: instructions.hh:7763
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_F64
GPUStaticInst * decode_OP_DS__DS_MIN_F64(MachInst)
Definition: decoder.cc:6770
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F16(MachInst)
Definition: decoder.cc:9735
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN(MachInst)
Definition: decoder.cc:7460
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I32(MachInst)
Definition: decoder.cc:4850
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NLE_F32
Definition: instructions.hh:12537
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F32(MachInst)
Definition: decoder.cc:4292
gpu_static_inst.hh
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LE_U32
Definition: instructions.hh:22057
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_INC
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_INC(MachInst)
Definition: decoder.cc:8325
gem5::Gcn3ISA::Inst_VOPC__V_CMP_T_U64
Definition: instructions.hh:16447
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SWAP
Definition: instructions.hh:41817
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUB_U32
GPUStaticInst * decode_OPU_VOP3__V_SUB_U32(MachInst)
Definition: decoder.cc:5270
gem5::Gcn3ISA::Inst_VOP3__V_RNDNE_F64
Definition: instructions.hh:26275
gem5::Gcn3ISA::Inst_VOP1__V_COS_F16
Definition: instructions.hh:10197
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F32(MachInst)
Definition: decoder.cc:9903
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX_F16
GPUStaticInst * decode_OPU_VOP3__V_MAX_F16(MachInst)
Definition: decoder.cc:5372
gem5::Gcn3ISA::Inst_SOPK__S_SETREG_B32
Definition: instructions.hh:2119
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I16(MachInst)
Definition: decoder.cc:4670
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LT_I64
Definition: instructions.hh:16515
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SAD_U16
GPUStaticInst * decode_OPU_VOP3__V_SAD_U16(MachInst)
Definition: decoder.cc:6014
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U32(MachInst)
Definition: decoder.cc:4802
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F32(MachInst)
Definition: decoder.cc:4220
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I64(MachInst)
Definition: decoder.cc:5066
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F64_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_F32(MachInst)
Definition: decoder.cc:9273
gem5::Gcn3ISA::Inst_VOP3__V_FREXP_EXP_I32_F64
Definition: instructions.hh:27011
gem5::Gcn3ISA::Inst_VOP3__V_RCP_F16
Definition: instructions.hh:27327
gem5::Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX8
Definition: instructions.hh:5433
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F16(MachInst)
Definition: decoder.cc:9825
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_SWAP
Definition: instructions.hh:36583
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_U_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F32(MachInst)
Definition: decoder.cc:9993
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GT_I64
Definition: instructions.hh:16617
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_F32(MachInst)
Definition: decoder.cc:7004
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I32_F32(MachInst)
Definition: decoder.cc:5714
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_BFM_B32
GPUStaticInst * decode_OP_SOP2__S_BFM_B32(MachInst)
Definition: decoder.cc:3752
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F64_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_I32(MachInst)
Definition: decoder.cc:5432
gem5::Gcn3ISA::Inst_SOPP__S_CBRANCH_EXECNZ
Definition: instructions.hh:4695
gem5::Gcn3ISA::Decoder::subDecode_OP_SOP1
GPUStaticInst * subDecode_OP_SOP1(MachInst)
Definition: decoder.cc:3148
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CEIL_F64
GPUStaticInst * decode_OP_VOP1__V_CEIL_F64(MachInst)
Definition: decoder.cc:9321
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_OR
Definition: instructions.hh:36907
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GE_I32
Definition: instructions.hh:15053
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GET_RESINFO
GPUStaticInst * decode_OP_MIMG__IMAGE_GET_RESINFO(MachInst)
Definition: decoder.cc:7490
gem5::Gcn3ISA::Inst_VOP3__V_FREXP_EXP_I32_F32
Definition: instructions.hh:27107
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GT_I16
Definition: instructions.hh:20731
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_WBINVL1
GPUStaticInst * decode_OP_MUBUF__BUFFER_WBINVL1(MachInst)
Definition: decoder.cc:8247
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LT_F64
Definition: instructions.hh:13251
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I64(MachInst)
Definition: decoder.cc:5054
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_SQRT_F32
GPUStaticInst * decode_OP_VOP1__V_SQRT_F32(MachInst)
Definition: decoder.cc:9411
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F32(MachInst)
Definition: decoder.cc:4172
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_CMOV_B64
GPUStaticInst * decode_OP_SOP1__S_CMOV_B64(MachInst)
Definition: decoder.cc:8577
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F64(MachInst)
Definition: decoder.cc:4466
gem5::Gcn3ISA::Inst_VOP3__V_MAD_I64_I32
Definition: instructions.hh:29323
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_ENDPGM
GPUStaticInst * decode_OP_SOPP__S_ENDPGM(MachInst)
Definition: decoder.cc:8985
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GT_F64
Definition: instructions.hh:13353
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U64(MachInst)
Definition: decoder.cc:10791
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_RNDNE_F16
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F16(MachInst)
Definition: decoder.cc:9585
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GT_F16
Definition: instructions.hh:17467
gem5::Gcn3ISA::Inst_SOPK__S_CMPK_LG_U32
Definition: instructions.hh:1831
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_RCP_IFLAG_F32
GPUStaticInst * decode_OPU_VOP3__V_RCP_IFLAG_F32(MachInst)
Definition: decoder.cc:5618
gem5::Gcn3ISA::Inst_VOP3__V_MAC_F32
Definition: instructions.hh:24609
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_PCK_SGN
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_PCK_SGN(MachInst)
Definition: decoder.cc:7448
gem5::Gcn3ISA::Inst_VOP3__V_FREXP_MANT_F16
Definition: instructions.hh:27487
gem5::Gcn3ISA::Decoder::tableSubDecode_OP_VOP1
static IsaDecodeMethod tableSubDecode_OP_VOP1[256]
Definition: gpu_decoder.hh:75
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GE_F32
Definition: instructions.hh:11789
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_TRU_F16
Definition: instructions.hh:11551
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_SUBREV_U16
GPUStaticInst * decode_OP_VOP2__V_SUBREV_U16(MachInst)
Definition: decoder.cc:3476
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_HI_I32
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_I32(MachInst)
Definition: decoder.cc:6224
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_DEC_X2
Definition: instructions.hh:37483
gem5::Gcn3ISA::Inst_SOP2__S_BFE_U64
Definition: instructions.hh:1373
gem5::Gcn3ISA::Inst_SOP1__S_AND_SAVEEXEC_B64
Definition: instructions.hh:3205
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE2_B32
GPUStaticInst * decode_OP_DS__DS_WRITE2_B32(MachInst)
Definition: decoder.cc:6410
gem5::Gcn3ISA::Inst_SOP2__S_SUBB_U32
Definition: instructions.hh:217
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NGT_F32
Definition: instructions.hh:12503
gem5::Gcn3ISA::Inst_VOP3__V_BFE_U32
Definition: instructions.hh:28127
gem5::Gcn3ISA::Inst_VOP1__V_READFIRSTLANE_B32
Definition: instructions.hh:7993
gem5::Gcn3ISA::Inst_SOPP__S_SENDMSGHALT
Definition: instructions.hh:4935
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:8145
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D(MachInst)
Definition: decoder.cc:7634
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_U16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_U16_F16(MachInst)
Definition: decoder.cc:9513
gem5::Gcn3ISA::Inst_VOP3__V_MAX_U16
Definition: instructions.hh:25341
gem5::Gcn3ISA::Inst_VOP1__V_CVT_OFF_F32_I4
Definition: instructions.hh:8377
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_O_F32
Definition: instructions.hh:19201
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_U64(MachInst)
Definition: decoder.cc:7076
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U16(MachInst)
Definition: decoder.cc:4604
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_DCACHE_INV_VOL
GPUStaticInst * decode_OP_SMEM__S_DCACHE_INV_VOL(MachInst)
Definition: decoder.cc:8523
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_CLASS_F64
Definition: instructions.hh:10395
gem5::Gcn3ISA::Inst_DS__DS_MIN_SRC2_U32
Definition: instructions.hh:34197
gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX4
Definition: instructions.hh:41783
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_RSUB_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_U32(MachInst)
Definition: decoder.cc:6338
gem5::Gcn3ISA::Inst_VOP3__V_CMP_CLASS_F32
Definition: instructions.hh:17127
gem5::Gcn3ISA::Inst_VOP2__V_CNDMASK_B32
Definition: instructions.hh:6141
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_LSHR_B64
GPUStaticInst * decode_OP_SOP2__S_LSHR_B64(MachInst)
Definition: decoder.cc:3734
gem5::Gcn3ISA::Inst_VOP3__V_MAD_U64_U32
Definition: instructions.hh:29285
gem5::Gcn3ISA::Inst_VOP1__V_NOP
Definition: instructions.hh:7933
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_MOVRELS_B64
GPUStaticInst * decode_OP_SOP1__S_MOVRELS_B64(MachInst)
Definition: decoder.cc:8817
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NLE_F32
Definition: instructions.hh:18827
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F64(MachInst)
Definition: decoder.cc:4544
gem5::Gcn3ISA::Inst_SOPP__S_ICACHE_INV
Definition: instructions.hh:4995
gem5::Gcn3ISA::Inst_VOPC__V_CMP_EQ_U32
Definition: instructions.hh:15189
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F32(MachInst)
Definition: decoder.cc:4178
gem5::Gcn3ISA::Inst_SMEM__S_ATC_PROBE_BUFFER
Definition: instructions.hh:6107
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I16_F16
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I16_F16(MachInst)
Definition: decoder.cc:9561
gem5::Gcn3ISA::Inst_SOP2__S_MIN_I32
Definition: instructions.hh:251
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SUB
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SUB(MachInst)
Definition: decoder.cc:7292
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE
Definition: instructions.hh:38963
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_RSQ_F32
GPUStaticInst * decode_OP_VOP1__V_RSQ_F32(MachInst)
Definition: decoder.cc:9393
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NGE_F16
Definition: instructions.hh:17637
gem5::Gcn3ISA::Inst_VOP1__V_CVT_F32_UBYTE3
Definition: instructions.hh:8569
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_L_O(MachInst)
Definition: decoder.cc:7850
gem5::Gcn3ISA::Inst_VOP3__V_MUL_F16
Definition: instructions.hh:24967
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F16(MachInst)
Definition: decoder.cc:4100
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_INC_X2
Definition: instructions.hh:37447
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_SRC2_I64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_I64(MachInst)
Definition: decoder.cc:7106
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I64(MachInst)
Definition: decoder.cc:5030
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C
Definition: instructions.hh:40331
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_READ_B64
GPUStaticInst * decode_OP_DS__DS_READ_B64(MachInst)
Definition: decoder.cc:6902
gem5::Gcn3ISA::Inst_SOP2__S_AND_B64
Definition: instructions.hh:489
gem5::Gcn3ISA::Inst_VOP3__V_DIV_SCALE_F64
Definition: instructions.hh:29029
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F64(MachInst)
Definition: decoder.cc:4484
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_CL_O(MachInst)
Definition: decoder.cc:7862
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U16(MachInst)
Definition: decoder.cc:4736
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F16(MachInst)
Definition: decoder.cc:9759
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_T_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U16(MachInst)
Definition: decoder.cc:4640
gem5::Gcn3ISA::Inst_VOP2__V_MAC_F32
Definition: instructions.hh:6891
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX_I16
GPUStaticInst * decode_OPU_VOP3__V_MAX_I16(MachInst)
Definition: decoder.cc:5390
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_READFIRSTLANE_B32
GPUStaticInst * decode_OP_VOP1__V_READFIRSTLANE_B32(MachInst)
Definition: decoder.cc:9189
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE3
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE3(MachInst)
Definition: decoder.cc:9297
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_SQRT_F16
GPUStaticInst * decode_OP_VOP1__V_SQRT_F16(MachInst)
Definition: decoder.cc:9531
gem5::Gcn3ISA::Inst_VOP3__V_CVT_F64_F32
Definition: instructions.hh:25987
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_RTN_U64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_U64(MachInst)
Definition: decoder.cc:6830
gem5::Gcn3ISA::Inst_VOP3__V_FLOOR_F16
Definition: instructions.hh:27551
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LT_U64
Definition: instructions.hh:23621
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUBB_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBB_U32(MachInst)
Definition: decoder.cc:5288
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I16(MachInst)
Definition: decoder.cc:10359
gem5::Gcn3ISA::Inst_VOP1__V_CVT_F64_F32
Definition: instructions.hh:8441
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_I64
GPUStaticInst * decode_OP_DS__DS_MAX_I64(MachInst)
Definition: decoder.cc:6698
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_PERM_B32
GPUStaticInst * decode_OPU_VOP3__V_PERM_B32(MachInst)
Definition: decoder.cc:6122
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_I32
GPUStaticInst * decode_OP_DS__DS_MAX_I32(MachInst)
Definition: decoder.cc:6362
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MUL_HI_U32_U24
GPUStaticInst * decode_OP_VOP2__V_MUL_HI_U32_U24(MachInst)
Definition: decoder.cc:3290
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_AND_B32
GPUStaticInst * decode_OP_SOP2__S_AND_B32(MachInst)
Definition: decoder.cc:3620
gem5::Gcn3ISA::Inst_VOP1__V_LOG_F32
Definition: instructions.hh:8985
gem5::Gcn3ISA::Inst_VOP3__V_ADD_F16
Definition: instructions.hh:24865
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GT_U64
Definition: instructions.hh:23723
gem5::Gcn3ISA::Inst_VOP3__V_CVT_F64_I32
Definition: instructions.hh:25603
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F32(MachInst)
Definition: decoder.cc:9945
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I32(MachInst)
Definition: decoder.cc:10431
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_XOR_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_XOR_SRC2_B32(MachInst)
Definition: decoder.cc:6992
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I16
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I16(MachInst)
Definition: decoder.cc:5366
gem5::Gcn3ISA::Inst_VOP3__V_CMP_U_F16
Definition: instructions.hh:17603
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_RTN_U32
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_U32(MachInst)
Definition: decoder.cc:6470
gem5::Gcn3ISA::Inst_DS__DS_OR_B32
Definition: instructions.hh:30983
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F64(MachInst)
Definition: decoder.cc:9633
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAC_F32
GPUStaticInst * decode_OPU_VOP3__V_MAC_F32(MachInst)
Definition: decoder.cc:5258
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP
Definition: instructions.hh:36619
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I16(MachInst)
Definition: decoder.cc:10245
gem5::Gcn3ISA::Inst_VOP1__V_CVT_F64_I32
Definition: instructions.hh:8057
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MUL_HI_I32_I24
GPUStaticInst * decode_OP_VOP2__V_MUL_HI_I32_I24(MachInst)
Definition: decoder.cc:3278
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MIN_F16
GPUStaticInst * decode_OP_VOP2__V_MIN_F16(MachInst)
Definition: decoder.cc:3512
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:7502
gem5::Gcn3ISA::Inst_SOP1__S_BREV_B64
Definition: instructions.hh:2471
gem5::Gcn3ISA::Inst_SOPK__S_CMPK_EQ_I32
Definition: instructions.hh:1607
gem5::Gcn3ISA::Inst_VOP1__V_RCP_F16
Definition: instructions.hh:9781
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_LZ(MachInst)
Definition: decoder.cc:7616
gem5::Gcn3ISA::Inst_VOP3__V_MED3_U32
Definition: instructions.hh:28703
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LT_U32
Definition: instructions.hh:15699
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F16(MachInst)
Definition: decoder.cc:4160
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I64(MachInst)
Definition: decoder.cc:10743
gem5::Gcn3ISA::Inst_DS__DS_OR_SRC2_B32
Definition: instructions.hh:34287
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_READ_B96
GPUStaticInst * decode_OP_DS__DS_READ_B96(MachInst)
Definition: decoder.cc:7178
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_I32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_I32_F64(MachInst)
Definition: decoder.cc:9195
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SAD_U32
GPUStaticInst * decode_OPU_VOP3__V_SAD_U32(MachInst)
Definition: decoder.cc:6020
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_INC_RTN_U32
GPUStaticInst * decode_OP_DS__DS_INC_RTN_U32(MachInst)
Definition: decoder.cc:6488
gem5::Gcn3ISA::Inst_VOP3__V_SIN_F32
Definition: instructions.hh:26787
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_ORN2_B32
GPUStaticInst * decode_OP_SOP2__S_ORN2_B32(MachInst)
Definition: decoder.cc:3668
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_T_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U16(MachInst)
Definition: decoder.cc:10323
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_INC
Definition: instructions.hh:36979
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F32(MachInst)
Definition: decoder.cc:4190
gem5::Gcn3ISA::Inst_SOP2__S_AND_B32
Definition: instructions.hh:455
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_BFE_I64
GPUStaticInst * decode_OP_SOP2__S_BFE_I64(MachInst)
Definition: decoder.cc:3788
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX_U16
GPUStaticInst * decode_OPU_VOP3__V_MAX_U16(MachInst)
Definition: decoder.cc:5384
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NE_U16
Definition: instructions.hh:21037
gem5::Gcn3ISA::Decoder::subDecode_OP_VOP1
GPUStaticInst * subDecode_OP_VOP1(MachInst)
Definition: decoder.cc:3140
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LT_U16
Definition: instructions.hh:20901
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MOV_B32
GPUStaticInst * decode_OPU_VOP3__V_MOV_B32(MachInst)
Definition: decoder.cc:5420
gem5::Gcn3ISA::Inst_VOP2__V_MUL_F16
Definition: instructions.hh:7317
gem5::Gcn3ISA::Inst_DS__DS_WRITE_B16
Definition: instructions.hh:31409
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_UMIN
Definition: instructions.hh:41995
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LT_I64
Definition: instructions.hh:23349
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F16(MachInst)
Definition: decoder.cc:3968
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GE_I64
Definition: instructions.hh:16685
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_U32(MachInst)
Definition: decoder.cc:6968
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GT_I64
Definition: instructions.hh:23451
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_AND_B32
GPUStaticInst * decode_OP_DS__DS_AND_B32(MachInst)
Definition: decoder.cc:6380
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F64(MachInst)
Definition: decoder.cc:10065
gem5::Gcn3ISA::Inst_VOP3__V_CMP_CLASS_F16
Definition: instructions.hh:17263
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LG_F64
Definition: instructions.hh:13387
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GE_U16
Definition: instructions.hh:14237
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I32(MachInst)
Definition: decoder.cc:4880
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GE_I32
Definition: instructions.hh:21887
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_CL
Definition: instructions.hh:40151
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I32(MachInst)
Definition: decoder.cc:10545
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX4
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:8199
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LT_F64
Definition: instructions.hh:20085
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NLE_F16
Definition: instructions.hh:17739
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F32(MachInst)
Definition: decoder.cc:4304
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE(MachInst)
Definition: decoder.cc:7574
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GE_F64
Definition: instructions.hh:13421
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_SUB_U32
GPUStaticInst * decode_OP_DS__DS_SUB_U32(MachInst)
Definition: decoder.cc:6332
gem5::Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
Definition: instructions.hh:37633
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_U64(MachInst)
Definition: decoder.cc:7118
gem5::Gcn3ISA::Inst_VOP2__V_ADD_F16
Definition: instructions.hh:7215
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F64(MachInst)
Definition: decoder.cc:10131
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F64(MachInst)
Definition: decoder.cc:10209
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_EXP_F16
GPUStaticInst * decode_OPU_VOP3__V_EXP_F16(MachInst)
Definition: decoder.cc:5780
gem5::Gcn3ISA::Inst_DS__DS_READ2_B64
Definition: instructions.hh:33885
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GT_F64
Definition: instructions.hh:20187
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F32(MachInst)
Definition: decoder.cc:9621
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GE_F32
Definition: instructions.hh:18623
gem5::Gcn3ISA::Inst_VOP3__V_DIV_FIXUP_F16
Definition: instructions.hh:29569
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_READ_B128
GPUStaticInst * decode_OP_DS__DS_READ_B128(MachInst)
Definition: decoder.cc:7184
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MSKOR_B32
GPUStaticInst * decode_OP_DS__DS_MSKOR_B32(MachInst)
Definition: decoder.cc:6398
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FMA_F32
GPUStaticInst * decode_OPU_VOP3__V_FMA_F32(MachInst)
Definition: decoder.cc:5918
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NGE_F32
Definition: instructions.hh:12435
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_L
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_L(MachInst)
Definition: decoder.cc:7646
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FFBL_B32
GPUStaticInst * decode_OPU_VOP3__V_FFBL_B32(MachInst)
Definition: decoder.cc:5684
gem5::Gcn3ISA::Inst_VOP1__V_SQRT_F16
Definition: instructions.hh:9813
gem5::Gcn3ISA::Inst_SOP1__S_SET_GPR_IDX_IDX
Definition: instructions.hh:3749
gem5::Gcn3ISA::Inst_VOP1__V_TRUNC_F64
Definition: instructions.hh:8665
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F64(MachInst)
Definition: decoder.cc:10101
gem5::Gcn3ISA::Inst_SOP2__S_XOR_B64
Definition: instructions.hh:625
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F32(MachInst)
Definition: decoder.cc:9969
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NLT_F64
Definition: instructions.hh:13149
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_RNDNE_F32
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F32(MachInst)
Definition: decoder.cc:9357
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NGT_F64
Definition: instructions.hh:19881
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_RSUB_RTN_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_RTN_U64(MachInst)
Definition: decoder.cc:6794
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F16(MachInst)
Definition: decoder.cc:9669
gem5::Gcn3ISA::Inst_VOP3__V_CVT_I16_F16
Definition: instructions.hh:27295
gem5::Gcn3ISA::Inst_SOPP__S_TRAP
Definition: instructions.hh:4965
gem5::Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY
Definition: instructions.hh:37557
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_CSELECT_B64
GPUStaticInst * decode_OP_SOP2__S_CSELECT_B64(MachInst)
Definition: decoder.cc:3614
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F64(MachInst)
Definition: decoder.cc:10047
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U16(MachInst)
Definition: decoder.cc:10407
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FLOOR_F16
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F16(MachInst)
Definition: decoder.cc:5798
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F16(MachInst)
Definition: decoder.cc:4010
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_BFREV_B32
GPUStaticInst * decode_OP_VOP1__V_BFREV_B32(MachInst)
Definition: decoder.cc:9441
gem5::Gcn3ISA::Inst_MIMG__IMAGE_LOAD_MIP
Definition: instructions.hh:38163
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_EQ_U64
Definition: instructions.hh:16821
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_ENDPGM_SAVED
GPUStaticInst * decode_OP_SOPP__S_ENDPGM_SAVED(MachInst)
Definition: decoder.cc:9141
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U32(MachInst)
Definition: decoder.cc:10605
gem5::Gcn3ISA::Inst_VOP1__V_CVT_I16_F16
Definition: instructions.hh:9749
gem5::Gcn3ISA::Inst_SOPP__S_INCPERFLEVEL
Definition: instructions.hh:5025
gem5::Gcn3ISA::Inst_VOP3__V_INTERP_P1LL_F16
Definition: instructions.hh:29741
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_ABSDIFF_I32
GPUStaticInst * decode_OP_SOP2__S_ABSDIFF_I32(MachInst)
Definition: decoder.cc:3800
gem5::Gcn3ISA::Inst_VOP3__V_CMP_U_F32
Definition: instructions.hh:18691
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_READ_I8
GPUStaticInst * decode_OP_DS__DS_READ_I8(MachInst)
Definition: decoder.cc:6620
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F64(MachInst)
Definition: decoder.cc:9639
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GE_U32
Definition: instructions.hh:15869
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_RCP_IFLAG_F32
GPUStaticInst * decode_OP_VOP1__V_RCP_IFLAG_F32(MachInst)
Definition: decoder.cc:9387
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_XOR
Definition: instructions.hh:36943
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GT_U16
Definition: instructions.hh:21003
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F64(MachInst)
Definition: decoder.cc:10137
gem5::Gcn3ISA::Inst_SOP2__S_NOR_B32
Definition: instructions.hh:863
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_EQ_U16
Definition: instructions.hh:21479
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I16(MachInst)
Definition: decoder.cc:4658
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NGT_F64
Definition: instructions.hh:13591
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_LE_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LE_I32(MachInst)
Definition: decoder.cc:3854
gem5::Gcn3ISA::Inst_DS__DS_GWS_SEMA_P
Definition: instructions.hh:34591
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X(MachInst)
Definition: decoder.cc:8109
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_DIV_SCALE_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_SCALE_F64(MachInst)
Definition: decoder.cc:6050
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_LZ_O(MachInst)
Definition: decoder.cc:7712
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I64(MachInst)
Definition: decoder.cc:10737
gem5::Gcn3ISA::Inst_VOPC__V_CMP_TRU_F32
Definition: instructions.hh:12095
gem5::Gcn3ISA::Inst_SOPP__S_CBRANCH_SCC0
Definition: instructions.hh:4541
gem5::Gcn3ISA::Inst_VINTRP__V_INTERP_P2_F32
Definition: instructions.hh:17059
gem5::Gcn3ISA::Inst_VOP3__V_SUBREV_U32
Definition: instructions.hh:24715
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LE_U64
Definition: instructions.hh:16311
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_FFBH_U32
GPUStaticInst * decode_OP_VOP1__V_FFBH_U32(MachInst)
Definition: decoder.cc:9447
gem5::Gcn3ISA::Inst_VOP3__V_RSQ_F16
Definition: instructions.hh:27391
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F16(MachInst)
Definition: decoder.cc:3986
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I16(MachInst)
Definition: decoder.cc:4682
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_OR_B64
GPUStaticInst * decode_OP_DS__DS_OR_B64(MachInst)
Definition: decoder.cc:6722
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_CLASS_F32
Definition: instructions.hh:17161
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F16(MachInst)
Definition: decoder.cc:4070
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_LSHL_B64
GPUStaticInst * decode_OP_SOP2__S_LSHL_B64(MachInst)
Definition: decoder.cc:3722
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX4
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:7232
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_SUB_U32
GPUStaticInst * decode_OP_SOP2__S_SUB_U32(MachInst)
Definition: decoder.cc:3554
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_AND_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_AND_SRC2_B32(MachInst)
Definition: decoder.cc:6980
gem5::Gcn3ISA::Inst_SOP2__S_MIN_U32
Definition: instructions.hh:285
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_T_U64
Definition: instructions.hh:16991
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I64(MachInst)
Definition: decoder.cc:4946
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_SUB
Definition: instructions.hh:36691
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_CNDMASK_B32
GPUStaticInst * decode_OP_VOP2__V_CNDMASK_B32(MachInst)
Definition: decoder.cc:3236
gem5::Gcn3ISA::Inst_VOP3__V_INTERP_P2_F32
Definition: instructions.hh:29673
gem5::Gcn3ISA::Inst_VINTRP__V_INTERP_MOV_F32
Definition: instructions.hh:17093
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_ADD_U32(MachInst)
Definition: decoder.cc:3548
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_U_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F64(MachInst)
Definition: decoder.cc:4406
gem5::Gcn3ISA::Inst_VOP3__V_BFI_B32
Definition: instructions.hh:28199
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MUL_U32_U24
GPUStaticInst * decode_OP_VOP2__V_MUL_U32_U24(MachInst)
Definition: decoder.cc:3284
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW
Definition: instructions.hh:35449
gem5::Gcn3ISA::Inst_SOPP__S_BARRIER
Definition: instructions.hh:4725
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I16(MachInst)
Definition: decoder.cc:4688
gem5::Gcn3ISA::Inst_VOPC__V_CMP_U_F16
Definition: instructions.hh:10769
gem5::Gcn3ISA::Inst_VOP1__V_SIN_F32
Definition: instructions.hh:9241
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_RSQ_F64
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F64(MachInst)
Definition: decoder.cc:5636
gem5::Gcn3ISA::Inst_VOP3__V_CVT_PKNORM_U16_F32
Definition: instructions.hh:30527
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_D
Definition: instructions.hh:39323
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O(MachInst)
Definition: decoder.cc:7724
gem5::Gcn3ISA::Inst_SOPK__S_CBRANCH_I_FORK
Definition: instructions.hh:2055
gem5::Gcn3ISA::Inst_VOP1__V_FREXP_MANT_F64
Definition: instructions.hh:9497
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_EQ_I16
Definition: instructions.hh:21207
gem5::Gcn3ISA::Inst_SOPK__S_CMPK_LE_U32
Definition: instructions.hh:1959
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_COS_F32
GPUStaticInst * decode_OP_VOP1__V_COS_F32(MachInst)
Definition: decoder.cc:9429
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:8451
gem5::Gcn3ISA::Inst_VOP3__V_LDEXP_F64
Definition: instructions.hh:29983
gem5::Gcn3ISA::Inst_VOP3__V_EXP_LEGACY_F32
Definition: instructions.hh:27775
gem5::Gcn3ISA::Inst_SOP1__S_WQM_B32
Definition: instructions.hh:2375
gem5::Gcn3ISA::Inst_VOP3__V_MUL_HI_U32_U24
Definition: instructions.hh:24167
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I64(MachInst)
Definition: decoder.cc:4970
gem5::Gcn3ISA::Inst_VOP2__V_SUBREV_U16
Definition: instructions.hh:7525
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_XNOR_B32
GPUStaticInst * decode_OP_SOP2__S_XNOR_B32(MachInst)
Definition: decoder.cc:3704
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_TRUNC_F32
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F32(MachInst)
Definition: decoder.cc:5576
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F16_I16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_I16(MachInst)
Definition: decoder.cc:5738
gem5::Gcn3ISA::Inst_DS__DS_GWS_SEMA_V
Definition: instructions.hh:34529
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_SUBREV_U32
GPUStaticInst * decode_OP_VOP2__V_SUBREV_U32(MachInst)
Definition: decoder.cc:3398
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_HI_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_I32_I24(MachInst)
Definition: decoder.cc:5168
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F16(MachInst)
Definition: decoder.cc:4112
gem5::Gcn3ISA::Inst_VOP3__V_DIV_FIXUP_F32
Definition: instructions.hh:28919
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_BFM_B32
GPUStaticInst * decode_OPU_VOP3__V_BFM_B32(MachInst)
Definition: decoder.cc:6290
gem5::Gcn3ISA::Inst_SOP1__S_FF1_I32_B64
Definition: instructions.hh:2727
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F32(MachInst)
Definition: decoder.cc:4352
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F16(MachInst)
Definition: decoder.cc:9783
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F32(MachInst)
Definition: decoder.cc:4250
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F16(MachInst)
Definition: decoder.cc:9807
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_SIN_F32
GPUStaticInst * decode_OP_VOP1__V_SIN_F32(MachInst)
Definition: decoder.cc:9423
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_I64
Definition: instructions.hh:23315
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GET_LOD
Definition: instructions.hh:40979
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_EQ_F16
Definition: instructions.hh:17943
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F32(MachInst)
Definition: decoder.cc:4322
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F32(MachInst)
Definition: decoder.cc:10005
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F32(MachInst)
Definition: decoder.cc:9885
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_BREV_B64
GPUStaticInst * decode_OP_SOP1__S_BREV_B64(MachInst)
Definition: decoder.cc:8613
gem5::Gcn3ISA::Inst_DS__DS_MAX_RTN_I64
Definition: instructions.hh:33375
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_T_I64
Definition: instructions.hh:16719
gem5::Gcn3ISA::Inst_VOP1__V_FLOOR_F16
Definition: instructions.hh:10005
gem5::Gcn3ISA::Inst_VOP3__V_ADD_F64
Definition: instructions.hh:29847
gem5::Gcn3ISA::Inst_VOP3__V_MBCNT_LO_U32_B32
Definition: instructions.hh:30255
gem5::Gcn3ISA::Inst_VOP2__V_LDEXP_F16
Definition: instructions.hh:7899
gem5::Gcn3ISA::InFmt_SOPC::OP
unsigned int OP
Definition: gpu_decoder.hh:1527
gem5::Gcn3ISA::Inst_DS__DS_SWIZZLE_B32
Definition: instructions.hh:32425
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_LZ
Definition: instructions.hh:40511
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FRACT_F16
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F16(MachInst)
Definition: decoder.cc:5822
gem5::Gcn3ISA::Inst_DS__DS_MAX_RTN_F64
Definition: instructions.hh:33817
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_F64
Definition: instructions.hh:20051
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_CMPST_F64
GPUStaticInst * decode_OP_DS__DS_CMPST_F64(MachInst)
Definition: decoder.cc:6764
gem5::Gcn3ISA::Inst_SMEM__S_DCACHE_WB_VOL
Definition: instructions.hh:5985
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I32(MachInst)
Definition: decoder.cc:10539
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NEQ_F16
Definition: instructions.hh:10939
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NE_I32
Definition: instructions.hh:15563
gem5::Gcn3ISA::Inst_VOP3__V_CMP_O_F64
Definition: instructions.hh:19745
gem5::Gcn3ISA::Inst_VOP3__V_CMP_F_F64
Definition: instructions.hh:19507
gem5::Gcn3ISA::Inst_DS__DS_SUB_U32
Definition: instructions.hh:30695
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_MIN_I32
GPUStaticInst * decode_OP_SOP2__S_MIN_I32(MachInst)
Definition: decoder.cc:3584
gem5::Gcn3ISA::Inst_VOP3__V_CVT_F32_UBYTE3
Definition: instructions.hh:26115
gem5::Gcn3ISA::Inst_SOPP__S_SETHALT
Definition: instructions.hh:4815
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_RNDNE_F32
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F32(MachInst)
Definition: decoder.cc:5588
gem5::Gcn3ISA::Inst_VOP3__V_CMP_F_I64
Definition: instructions.hh:22771
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F32(MachInst)
Definition: decoder.cc:4232
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F16(MachInst)
Definition: decoder.cc:4154
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_SUB_F32
GPUStaticInst * decode_OP_VOP2__V_SUB_F32(MachInst)
Definition: decoder.cc:3248
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_CD_O
Definition: instructions.hh:41159
gem5::Gcn3ISA::Inst_SMEM__S_BUFFER_STORE_DWORDX4
Definition: instructions.hh:5865
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_SENDMSGHALT
GPUStaticInst * decode_OP_SOPP__S_SENDMSGHALT(MachInst)
Definition: decoder.cc:9081
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I16(MachInst)
Definition: decoder.cc:4586
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F32
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F32(MachInst)
Definition: decoder.cc:5720
gem5::Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX4
Definition: instructions.hh:5397
gem5::Gcn3ISA::Inst_VOP3__V_CVT_F16_F32
Definition: instructions.hh:25795
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_D_CL
Definition: instructions.hh:39071
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NLG_F64
Definition: instructions.hh:13013
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_U_F16
Definition: instructions.hh:18147
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_LG_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_I32(MachInst)
Definition: decoder.cc:8865
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F64(MachInst)
Definition: decoder.cc:4418
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F16(MachInst)
Definition: decoder.cc:9729
gem5::Gcn3ISA::Inst_VOP3__V_DIV_FMAS_F64
Definition: instructions.hh:29105
gem5::Gcn3ISA::Inst_VOP1__V_CVT_F16_F32
Definition: instructions.hh:8249
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE_B64
GPUStaticInst * decode_OP_DS__DS_WRITE_B64(MachInst)
Definition: decoder.cc:6740
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O(MachInst)
Definition: decoder.cc:7946
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_ADD
Definition: instructions.hh:36655
gem5::Gcn3ISA::Inst_DS__DS_MSKOR_RTN_B32
Definition: instructions.hh:31851
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_O_F64
Definition: instructions.hh:13455
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_D
Definition: instructions.hh:39035
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_CD
Definition: instructions.hh:41015
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_SET_GPR_IDX_IDX
GPUStaticInst * decode_OP_SOP1__S_SET_GPR_IDX_IDX(MachInst)
Definition: decoder.cc:8853
gem5::Gcn3ISA::Inst_SOP2__S_ORN2_B64
Definition: instructions.hh:761
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_ADD
Definition: instructions.hh:41889
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRXCHG2ST64_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG2ST64_RTN_B64(MachInst)
Definition: decoder.cc:6872
gem5::Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX2
Definition: instructions.hh:5541
gem5::Gcn3ISA::Inst_VOP3__V_SUBREV_F16
Definition: instructions.hh:24933
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_SETKILL
GPUStaticInst * decode_OP_SOPP__S_SETKILL(MachInst)
Definition: decoder.cc:9045
gem5::Gcn3ISA::Inst_VOP1__V_RSQ_F16
Definition: instructions.hh:9845
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F32(MachInst)
Definition: decoder.cc:4274
gem5::Gcn3ISA::Inst_DS__DS_READ_I16
Definition: instructions.hh:32359
gem5::Gcn3ISA::InFmt_MTBUF::OP
unsigned int OP
Definition: gpu_decoder.hh:1449
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_TRU_F16
Definition: instructions.hh:18385
gem5::Gcn3ISA::Inst_VOP2__V_ADD_U16
Definition: instructions.hh:7457
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_SETREG_B32
GPUStaticInst * decode_OP_SOPK__S_SETREG_B32(MachInst)
Definition: decoder.cc:3920
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_U64
Definition: instructions.hh:23587
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
Definition: instructions.hh:35677
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_LSHLREV_B32
GPUStaticInst * decode_OP_VOP2__V_LSHLREV_B32(MachInst)
Definition: decoder.cc:3344
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_BITSET0_B64
GPUStaticInst * decode_OP_SOP1__S_BITSET0_B64(MachInst)
Definition: decoder.cc:8709
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX4
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX4(MachInst)
Definition: decoder.cc:8235
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:8349
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I64(MachInst)
Definition: decoder.cc:5060
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_SCC0
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_SCC0(MachInst)
Definition: decoder.cc:9003
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GE_U32
Definition: instructions.hh:22159
gem5::Gcn3ISA::Inst_VOP3__V_CMP_F_U64
Definition: instructions.hh:23043
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U32(MachInst)
Definition: decoder.cc:4910
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_T_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I16(MachInst)
Definition: decoder.cc:4592
gem5::Gcn3ISA::Inst_SOP2__S_BFM_B64
Definition: instructions.hh:1237
gem5::Gcn3ISA::Inst_DS__DS_ADD_RTN_U64
Definition: instructions.hh:33171
gem5::Gcn3ISA::InFmt_SOPP::OP
unsigned int OP
Definition: gpu_decoder.hh:1542
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LG_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F64(MachInst)
Definition: decoder.cc:10071
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_BFE_U32
GPUStaticInst * decode_OPU_VOP3__V_BFE_U32(MachInst)
Definition: decoder.cc:5900
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_READ_U16
GPUStaticInst * decode_OP_DS__DS_READ_U16(MachInst)
Definition: decoder.cc:6638
gem5::Gcn3ISA::Inst_VOP3__V_ASHRREV_I16
Definition: instructions.hh:25239
gem5::Gcn3ISA::Inst_SOP1__S_QUADMASK_B64
Definition: instructions.hh:3493
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F32(MachInst)
Definition: decoder.cc:9951
gem5::Gcn3ISA::Inst_DS__DS_RSUB_RTN_U64
Definition: instructions.hh:33239
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LE_U64
Definition: instructions.hh:16855
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_MOVK_I32
GPUStaticInst * decode_OP_SOPK__S_MOVK_I32(MachInst)
Definition: decoder.cc:3812
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I32(MachInst)
Definition: decoder.cc:10425
gem5::Gcn3ISA::Inst_DS__DS_READ2_B32
Definition: instructions.hh:32225
gem5::Gcn3ISA::InFmt_VOP1
Definition: gpu_decoder.hh:1556
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_ADD_U16
GPUStaticInst * decode_OP_VOP2__V_ADD_U16(MachInst)
Definition: decoder.cc:3464
gem5::Gcn3ISA::Inst_SOP1__S_OR_SAVEEXEC_B64
Definition: instructions.hh:3237
gem5::Gcn3ISA::Inst_VOP3__V_CVT_I32_F32
Definition: instructions.hh:25731
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_INC_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_INC_SRC2_U64(MachInst)
Definition: decoder.cc:7094
gem5::Gcn3ISA::Inst_DS__DS_WRITE_B128
Definition: instructions.hh:35233
gem5::Gcn3ISA::Inst_VOP1__V_CVT_I32_F32
Definition: instructions.hh:8185
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_INTERP_P1_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1_F32(MachInst)
Definition: decoder.cc:6146
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F64(MachInst)
Definition: decoder.cc:10041
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_I64_I32
GPUStaticInst * decode_OPU_VOP3__V_MAD_I64_I32(MachInst)
Definition: decoder.cc:6098
gem5::Gcn3ISA::Inst_VOP2__V_MUL_LO_U16
Definition: instructions.hh:7559
gem5::Gcn3ISA::Decoder::tableSubDecode_OP_DS
static IsaDecodeMethod tableSubDecode_OP_DS[256]
Definition: gpu_decoder.hh:65
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MED3_I32
GPUStaticInst * decode_OPU_VOP3__V_MED3_I32(MachInst)
Definition: decoder.cc:5990
gem5::Gcn3ISA::InFmt_DS::OP
unsigned int OP
Definition: gpu_decoder.hh:1362
gem5::Gcn3ISA::Inst_VOP3__V_MUL_HI_U32
Definition: instructions.hh:30051
gem5::Gcn3ISA::Inst_SOPP__S_CBRANCH_CDBGSYS
Definition: instructions.hh:5115
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_T_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U64(MachInst)
Definition: decoder.cc:5024
gem5::Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX4
Definition: instructions.hh:5577
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:8139
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_ALIGNBIT_B32
GPUStaticInst * decode_OPU_VOP3__V_ALIGNBIT_B32(MachInst)
Definition: decoder.cc:5936
gem5::Gcn3ISA::Inst_SOP1__S_MOVRELD_B64
Definition: instructions.hh:3621
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_XOR_B64
GPUStaticInst * decode_OP_DS__DS_XOR_B64(MachInst)
Definition: decoder.cc:6728
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_CMPST_RTN_F64
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_F64(MachInst)
Definition: decoder.cc:6884
gem5::Gcn3ISA::InstFormat::iFmt_SOP2
InFmt_SOP2 iFmt_SOP2
Definition: gpu_decoder.hh:1659
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_RSQ_F32
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F32(MachInst)
Definition: decoder.cc:5624
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_RTN_F64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_F64(MachInst)
Definition: decoder.cc:6896
gem5::Gcn3ISA::Inst_VOP3__V_RCP_F64
Definition: instructions.hh:26659
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LE_U16
Definition: instructions.hh:14135
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:7424
gem5::Gcn3ISA::Inst_VOP3__V_RSQ_F64
Definition: instructions.hh:26691
gem5::Gcn3ISA::Inst_VOP3__V_CUBEMA_F32
Definition: instructions.hh:28091
gem5::Gcn3ISA::Inst_VOP3__V_MAD_LEGACY_F32
Definition: instructions.hh:27839
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_LZ_O
Definition: instructions.hh:40727
gem5::Gcn3ISA::Inst_VOP3__V_ADD_U16
Definition: instructions.hh:25035
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX3
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:8193
gem5::Gcn3ISA::InFmt_VINTRP
Definition: gpu_decoder.hh:1546
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_ADD_I32
GPUStaticInst * decode_OP_SOP2__S_ADD_I32(MachInst)
Definition: decoder.cc:3560
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I32(MachInst)
Definition: decoder.cc:10437
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_U_F32
Definition: instructions.hh:12401
gem5::Gcn3ISA::Inst_SOPP__S_DECPERFLEVEL
Definition: instructions.hh:5055
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_LOG_F16
GPUStaticInst * decode_OP_VOP1__V_LOG_F16(MachInst)
Definition: decoder.cc:9543
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4(MachInst)
Definition: decoder.cc:7766
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_EXECNZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_EXECNZ(MachInst)
Definition: decoder.cc:9033
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_STORE_BYTE
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_BYTE(MachInst)
Definition: decoder.cc:7238
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_WBINVL1_VOL
GPUStaticInst * decode_OP_MUBUF__BUFFER_WBINVL1_VOL(MachInst)
Definition: decoder.cc:8253
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_WQM_B32
GPUStaticInst * decode_OP_SOP1__S_WQM_B32(MachInst)
Definition: decoder.cc:8595
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LG_F64
Definition: instructions.hh:12843
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_L_O
Definition: instructions.hh:39683
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_AND
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_AND(MachInst)
Definition: decoder.cc:7544
gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX2
Definition: instructions.hh:41715
gem5::Gcn3ISA::Inst_MIMG__IMAGE_STORE_PCK
Definition: instructions.hh:38415
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP(MachInst)
Definition: decoder.cc:7436
gem5::Gcn3ISA::Inst_SOP2__S_LSHR_B64
Definition: instructions.hh:1101
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SWAP
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:7496
gem5::Gcn3ISA::Inst_VOP3__V_CEIL_F32
Definition: instructions.hh:26403
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_XOR_X2
Definition: instructions.hh:42617
gem5::Gcn3ISA::Inst_SMEM__S_ATC_PROBE
Definition: instructions.hh:6073
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MAC_F32
GPUStaticInst * decode_OP_VOP2__V_MAC_F32(MachInst)
Definition: decoder.cc:3368
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_OR_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_OR_SRC2_B32(MachInst)
Definition: decoder.cc:6986
gem5::Gcn3ISA::InstFormat::iFmt_EXP
InFmt_EXP iFmt_EXP
Definition: gpu_decoder.hh:1645
gem5::Gcn3ISA::Inst_DS__DS_INC_SRC2_U32
Definition: instructions.hh:34077
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_LE_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LE_U32(MachInst)
Definition: decoder.cc:3890
gem5::Gcn3ISA::Inst_DS__DS_OR_SRC2_B64
Definition: instructions.hh:35049
gem5::Gcn3ISA::Inst_VOP3__V_INTERP_P1LV_F16
Definition: instructions.hh:29775
gem5::Gcn3ISA::Inst_SOPK__S_CMPK_EQ_U32
Definition: instructions.hh:1799
gem5::Gcn3ISA::InstFormat::iFmt_MTBUF
InFmt_MTBUF iFmt_MTBUF
Definition: gpu_decoder.hh:1652
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F64(MachInst)
Definition: decoder.cc:10167
gem5::Gcn3ISA::Inst_SOPC__S_CMP_LT_I32
Definition: instructions.hh:3909
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NE_U16
Definition: instructions.hh:14747
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_XOR_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_XOR_SRC2_B64(MachInst)
Definition: decoder.cc:7142
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE1
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE1(MachInst)
Definition: decoder.cc:9285
gem5::Gcn3ISA::Decoder::decode_OP_VINTRP__V_INTERP_P1_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_P1_F32(MachInst)
Definition: decoder.cc:9159
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_AND_RTN_B64
GPUStaticInst * decode_OP_DS__DS_AND_RTN_B64(MachInst)
Definition: decoder.cc:6836
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NEQ_F32
Definition: instructions.hh:19405
gem5::Gcn3ISA::Inst_DS__DS_INC_RTN_U64
Definition: instructions.hh:33273
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_SRC2_F64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_F64(MachInst)
Definition: decoder.cc:7160
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_LG_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LG_U32(MachInst)
Definition: decoder.cc:3866
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B32
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B32(MachInst)
Definition: decoder.cc:5234
gem5::Gcn3ISA::Inst_VOP3__V_CMP_T_I64
Definition: instructions.hh:23009
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUB_U16
GPUStaticInst * decode_OPU_VOP3__V_SUB_U16(MachInst)
Definition: decoder.cc:5336
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX8
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX8(MachInst)
Definition: decoder.cc:8433
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F16(MachInst)
Definition: decoder.cc:9645
gem5::Gcn3ISA::Inst_DS__DS_DEC_SRC2_U64
Definition: instructions.hh:34869
gem5::Gcn3ISA::Inst_DS__DS_MIN_SRC2_I32
Definition: instructions.hh:34137
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F64(MachInst)
Definition: decoder.cc:4490
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_FLR_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_FLR_I32_F32(MachInst)
Definition: decoder.cc:9255
gem5::Gcn3ISA::Inst_VOP3__V_CMP_TRU_F32
Definition: instructions.hh:18929
gem5::Gcn3ISA::Inst_DS__DS_OR_RTN_B64
Definition: instructions.hh:33511
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F16(MachInst)
Definition: decoder.cc:9777
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY
Definition: instructions.hh:35829
gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORD
Definition: instructions.hh:41681
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O
Definition: instructions.hh:40043
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_SCC1
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_SCC1(MachInst)
Definition: decoder.cc:9009
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_ADD_F64
GPUStaticInst * decode_OPU_VOP3__V_ADD_F64(MachInst)
Definition: decoder.cc:6182
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_SBYTE
Definition: instructions.hh:35989
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I16(MachInst)
Definition: decoder.cc:4652
gem5::Gcn3ISA::Inst_DS__DS_GWS_INIT
Definition: instructions.hh:34497
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U32(MachInst)
Definition: decoder.cc:4814
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_OR_B32
GPUStaticInst * decode_OPU_VOP3__V_OR_B32(MachInst)
Definition: decoder.cc:5246
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_BFE_I32
GPUStaticInst * decode_OP_SOP2__S_BFE_I32(MachInst)
Definition: decoder.cc:3776
gem5::Gcn3ISA::Inst_VOPC__V_CMP_EQ_I32
Definition: instructions.hh:14917
gem5::Gcn3ISA::Inst_DS__DS_ADD_RTN_U32
Definition: instructions.hh:31443
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GE_U64
Definition: instructions.hh:23791
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MAC_F16
GPUStaticInst * decode_OP_VOP2__V_MAC_F16(MachInst)
Definition: decoder.cc:3446
gem5::Gcn3ISA::Inst_DS__DS_MIN_SRC2_F32
Definition: instructions.hh:34377
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ(MachInst)
Definition: decoder.cc:8073
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U64(MachInst)
Definition: decoder.cc:5006
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MADAK_F16
GPUStaticInst * decode_OP_VOP2__V_MADAK_F16(MachInst)
Definition: decoder.cc:3458
gem5::Gcn3ISA::Inst_VOP3__V_CMP_F_F16
Definition: instructions.hh:17331
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_BFREV_B32
GPUStaticInst * decode_OPU_VOP3__V_BFREV_B32(MachInst)
Definition: decoder.cc:5672
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I32(MachInst)
Definition: decoder.cc:4778
gem5::Gcn3ISA::Inst_SOPC__S_CMP_GT_I32
Definition: instructions.hh:3845
gem5::Gcn3ISA::Inst_VOP3__V_FRACT_F64
Definition: instructions.hh:27075
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_PERMUTE_B32
GPUStaticInst * decode_OP_DS__DS_PERMUTE_B32(MachInst)
Definition: decoder.cc:6650
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U64(MachInst)
Definition: decoder.cc:10695
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_STORE_SHORT
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_SHORT(MachInst)
Definition: decoder.cc:7244
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX4
Definition: instructions.hh:36217
gem5::Gcn3ISA::Decoder::tableSubDecode_OP_VOPC
static IsaDecodeMethod tableSubDecode_OP_VOPC[256]
Definition: gpu_decoder.hh:76
gem5::Gcn3ISA::Inst_SOPK__S_CMPK_GT_I32
Definition: instructions.hh:1671
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORDX4(MachInst)
Definition: decoder.cc:8505
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:8769
gem5::Gcn3ISA::Inst_VOP3__V_CMP_F_I16
Definition: instructions.hh:20595
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_EXP_F32
GPUStaticInst * decode_OP_VOP1__V_EXP_F32(MachInst)
Definition: decoder.cc:9369
gem5::Gcn3ISA::Inst_VOPC__V_CMP_EQ_F32
Definition: instructions.hh:11653
gem5::Gcn3ISA::InFmt_MIMG
Definition: gpu_decoder.hh:1418
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NGE_F32
Definition: instructions.hh:19269
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F64(MachInst)
Definition: decoder.cc:10107
gem5::Gcn3ISA::Inst_VOP3__V_SQRT_F32
Definition: instructions.hh:26723
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_MOV_B32
GPUStaticInst * decode_OP_VOP1__V_MOV_B32(MachInst)
Definition: decoder.cc:9183
gem5::Gcn3ISA::Inst_VOPC__V_CMP_CLASS_F64
Definition: instructions.hh:10361
gem5::Gcn3ISA::Inst_VOP3__V_ALIGNBYTE_B32
Definition: instructions.hh:28379
gem5::Gcn3ISA::Inst_VOP3__V_CMP_T_U64
Definition: instructions.hh:23281
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_TRUNC_F64
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F64(MachInst)
Definition: decoder.cc:9315
gem5::Gcn3ISA::Inst_SOPK__S_CMPK_LT_I32
Definition: instructions.hh:1735
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U64(MachInst)
Definition: decoder.cc:10683
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NLT_F32
Definition: instructions.hh:12605
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F32(MachInst)
Definition: decoder.cc:4280
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_F_U16
Definition: instructions.hh:14577
gem5::Gcn3ISA::Inst_DS__DS_AND_RTN_B64
Definition: instructions.hh:33477
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I32(MachInst)
Definition: decoder.cc:4760
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U64(MachInst)
Definition: decoder.cc:10671
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_RSQ_F16
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F16(MachInst)
Definition: decoder.cc:5768
gem5::Gcn3ISA::Inst_VOP1__V_CVT_U32_F64
Definition: instructions.hh:8601
gem5::Gcn3ISA::Inst_SOP2__S_OR_B32
Definition: instructions.hh:523
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GT_U64
Definition: instructions.hh:16345
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_XOR
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_XOR(MachInst)
Definition: decoder.cc:7334
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U64(MachInst)
Definition: decoder.cc:4994
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F16_U16
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_U16(MachInst)
Definition: decoder.cc:9501
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I64(MachInst)
Definition: decoder.cc:4952
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_QUADMASK_B32
GPUStaticInst * decode_OP_SOP1__S_QUADMASK_B32(MachInst)
Definition: decoder.cc:8799
gem5::Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_X
Definition: instructions.hh:37671
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I32
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I32(MachInst)
Definition: decoder.cc:5228
gem5::Gcn3ISA::Decoder::tableSubDecode_OP_SOPP
static IsaDecodeMethod tableSubDecode_OP_SOPP[128]
Definition: gpu_decoder.hh:73
gem5::Gcn3ISA::Decoder::tableSubDecode_OP_SOPC
static IsaDecodeMethod tableSubDecode_OP_SOPC[128]
Definition: gpu_decoder.hh:72
gem5::Gcn3ISA::InFmt_MIMG::OP
unsigned int OP
Definition: gpu_decoder.hh:1428
gem5::Gcn3ISA::Inst_VOP3__V_CVT_U32_F64
Definition: instructions.hh:26147
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F32(MachInst)
Definition: decoder.cc:4334
gem5::Gcn3ISA::Inst_DS__DS_WRITE2ST64_B64
Definition: instructions.hh:33011
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F16(MachInst)
Definition: decoder.cc:9651
gem5::Gcn3ISA::Inst_VOP1__V_CVT_RPI_I32_F32
Definition: instructions.hh:8313
gem5::Gcn3ISA::Inst_SOPC__S_BITCMP0_B32
Definition: instructions.hh:4165
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I64(MachInst)
Definition: decoder.cc:10749
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GE_I64
Definition: instructions.hh:23519
gem5::Gcn3ISA::Inst_DS__DS_ADD_U64
Definition: instructions.hh:32525
gem5::Gcn3ISA::Inst_SOP2__S_ASHR_I64
Definition: instructions.hh:1169
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_RCP_F16
GPUStaticInst * decode_OPU_VOP3__V_RCP_F16(MachInst)
Definition: decoder.cc:5756
gem5::Gcn3ISA::Inst_VOP3__V_CEIL_F16
Definition: instructions.hh:27583
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_NOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_NOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:8787
gem5::Gcn3ISA::Inst_VOP1__V_RCP_F64
Definition: instructions.hh:9113
gem5::Gcn3ISA::Inst_VOP1__V_RSQ_F64
Definition: instructions.hh:9145
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_U32
GPUStaticInst * decode_OP_DS__DS_ADD_U32(MachInst)
Definition: decoder.cc:6326
gem5::Gcn3ISA::Inst_SOP2__S_BFE_I32
Definition: instructions.hh:1339
gem5::Gcn3ISA::Inst_MIMG__IMAGE_STORE_MIP
Definition: instructions.hh:38379
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LT_I32
Definition: instructions.hh:15427
gem5::Gcn3ISA::Inst_VOP3__V_FREXP_MANT_F64
Definition: instructions.hh:27043
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_F32
GPUStaticInst * decode_OPU_VOP3__V_MAD_F32(MachInst)
Definition: decoder.cc:5858
gem5::Gcn3ISA::Inst_VOP3__V_LOG_F16
Definition: instructions.hh:27423
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_WRITE_SRC2_B32(MachInst)
Definition: decoder.cc:6998
gem5::Gcn3ISA::Inst_VOP1__V_CVT_F32_UBYTE0
Definition: instructions.hh:8473
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NEQ_F16
Definition: instructions.hh:17773
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_CL_O(MachInst)
Definition: decoder.cc:7844
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX2
Definition: instructions.hh:36377
gem5::Gcn3ISA::Inst_VOP3__V_CMP_F_U16
Definition: instructions.hh:20867
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GE_F64
Definition: instructions.hh:20255
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F16(MachInst)
Definition: decoder.cc:4058
gem5::Gcn3ISA::Decoder::subDecode_OP_MUBUF
GPUStaticInst * subDecode_OP_MUBUF(MachInst)
Definition: decoder.cc:3212
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_B_CL
Definition: instructions.hh:39179
gem5::Gcn3ISA::Inst_DS__DS_READ_U16
Definition: instructions.hh:32391
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F64_I32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_I32(MachInst)
Definition: decoder.cc:9201
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_F_I16
Definition: instructions.hh:14305
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_STORE_MIP_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_MIP_PCK(MachInst)
Definition: decoder.cc:7484
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LT_F32
Definition: instructions.hh:12163
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F32(MachInst)
Definition: decoder.cc:9975
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMAX
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:7310
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD(MachInst)
Definition: decoder.cc:8241
gem5::Gcn3ISA::Inst_SOP1__S_BREV_B32
Definition: instructions.hh:2439
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F64(MachInst)
Definition: decoder.cc:4376
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_F_F16
Definition: instructions.hh:11041
gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX3
Definition: instructions.hh:41749
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX2
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:7220
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LG_F64
Definition: instructions.hh:19677
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_PK_U16_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_U16_U32(MachInst)
Definition: decoder.cc:6314
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_I32
GPUStaticInst * decode_OP_DS__DS_MIN_I32(MachInst)
Definition: decoder.cc:6356
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GE_I16
Definition: instructions.hh:13965
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2
Definition: instructions.hh:37051
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NLG_F64
Definition: instructions.hh:19847
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U32(MachInst)
Definition: decoder.cc:10503
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_INTERP_P1LV_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1LV_F16(MachInst)
Definition: decoder.cc:6170
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MUL_F32
GPUStaticInst * decode_OP_VOP2__V_MUL_F32(MachInst)
Definition: decoder.cc:3266
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW(MachInst)
Definition: decoder.cc:8103
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_STORE_MIP
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_MIP(MachInst)
Definition: decoder.cc:7472
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_B32(MachInst)
Definition: decoder.cc:8667
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_L_O
Definition: instructions.hh:40619
gem5::Gcn3ISA::Decoder::subDecode_OP_SMEM
GPUStaticInst * subDecode_OP_SMEM(MachInst)
Definition: decoder.cc:3172
gem5::Gcn3ISA::Inst_VOP2__V_LSHRREV_B32
Definition: instructions.hh:6687
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I32_F64
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I32_F64(MachInst)
Definition: decoder.cc:5696
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_O(MachInst)
Definition: decoder.cc:7874
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_LOG_LEGACY_F32
GPUStaticInst * decode_OP_VOP1__V_LOG_LEGACY_F32(MachInst)
Definition: decoder.cc:9615
gem5::Gcn3ISA::Inst_SOPC__S_CMP_LG_I32
Definition: instructions.hh:3813
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GE_F16
Definition: instructions.hh:10701
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F64(MachInst)
Definition: decoder.cc:4472
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NE_U32
Definition: instructions.hh:15291
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LT_U32
Definition: instructions.hh:15155
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F16(MachInst)
Definition: decoder.cc:9717
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_UMAX
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:7538
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_COS_F16
GPUStaticInst * decode_OP_VOP1__V_COS_F16(MachInst)
Definition: decoder.cc:9603
gem5::Gcn3ISA::InstFormat::imm_u32
uint32_t imm_u32
Definition: gpu_decoder.hh:1672
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F16(MachInst)
Definition: decoder.cc:4004
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_OR
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_OR(MachInst)
Definition: decoder.cc:7550
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_LZ
Definition: instructions.hh:40295
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_LDS_DWORD
Definition: instructions.hh:36491
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NLT_F16
Definition: instructions.hh:11517
gem5::Gcn3ISA::Inst_DS__DS_INC_U64
Definition: instructions.hh:32621
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_TTRACEDATA
GPUStaticInst * decode_OP_SOPP__S_TTRACEDATA(MachInst)
Definition: decoder.cc:9111
gem5::Gcn3ISA::Decoder::Decoder
Decoder()
Definition: decoder.cc:45
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LG_F16
Definition: instructions.hh:10667
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_RCP_F64
GPUStaticInst * decode_OPU_VOP3__V_RCP_F64(MachInst)
Definition: decoder.cc:5630
gem5::Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX16
Definition: instructions.hh:5469
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F32(MachInst)
Definition: decoder.cc:4202
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE2ST64_B32
GPUStaticInst * decode_OP_DS__DS_WRITE2ST64_B32(MachInst)
Definition: decoder.cc:6416
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F32(MachInst)
Definition: decoder.cc:4310
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_EQ_I64
Definition: instructions.hh:16549
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAC_F16
GPUStaticInst * decode_OPU_VOP3__V_MAC_F16(MachInst)
Definition: decoder.cc:5324
gem5::Gcn3ISA::Inst_SOPC__S_CMP_LT_U32
Definition: instructions.hh:4101
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F32(MachInst)
Definition: decoder.cc:4328
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_SUBBREV_U32
GPUStaticInst * decode_OP_VOP2__V_SUBBREV_U32(MachInst)
Definition: decoder.cc:3416
gem5::Gcn3ISA::Inst_VOPC__V_CMP_F_I16
Definition: instructions.hh:13761
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XY
Definition: instructions.hh:35373
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F32(MachInst)
Definition: decoder.cc:4256
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SWAP_X2
Definition: instructions.hh:42271
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_MIN_U32
GPUStaticInst * decode_OP_SOP2__S_MIN_U32(MachInst)
Definition: decoder.cc:3590
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_EQ_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_EQ_U32(MachInst)
Definition: decoder.cc:3860
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_LO_U32
GPUStaticInst * decode_OPU_VOP3__V_MUL_LO_U32(MachInst)
Definition: decoder.cc:6212
gem5::Gcn3ISA::Decoder::tableSubDecode_OP_VINTRP
static IsaDecodeMethod tableSubDecode_OP_VINTRP[4]
Definition: gpu_decoder.hh:74
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GE_I32
Definition: instructions.hh:15597
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MADMK_F32
GPUStaticInst * decode_OP_VOP2__V_MADMK_F32(MachInst)
Definition: decoder.cc:3374
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_LZ(MachInst)
Definition: decoder.cc:7796
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U64(MachInst)
Definition: decoder.cc:10761
gem5::Gcn3ISA::Inst_VOPC__V_CMP_EQ_U16
Definition: instructions.hh:14101
gem5::Gcn3ISA::Inst_DS__DS_AND_RTN_B32
Definition: instructions.hh:31749
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN3_F32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_F32(MachInst)
Definition: decoder.cc:5948
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F16(MachInst)
Definition: decoder.cc:3980
gem5::Gcn3ISA::Inst_VOPC__V_CMP_F_F16
Definition: instructions.hh:10497
gem5::Gcn3ISA::Inst_SOP1__S_BCNT0_I32_B32
Definition: instructions.hh:2503
gem5::Gcn3ISA::Inst_VOP3__V_CMP_EQ_I32
Definition: instructions.hh:21751
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX3
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:7226
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_DEC_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_DEC_SRC2_U32(MachInst)
Definition: decoder.cc:6950
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GT_U32
Definition: instructions.hh:15257
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_WBINVL1_VOL
Definition: instructions.hh:36553
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_B
Definition: instructions.hh:39431
gem5::Gcn3ISA::Inst_DS__DS_WRXCHG_RTN_B64
Definition: instructions.hh:33613
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_EQ_F64
Definition: instructions.hh:13285
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O(MachInst)
Definition: decoder.cc:7706
gem5::Gcn3ISA::Inst_DS__DS_WRAP_RTN_B32
Definition: instructions.hh:32123
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F16_U16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_U16(MachInst)
Definition: decoder.cc:5732
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP_PCK(MachInst)
Definition: decoder.cc:7454
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_ADDC_U32
GPUStaticInst * decode_OPU_VOP3__V_ADDC_U32(MachInst)
Definition: decoder.cc:5282
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_QSAD_PK_U16_U8
GPUStaticInst * decode_OPU_VOP3__V_QSAD_PK_U16_U8(MachInst)
Definition: decoder.cc:6074
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NE_U32
Definition: instructions.hh:22669
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LT_U32
Definition: instructions.hh:22533
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_L
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_L(MachInst)
Definition: decoder.cc:7814
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_CL_O
Definition: instructions.hh:40799
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O(MachInst)
Definition: decoder.cc:7736
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NLT_F32
Definition: instructions.hh:19439
gem5::Gcn3ISA::Inst_MIMG__IMAGE_STORE_MIP_PCK
Definition: instructions.hh:38451
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LE_I64
Definition: instructions.hh:16039
gem5::Gcn3ISA::Inst_VOP3__V_CMP_EQ_F32
Definition: instructions.hh:18487
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GE_F32
Definition: instructions.hh:12333
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F16(MachInst)
Definition: decoder.cc:9723
gem5::Gcn3ISA::Inst_VOP3__V_MED3_F32
Definition: instructions.hh:28631
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NLG_F32
Definition: instructions.hh:12469
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORD
Definition: instructions.hh:36103
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_T_U16
Definition: instructions.hh:14815
gem5::Gcn3ISA::Inst_DS__DS_CONDXCHG32_RTN_B64
Definition: instructions.hh:33953
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F64(MachInst)
Definition: decoder.cc:4508
gem5::Gcn3ISA::Inst_DS__DS_PERMUTE_B32
Definition: instructions.hh:32457
gem5::Gcn3ISA::Inst_VOP3__V_CUBESC_F32
Definition: instructions.hh:28019
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_CD
Definition: instructions.hh:41087
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_U64
GPUStaticInst * decode_OP_DS__DS_ADD_U64(MachInst)
Definition: decoder.cc:6662
gem5::Gcn3ISA::Inst_DS__DS_ADD_SRC2_U32
Definition: instructions.hh:33987
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_AND_B32
GPUStaticInst * decode_OPU_VOP3__V_AND_B32(MachInst)
Definition: decoder.cc:5240
gem5::Gcn3ISA::Inst_VOP3__V_FLOOR_F32
Definition: instructions.hh:26467
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F32(MachInst)
Definition: decoder.cc:9933
gem5::Gcn3ISA::Inst_DS__DS_AND_SRC2_B32
Definition: instructions.hh:34257
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F64(MachInst)
Definition: decoder.cc:6038
gem5::Gcn3ISA::Inst_SOPC__S_CMP_GT_U32
Definition: instructions.hh:4037
gem5::Gcn3ISA::Inst_VOP1__V_FRACT_F32
Definition: instructions.hh:8793
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NGT_F64
Definition: instructions.hh:13047
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_STORE_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORDX2(MachInst)
Definition: decoder.cc:8481
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_INC_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:7418
gem5::Gcn3ISA::Inst_VOP3__V_MED3_I32
Definition: instructions.hh:28667
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_DCACHE_INV
GPUStaticInst * decode_OP_SMEM__S_DCACHE_INV(MachInst)
Definition: decoder.cc:8511
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_O(MachInst)
Definition: decoder.cc:7838
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LE_F64
Definition: instructions.hh:12775
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_XOR
Definition: instructions.hh:42165
gem5::Gcn3ISA::Inst_VOP1__V_LOG_F16
Definition: instructions.hh:9877
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_L_O(MachInst)
Definition: decoder.cc:7742
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O(MachInst)
Definition: decoder.cc:7688
gem5::Gcn3ISA::Inst_VOP1__V_CVT_U16_F16
Definition: instructions.hh:9717
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_ADD
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_ADD(MachInst)
Definition: decoder.cc:8271
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_NOP
GPUStaticInst * decode_OPU_VOP3__V_NOP(MachInst)
Definition: decoder.cc:5414
gem5::Gcn3ISA::Inst_SOPP__S_ENDPGM_SAVED
Definition: instructions.hh:5235
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B(MachInst)
Definition: decoder.cc:7820
gem5::Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY(MachInst)
Definition: decoder.cc:7970
gem5::Gcn3ISA::Inst_VOP3__V_CVT_U16_F16
Definition: instructions.hh:27263
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B(MachInst)
Definition: decoder.cc:7652
gem5::Gcn3ISA::Inst_DS__DS_XOR_SRC2_B64
Definition: instructions.hh:35079
gem5::Gcn3ISA::Inst_DS__DS_OR_RTN_B32
Definition: instructions.hh:31783
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SIN_F16
GPUStaticInst * decode_OPU_VOP3__V_SIN_F16(MachInst)
Definition: decoder.cc:5828
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_SUB_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_SUB_SRC2_U64(MachInst)
Definition: decoder.cc:7082
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:8151
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LT_U16
Definition: instructions.hh:14611
gem5::Gcn3ISA::Inst_VOP2__V_LSHRREV_B16
Definition: instructions.hh:7627
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_FLOOR_F16
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F16(MachInst)
Definition: decoder.cc:9567
gem5::Gcn3ISA::Inst_VOP3__V_DIV_FIXUP_F64
Definition: instructions.hh:28955
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NE_I32
Definition: instructions.hh:22397
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LT_I32
Definition: instructions.hh:22261
gem5::Gcn3ISA::InstFormat::iFmt_MUBUF
InFmt_MUBUF iFmt_MUBUF
Definition: gpu_decoder.hh:1654
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_OR
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_OR(MachInst)
Definition: decoder.cc:7328
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_RPI_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_RPI_I32_F32(MachInst)
Definition: decoder.cc:5480
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U32(MachInst)
Definition: decoder.cc:4808
gem5::Gcn3ISA::Inst_VOP3__V_MUL_HI_I32
Definition: instructions.hh:30085
gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_AND
Definition: instructions.hh:38793
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F64(MachInst)
Definition: decoder.cc:4538
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_XOR_X2
Definition: instructions.hh:37411
gem5::Gcn3ISA::Inst_DS__DS_RSUB_U32
Definition: instructions.hh:30727
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I16(MachInst)
Definition: decoder.cc:10263
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_SUB_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_SUB_SRC2_U32(MachInst)
Definition: decoder.cc:6932
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_T_I16
Definition: instructions.hh:14543
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FFBH_U32
GPUStaticInst * decode_OPU_VOP3__V_FFBH_U32(MachInst)
Definition: decoder.cc:5678
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LG_F32
Definition: instructions.hh:12299
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F16(MachInst)
Definition: decoder.cc:3974
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F64(MachInst)
Definition: decoder.cc:4448
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F64(MachInst)
Definition: decoder.cc:10221
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MIN_U32
GPUStaticInst * decode_OP_VOP2__V_MIN_U32(MachInst)
Definition: decoder.cc:3320
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I16(MachInst)
Definition: decoder.cc:10353
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F32(MachInst)
Definition: decoder.cc:4268
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LT_F32
Definition: instructions.hh:18997
gem5::Gcn3ISA::Inst_SOP2__S_BFE_U32
Definition: instructions.hh:1305
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I64(MachInst)
Definition: decoder.cc:10617
gem5::Gcn3ISA::Decoder::decode
GPUStaticInst * decode(MachInst mach_inst)
Definition: decoder.cc:3124
gem5::Gcn3ISA::Inst_SOP1__S_XOR_SAVEEXEC_B64
Definition: instructions.hh:3269
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F16
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F16(MachInst)
Definition: decoder.cc:5786
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_INC_U64
GPUStaticInst * decode_OP_DS__DS_INC_U64(MachInst)
Definition: decoder.cc:6680
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW
Definition: instructions.hh:35601
gem5::Gcn3ISA::Inst_MIMG__IMAGE_LOAD_PCK_SGN
Definition: instructions.hh:38235
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GE_I16
Definition: instructions.hh:20799
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_CLASS_F32
Definition: instructions.hh:10327
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_B
Definition: instructions.hh:39143
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_SEXT_I32_I16
GPUStaticInst * decode_OP_SOP1__S_SEXT_I32_I16(MachInst)
Definition: decoder.cc:8697
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMAX
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:8295
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F64(MachInst)
Definition: decoder.cc:10191
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_CL_O
Definition: instructions.hh:40583
gem5::Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX8
Definition: instructions.hh:5613
gem5::Gcn3ISA::Inst_VOP3__V_QSAD_PK_U16_U8
Definition: instructions.hh:29177
gem5::Gcn3ISA::Inst_SOP1__S_CMOV_B64
Definition: instructions.hh:2279
gem5::Gcn3ISA::Inst_DS__DS_GWS_SEMA_RELEASE_ALL
Definition: instructions.hh:34467
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U32(MachInst)
Definition: decoder.cc:10587
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_MOVRELS_B32
GPUStaticInst * decode_OP_SOP1__S_MOVRELS_B32(MachInst)
Definition: decoder.cc:8811
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GE_F16
Definition: instructions.hh:17535
gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B32
Definition: instructions.hh:6755
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U16(MachInst)
Definition: decoder.cc:4598
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I32(MachInst)
Definition: decoder.cc:4844
gem5::Gcn3ISA::Inst_DS__DS_WRITE2ST64_B32
Definition: instructions.hh:31149
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_U32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_U32_F64(MachInst)
Definition: decoder.cc:9303
gem5::Gcn3ISA::Inst_SOP1__S_BITSET1_B64
Definition: instructions.hh:3047
gem5::Gcn3ISA::InFmt_FLAT
Definition: gpu_decoder.hh:1394
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_T_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I32(MachInst)
Definition: decoder.cc:10563
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORD(MachInst)
Definition: decoder.cc:8181
gem5::Gcn3ISA::Inst_SOPC__S_BITCMP0_B64
Definition: instructions.hh:4229
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NLT_F16
Definition: instructions.hh:18351
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_ATC_PROBE_BUFFER
GPUStaticInst * decode_OP_SMEM__S_ATC_PROBE_BUFFER(MachInst)
Definition: decoder.cc:8553
gem5::Gcn3ISA::Inst_DS__DS_MAX_RTN_U32
Definition: instructions.hh:31715
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_DEC_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_DEC_SRC2_U64(MachInst)
Definition: decoder.cc:7100
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NLE_F16
Definition: instructions.hh:11449
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NLG_F16
Definition: instructions.hh:11381
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_SEXT_I32_I8
GPUStaticInst * decode_OP_SOP1__S_SEXT_I32_I8(MachInst)
Definition: decoder.cc:8691
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_RSQ_F16
GPUStaticInst * decode_OP_VOP1__V_RSQ_F16(MachInst)
Definition: decoder.cc:9537
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_T_I64
Definition: instructions.hh:23553
gem5::Gcn3ISA::Inst_VOP3__V_MIN_F64
Definition: instructions.hh:29915
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LG_F16
Definition: instructions.hh:17501
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL(MachInst)
Definition: decoder.cc:7640
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_O_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F16(MachInst)
Definition: decoder.cc:9795
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XY
Definition: instructions.hh:35525
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MBCNT_HI_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_MBCNT_HI_U32_B32(MachInst)
Definition: decoder.cc:6260
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_O_F16
Definition: instructions.hh:11279
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F16(MachInst)
Definition: decoder.cc:9657
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U16(MachInst)
Definition: decoder.cc:4694
gem5::Gcn3ISA::Inst_SOPC__S_CMP_LG_U32
Definition: instructions.hh:4005
gem5::Gcn3ISA::Inst_VOP3__V_CVT_RPI_I32_F32
Definition: instructions.hh:25859
gem5::Gcn3ISA::Inst_VOP3__V_READLANE_B32
Definition: instructions.hh:30153
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U64(MachInst)
Definition: decoder.cc:10785
gem5::Gcn3ISA::InFmt_VOP3
Definition: gpu_decoder.hh:1573
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O(MachInst)
Definition: decoder.cc:7958
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F32(MachInst)
Definition: decoder.cc:4184
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F16(MachInst)
Definition: decoder.cc:4136
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F32(MachInst)
Definition: decoder.cc:10023
gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_SUB
Definition: instructions.hh:38623
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_I64
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_I64(MachInst)
Definition: decoder.cc:8685
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_TRU_F64
Definition: instructions.hh:13727
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_L
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_L(MachInst)
Definition: decoder.cc:7598
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_USHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_USHORT(MachInst)
Definition: decoder.cc:8169
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORD
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORD(MachInst)
Definition: decoder.cc:7214
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_RCP_F32
GPUStaticInst * decode_OPU_VOP3__V_RCP_F32(MachInst)
Definition: decoder.cc:5612
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMIN
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:7298
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_LZ(MachInst)
Definition: decoder.cc:7832
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_FF0_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FF0_I32_B32(MachInst)
Definition: decoder.cc:8643
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_GWS_SEMA_P
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_P(MachInst)
Definition: decoder.cc:7046
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_U64
GPUStaticInst * decode_OP_DS__DS_MIN_U64(MachInst)
Definition: decoder.cc:6704
gem5::Gcn3ISA::Inst_VOP3__V_CVT_F32_UBYTE0
Definition: instructions.hh:26019
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F16(MachInst)
Definition: decoder.cc:9843
gem5::Gcn3ISA::Inst_SOP1__S_MOV_FED_B32
Definition: instructions.hh:3717
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_GETREG_B32
GPUStaticInst * decode_OP_SOPK__S_GETREG_B32(MachInst)
Definition: decoder.cc:3914
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_L_O
Definition: instructions.hh:40835
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F16(MachInst)
Definition: decoder.cc:4106
gem5::Gcn3ISA::Inst_VOP3__V_SUBREV_U16
Definition: instructions.hh:25103
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_GT_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_GT_U32(MachInst)
Definition: decoder.cc:8907
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FMA_F16
GPUStaticInst * decode_OPU_VOP3__V_FMA_F16(MachInst)
Definition: decoder.cc:6128
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CLREXCP
GPUStaticInst * decode_OP_VOP1__V_CLREXCP(MachInst)
Definition: decoder.cc:9495
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LE_I64
Definition: instructions.hh:22873
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LE_I64
Definition: instructions.hh:16583
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMAX
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:8301
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX_U32
GPUStaticInst * decode_OPU_VOP3__V_MAX_U32(MachInst)
Definition: decoder.cc:5216
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I64(MachInst)
Definition: decoder.cc:10641
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_ASHR_I32
GPUStaticInst * decode_OP_SOP2__S_ASHR_I32(MachInst)
Definition: decoder.cc:3740
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NGE_F64
Definition: instructions.hh:12979
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O(MachInst)
Definition: decoder.cc:7898
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F16(MachInst)
Definition: decoder.cc:4028
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LE_F64
Definition: instructions.hh:19609
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_TRUNC_F64
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F64(MachInst)
Definition: decoder.cc:5546
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_MOV_B64
GPUStaticInst * decode_OP_SOP1__S_MOV_B64(MachInst)
Definition: decoder.cc:8565
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_SUB_U32
GPUStaticInst * decode_OP_VOP2__V_SUB_U32(MachInst)
Definition: decoder.cc:3392
gem5::Gcn3ISA::Inst_VOP3__V_LDEXP_F32
Definition: instructions.hh:30119
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F64(MachInst)
Definition: decoder.cc:4388
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_AND_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_AND_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:8751
gem5::Gcn3ISA::InFmt_SOP1
Definition: gpu_decoder.hh:1506
gem5::Gcn3ISA::Inst_VOPC__V_CMP_U_F32
Definition: instructions.hh:11857
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LE_F64
Definition: instructions.hh:13319
gem5::Gcn3ISA::Inst_DS__DS_CMPST_RTN_F64
Definition: instructions.hh:33749
gem5::Gcn3ISA::Inst_VOP3__V_CMP_O_F16
Definition: instructions.hh:17569
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_O_F64
Definition: instructions.hh:20289
gem5::Gcn3ISA::Inst_DS__DS_INC_U32
Definition: instructions.hh:30759
gem5::Gcn3ISA::Inst_VOPC__V_CMP_F_U16
Definition: instructions.hh:14033
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F16(MachInst)
Definition: decoder.cc:4124
gem5::Gcn3ISA::Inst_SOPK__S_CMPK_GT_U32
Definition: instructions.hh:1863
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_AND_B64
GPUStaticInst * decode_OP_DS__DS_AND_B64(MachInst)
Definition: decoder.cc:6716
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN_U32
GPUStaticInst * decode_OPU_VOP3__V_MIN_U32(MachInst)
Definition: decoder.cc:5210
gem5::Gcn3ISA::Inst_SOP1__S_QUADMASK_B32
Definition: instructions.hh:3461
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LE_I16
Definition: instructions.hh:13863
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL(MachInst)
Definition: decoder.cc:7022
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_SUB_I32
GPUStaticInst * decode_OP_SOP2__S_SUB_I32(MachInst)
Definition: decoder.cc:3566
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_T_U64
Definition: instructions.hh:23825
gem5::Gcn3ISA::Inst_SOPK__S_CMPK_LT_U32
Definition: instructions.hh:1927
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_DEC
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_DEC(MachInst)
Definition: decoder.cc:7346
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32(MachInst)
Definition: decoder.cc:6140
gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B16
Definition: instructions.hh:7593
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_SSHORT
Definition: instructions.hh:36065
gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_UMIN
Definition: instructions.hh:38691
gem5::Gcn3ISA::Inst_VOP3__V_CMP_EQ_U32
Definition: instructions.hh:22023
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U16(MachInst)
Definition: decoder.cc:4610
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F64
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F64(MachInst)
Definition: decoder.cc:9471
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_X
Definition: instructions.hh:35335
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_CONDXCHG32_RTN_B64
GPUStaticInst * decode_OP_DS__DS_CONDXCHG32_RTN_B64(MachInst)
Definition: decoder.cc:6920
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_RTN_U32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_U32(MachInst)
Definition: decoder.cc:6518
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_BPERMUTE_B32
GPUStaticInst * decode_OP_DS__DS_BPERMUTE_B32(MachInst)
Definition: decoder.cc:6656
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F32(MachInst)
Definition: decoder.cc:9873
gem5::Gcn3ISA::Inst_DS__DS_AND_B32
Definition: instructions.hh:30951
gem5::Gcn3ISA::Inst_SOP2__S_CSELECT_B64
Definition: instructions.hh:421
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LE_F16
Definition: instructions.hh:10599
gem5::Gcn3ISA::Inst_VOP1__V_FLOOR_F32
Definition: instructions.hh:8921
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F16(MachInst)
Definition: decoder.cc:9741
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I64(MachInst)
Definition: decoder.cc:10731
gem5::Gcn3ISA::InFmt_SOP1::OP
unsigned int OP
Definition: gpu_decoder.hh:1509
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_SIN_F16
GPUStaticInst * decode_OP_VOP1__V_SIN_F16(MachInst)
Definition: decoder.cc:9597
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U16(MachInst)
Definition: decoder.cc:10377
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U16(MachInst)
Definition: decoder.cc:10383
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B64
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B64(MachInst)
Definition: decoder.cc:6266
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F16(MachInst)
Definition: decoder.cc:3998
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F32_I32
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_I32(MachInst)
Definition: decoder.cc:9207
gem5::Gcn3ISA::Inst_DS__DS_GWS_SEMA_BR
Definition: instructions.hh:34559
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_EXP_LEGACY_F32
GPUStaticInst * decode_OP_VOP1__V_EXP_LEGACY_F32(MachInst)
Definition: decoder.cc:9609
gem5::Gcn3ISA::Inst_SOPP__S_SETPRIO
Definition: instructions.hh:4875
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_I32_F32(MachInst)
Definition: decoder.cc:5456
gem5::Gcn3ISA::Inst_VOP1__V_CVT_U32_F32
Definition: instructions.hh:8153
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_L_O(MachInst)
Definition: decoder.cc:7886
gem5::Gcn3ISA::Inst_VOP1__V_RNDNE_F16
Definition: instructions.hh:10101
gem5::Gcn3ISA::Inst_SOP1__S_SEXT_I32_I16
Definition: instructions.hh:2919
gem5::Gcn3ISA::Inst_SOPP__S_CBRANCH_VCCNZ
Definition: instructions.hh:4633
gem5::Gcn3ISA::Inst_DS__DS_CMPST_RTN_B64
Definition: instructions.hh:33715
gem5::Gcn3ISA::Inst_VOP3__V_ADD_F32
Definition: instructions.hh:23895
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_F64(MachInst)
Definition: decoder.cc:9267
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NE_I16
Definition: instructions.hh:14475
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C
Definition: instructions.hh:39251
gem5::Gcn3ISA::Inst_DS__DS_CMPST_RTN_F32
Definition: instructions.hh:32021
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U16(MachInst)
Definition: decoder.cc:10305
gem5::Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
Definition: instructions.hh:37899
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F64(MachInst)
Definition: decoder.cc:10203
gem5::Gcn3ISA::Inst_VOP3__V_CVT_U32_F32
Definition: instructions.hh:25699
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:7358
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_RSUB_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_SRC2_U64(MachInst)
Definition: decoder.cc:7088
gem5::Gcn3ISA::Inst_VOP1__V_CEIL_F32
Definition: instructions.hh:8857
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_CBRANCH_JOIN
GPUStaticInst * decode_OP_SOP1__S_CBRANCH_JOIN(MachInst)
Definition: decoder.cc:8835
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MADAK_F32
GPUStaticInst * decode_OP_VOP2__V_MADAK_F32(MachInst)
Definition: decoder.cc:3380
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I64(MachInst)
Definition: decoder.cc:5072
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SAD_U8
GPUStaticInst * decode_OPU_VOP3__V_SAD_U8(MachInst)
Definition: decoder.cc:6002
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_STORE
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE(MachInst)
Definition: decoder.cc:7466
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U64(MachInst)
Definition: decoder.cc:10689
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F16
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F16(MachInst)
Definition: decoder.cc:6134
gem5::Gcn3ISA::Inst_DS__DS_WRXCHG2_RTN_B32
Definition: instructions.hh:31919
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_BITCMP1_B32
GPUStaticInst * decode_OP_SOPC__S_BITCMP1_B32(MachInst)
Definition: decoder.cc:8937
gem5::Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X(MachInst)
Definition: decoder.cc:8012
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_BCNT0_I32_B32
GPUStaticInst * decode_OP_SOP1__S_BCNT0_I32_B32(MachInst)
Definition: decoder.cc:8619
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I16(MachInst)
Definition: decoder.cc:4556
gem5::Gcn3ISA::Inst_SOP1__S_BITSET1_B32
Definition: instructions.hh:3015
gem5::Gcn3ISA::Inst_VOP3__V_CUBEID_F32
Definition: instructions.hh:27983
gem5::Gcn3ISA::Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER
Definition: instructions.hh:5175
gem5::Gcn3ISA::Inst_SOPC__S_SET_GPR_IDX_ON
Definition: instructions.hh:4325
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U16(MachInst)
Definition: decoder.cc:10401
gem5::Gcn3ISA::Inst_DS__DS_ORDERED_COUNT
Definition: instructions.hh:34717
gem5::Gcn3ISA::Inst_DS__DS_SUB_SRC2_U32
Definition: instructions.hh:34017
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NEQ_F16
Definition: instructions.hh:11483
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_O
Definition: instructions.hh:40763
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_CL(MachInst)
Definition: decoder.cc:7592
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_U_F32
Definition: instructions.hh:19235
gem5::Gcn3ISA::Decoder::tableSubDecode_OP_SOP1
static IsaDecodeMethod tableSubDecode_OP_SOP1[256]
Definition: gpu_decoder.hh:71
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GE_U64
Definition: instructions.hh:16413
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMIN
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:7304
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_INC
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_INC(MachInst)
Definition: decoder.cc:7562
gem5::Gcn3ISA::Inst_DS__DS_WRITE_B32
Definition: instructions.hh:31079
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I64(MachInst)
Definition: decoder.cc:4958
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_ADD_F16
GPUStaticInst * decode_OP_VOP2__V_ADD_F16(MachInst)
Definition: decoder.cc:3422
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_READLANE_B32
GPUStaticInst * decode_OPU_VOP3__V_READLANE_B32(MachInst)
Definition: decoder.cc:6236
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_QUADMASK_B64
GPUStaticInst * decode_OP_SOP1__S_QUADMASK_B64(MachInst)
Definition: decoder.cc:8805
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_UMAX_X2
Definition: instructions.hh:42515
gem5::Gcn3ISA::Inst_SMEM__S_STORE_DWORDX4
Definition: instructions.hh:5757
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_U32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_U32_F32(MachInst)
Definition: decoder.cc:9219
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN3_U32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_U32(MachInst)
Definition: decoder.cc:5960
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_U_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F32(MachInst)
Definition: decoder.cc:9897
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_DEC_RTN_U32
GPUStaticInst * decode_OP_DS__DS_DEC_RTN_U32(MachInst)
Definition: decoder.cc:6494
gem5::Gcn3ISA::Inst_EXP__EXP
Definition: instructions.hh:41303
gem5::Gcn3ISA::Inst_DS__DS_ADD_RTN_F32
Definition: instructions.hh:32157
gem5::Gcn3ISA::Inst_DS__DS_CMPST_RTN_B32
Definition: instructions.hh:31987
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SMAX
Definition: instructions.hh:42029
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_L
Definition: instructions.hh:39395
gem5::Gcn3ISA::Inst_VOP3__V_CMP_O_F32
Definition: instructions.hh:18657
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U32(MachInst)
Definition: decoder.cc:4826
gem5::Gcn3ISA::Inst_VOP2__V_MADMK_F16
Definition: instructions.hh:7385
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_LZ_O
Definition: instructions.hh:40079
gem5::Gcn3ISA::Inst_VOP3__V_CNDMASK_B32
Definition: instructions.hh:23859
gem5::Gcn3ISA::Inst_VOP3__V_CVT_PK_U8_F32
Definition: instructions.hh:28883
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_SETHALT
GPUStaticInst * decode_OP_SOPP__S_SETHALT(MachInst)
Definition: decoder.cc:9057
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_D_O
Definition: instructions.hh:39611
gem5::Gcn3ISA::Inst_VOP3__V_TRUNC_F16
Definition: instructions.hh:27615
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GE_U16
Definition: instructions.hh:21071
gem5::Gcn3ISA::InFmt_MUBUF
Definition: gpu_decoder.hh:1466
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F16(MachInst)
Definition: decoder.cc:9813
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GT_U16
Definition: instructions.hh:14713
gem5::Gcn3ISA::Inst_VOP2__V_ADD_F32
Definition: instructions.hh:6177
gem5::Gcn3ISA::Inst_VOP3__V_MAX_F32
Definition: instructions.hh:24235
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LE_U32
Definition: instructions.hh:15767
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:8355
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F64(MachInst)
Definition: decoder.cc:4430
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NLE_F64
Definition: instructions.hh:13625
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F64
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F64(MachInst)
Definition: decoder.cc:5702
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GT_I64
Definition: instructions.hh:16073
gem5::Gcn3ISA::Inst_VOP3__V_MQSAD_U32_U8
Definition: instructions.hh:29249
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_LDEXP_F16
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F16(MachInst)
Definition: decoder.cc:5408
gem5::Gcn3ISA::Inst_VOP3__V_MAX_I32
Definition: instructions.hh:24303
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_ADD_F16
GPUStaticInst * decode_OPU_VOP3__V_ADD_F16(MachInst)
Definition: decoder.cc:5300
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_CL_O
Definition: instructions.hh:39863
gem5::Gcn3ISA::Inst_VOP1__V_SQRT_F32
Definition: instructions.hh:9177
gem5::Gcn3ISA::Inst_SOP2__S_BFM_B32
Definition: instructions.hh:1203
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_FFBH_I32
GPUStaticInst * decode_OP_VOP1__V_FFBH_I32(MachInst)
Definition: decoder.cc:9459
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I32(MachInst)
Definition: decoder.cc:4748
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2
Definition: instructions.hh:42305
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CUBEID_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBEID_F32(MachInst)
Definition: decoder.cc:5876
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F16_I16
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_I16(MachInst)
Definition: decoder.cc:9507
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_CMOV_B32
GPUStaticInst * decode_OP_SOP1__S_CMOV_B32(MachInst)
Definition: decoder.cc:8571
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:8379
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:8337
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GT_F64
Definition: instructions.hh:12809
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN_F64
GPUStaticInst * decode_OPU_VOP3__V_MIN_F64(MachInst)
Definition: decoder.cc:6194
gem5::Gcn3ISA::Inst_VOP3__V_SAD_U32
Definition: instructions.hh:28847
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_EQ_U64
Definition: instructions.hh:23655
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F32(MachInst)
Definition: decoder.cc:9627
gem5::Gcn3ISA::InstFormat::iFmt_VOPC
InFmt_VOPC iFmt_VOPC
Definition: gpu_decoder.hh:1669
gem5::Gcn3ISA::Inst_VOPC__V_CMP_O_F16
Definition: instructions.hh:10735
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U16(MachInst)
Definition: decoder.cc:10317
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NLT_F32
Definition: instructions.hh:18895
gem5::Gcn3ISA::InstFormat::iFmt_DS
InFmt_DS iFmt_DS
Definition: gpu_decoder.hh:1643
gem5::Gcn3ISA::Inst_VOP3__V_MAX3_I32
Definition: instructions.hh:28559
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_RTN_F32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_F32(MachInst)
Definition: decoder.cc:6584
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F16(MachInst)
Definition: decoder.cc:4130
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GE_U32
Definition: instructions.hh:22703
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MIN_F32
GPUStaticInst * decode_OP_VOP2__V_MIN_F32(MachInst)
Definition: decoder.cc:3296
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LG_F64
Definition: instructions.hh:20221
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F16(MachInst)
Definition: decoder.cc:4088
gem5::Gcn3ISA::Inst_VOP3__V_CVT_I32_F64
Definition: instructions.hh:25571
gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_SWAP
Definition: instructions.hh:38521
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_LDEXP_F64
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F64(MachInst)
Definition: decoder.cc:6206
gem5::Gcn3ISA::Inst_VOP1__V_CEIL_F16
Definition: instructions.hh:10037
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_CMPST_F32
GPUStaticInst * decode_OP_DS__DS_CMPST_F32(MachInst)
Definition: decoder.cc:6428
gem5::Gcn3ISA::Inst_VOP3__V_CMP_T_I16
Definition: instructions.hh:20833
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32(MachInst)
Definition: decoder.cc:6308
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MED3_U32
GPUStaticInst * decode_OPU_VOP3__V_MED3_U32(MachInst)
Definition: decoder.cc:5996
gem5::Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ(MachInst)
Definition: decoder.cc:7976
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE0
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE0(MachInst)
Definition: decoder.cc:9279
gem5::Gcn3ISA::Inst_VOP1__V_CVT_I32_F64
Definition: instructions.hh:8025
gem5::Gcn3ISA::Inst_VOP3__V_SUB_F16
Definition: instructions.hh:24899
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U64(MachInst)
Definition: decoder.cc:5012
gem5::Gcn3ISA::Inst_SOP2__S_LSHR_B32
Definition: instructions.hh:1067
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LE_I16
Definition: instructions.hh:20697
gem5::Gcn3ISA::Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN
Definition: instructions.hh:38307
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NGT_F16
Definition: instructions.hh:18249
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_SUB_X2
Definition: instructions.hh:37159
gem5::Gcn3ISA::Inst_VOP3__V_MAX3_F32
Definition: instructions.hh:28523
gem5::Gcn3ISA::Inst_DS__DS_WRITE_B8
Definition: instructions.hh:31375
gem5::Gcn3ISA::InFmt_MTBUF
Definition: gpu_decoder.hh:1443
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGUSER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGUSER(MachInst)
Definition: decoder.cc:9123
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_TRIG_PREOP_F64
GPUStaticInst * decode_OPU_VOP3__V_TRIG_PREOP_F64(MachInst)
Definition: decoder.cc:6284
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_INC_U32
GPUStaticInst * decode_OP_DS__DS_INC_U32(MachInst)
Definition: decoder.cc:6344
gem5::Gcn3ISA::Decoder::~Decoder
~Decoder()
Definition: decoder.cc:49
gem5::Gcn3ISA::Inst_VOP2__V_MAX_F32
Definition: instructions.hh:6517
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LE_F16
Definition: instructions.hh:17433
instructions.hh
gem5::Gcn3ISA::Inst_VOP3__V_INTERP_MOV_F32
Definition: instructions.hh:29707
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U32(MachInst)
Definition: decoder.cc:10479
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F16(MachInst)
Definition: decoder.cc:4052
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NLE_F64
Definition: instructions.hh:13081
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_B_CL
Definition: instructions.hh:40475
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Gcn3ISA::Inst_DS__DS_MSKOR_B64
Definition: instructions.hh:32909
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LE_U64
Definition: instructions.hh:23145
gem5::Gcn3ISA::Inst_SOP1__S_MOVRELS_B32
Definition: instructions.hh:3525
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B64
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B64(MachInst)
Definition: decoder.cc:6272
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U16(MachInst)
Definition: decoder.cc:4730
gem5::Gcn3ISA::Inst_VOP2__V_MAX_I32
Definition: instructions.hh:6585
gem5::Gcn3ISA::Inst_DS__DS_RSUB_SRC2_U64
Definition: instructions.hh:34809
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_EQ_I64
Definition: instructions.hh:23383
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_L
Definition: instructions.hh:39107
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_ADD
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_ADD(MachInst)
Definition: decoder.cc:7286
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MAX_U32
GPUStaticInst * decode_OP_VOP2__V_MAX_U32(MachInst)
Definition: decoder.cc:3326
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NE_I32
Definition: instructions.hh:15019
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LT_I32
Definition: instructions.hh:14883
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_U32(MachInst)
Definition: decoder.cc:6974
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GE_I32
Definition: instructions.hh:22431
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORD
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORD(MachInst)
Definition: decoder.cc:8445
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F64(MachInst)
Definition: decoder.cc:10143
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F64(MachInst)
Definition: decoder.cc:4394
gem5::Gcn3ISA::Inst_VOP3__V_CMP_T_U16
Definition: instructions.hh:21105
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CUBESC_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBESC_F32(MachInst)
Definition: decoder.cc:5882
gem5::Gcn3ISA::Inst_VOP3__V_MOV_FED_B32
Definition: instructions.hh:25763
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_BITCMP0_B32
GPUStaticInst * decode_OP_SOPC__S_BITCMP0_B32(MachInst)
Definition: decoder.cc:8931
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_CL(MachInst)
Definition: decoder.cc:7808
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_EQ_F64
Definition: instructions.hh:20119
gem5::Gcn3ISA::InstFormat::iFmt_SMEM
InFmt_SMEM iFmt_SMEM
Definition: gpu_decoder.hh:1656
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_I16
Definition: instructions.hh:21139
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CL_O(MachInst)
Definition: decoder.cc:7676
gem5::Gcn3ISA::Inst_VOP3__V_MUL_LO_U16
Definition: instructions.hh:25137
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F16(MachInst)
Definition: decoder.cc:3962
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U16(MachInst)
Definition: decoder.cc:4718
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_O(MachInst)
Definition: decoder.cc:7748
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_DEC_RTN_U64
GPUStaticInst * decode_OP_DS__DS_DEC_RTN_U64(MachInst)
Definition: decoder.cc:6806
gem5::Gcn3ISA::Inst_VOP1__V_MOV_FED_B32
Definition: instructions.hh:8217
gem5::Gcn3ISA::Inst_VOPC__V_CMP_LT_F32
Definition: instructions.hh:11619
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GE_F32
Definition: instructions.hh:19167
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL(MachInst)
Definition: decoder.cc:7658
gem5::Gcn3ISA::Inst_VOP2__V_SUB_F16
Definition: instructions.hh:7249
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY(MachInst)
Definition: decoder.cc:8091
gem5::Gcn3ISA::Inst_DS__DS_MIN_RTN_U64
Definition: instructions.hh:33409
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_RNDNE_F64
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F64(MachInst)
Definition: decoder.cc:9327
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I32(MachInst)
Definition: decoder.cc:10455
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4
Definition: instructions.hh:40115
gem5::Gcn3ISA::Decoder::subDecode_OPU_VOP3
GPUStaticInst * subDecode_OPU_VOP3(MachInst)
Definition: decoder.cc:3180
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_NOT_B64
GPUStaticInst * decode_OP_SOP1__S_NOT_B64(MachInst)
Definition: decoder.cc:8589
gem5::Gcn3ISA::Inst_DS__DS_MAX_SRC2_U32
Definition: instructions.hh:34227
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_F16
Definition: instructions.hh:17875
gem5::Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:8054
gem5::Gcn3ISA::Inst_DS__DS_DEC_U64
Definition: instructions.hh:32653
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_FLOOR_F32
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F32(MachInst)
Definition: decoder.cc:9363
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_FLR_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_FLR_I32_F32(MachInst)
Definition: decoder.cc:5486
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NGE_F64
Definition: instructions.hh:19813
gem5::Gcn3ISA::Inst_VOPC__V_CMP_EQ_I16
Definition: instructions.hh:13829
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F32(MachInst)
Definition: decoder.cc:9855
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:8121
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_T_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I64(MachInst)
Definition: decoder.cc:10755
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:8385
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_T_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I64(MachInst)
Definition: decoder.cc:10659
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_ANDN2_B64
GPUStaticInst * decode_OP_SOP2__S_ANDN2_B64(MachInst)
Definition: decoder.cc:3662
gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_UMAX
Definition: instructions.hh:38759
gem5::Gcn3ISA::Inst_SOPP__S_BRANCH
Definition: instructions.hh:4481
gem5::Gcn3ISA::Inst_VOP3__V_MUL_HI_I32_I24
Definition: instructions.hh:24099
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GT_I32
Definition: instructions.hh:14985
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MUL_LEGACY_F32
GPUStaticInst * decode_OP_VOP2__V_MUL_LEGACY_F32(MachInst)
Definition: decoder.cc:3260
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U32(MachInst)
Definition: decoder.cc:4922
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_UBYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_UBYTE(MachInst)
Definition: decoder.cc:8157
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F64(MachInst)
Definition: decoder.cc:4478
gem5::Gcn3ISA::Inst_VOPC__V_CMP_NGE_F32
Definition: instructions.hh:11891
gem5::Gcn3ISA::Inst_DS__DS_READ_B128
Definition: instructions.hh:35301
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F32(MachInst)
Definition: decoder.cc:4262
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MIN_I32
GPUStaticInst * decode_OP_VOP2__V_MIN_I32(MachInst)
Definition: decoder.cc:3308
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16(MachInst)
Definition: decoder.cc:8469
gem5::Gcn3ISA::Inst_VOP3__V_COS_F32
Definition: instructions.hh:26819
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_NOT_B32
GPUStaticInst * decode_OP_VOP1__V_NOT_B32(MachInst)
Definition: decoder.cc:9435
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NLT_F16
Definition: instructions.hh:17807
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_T_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U16(MachInst)
Definition: decoder.cc:10419
gem5::Gcn3ISA::Inst_VOPC__V_CMP_EQ_F16
Definition: instructions.hh:10565
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I64(MachInst)
Definition: decoder.cc:10725
gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_BYTE
Definition: instructions.hh:41613
gem5::Gcn3ISA::Inst_SOP2__S_MUL_I32
Definition: instructions.hh:1271
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX3
Definition: instructions.hh:36415
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_O_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F16(MachInst)
Definition: decoder.cc:4016
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_AND_RTN_B32
GPUStaticInst * decode_OP_DS__DS_AND_RTN_B32(MachInst)
Definition: decoder.cc:6524
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUBBREV_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBBREV_U32(MachInst)
Definition: decoder.cc:5294
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MADMK_F16
GPUStaticInst * decode_OP_VOP2__V_MADMK_F16(MachInst)
Definition: decoder.cc:3452
gem5::Gcn3ISA::Inst_VOP3__V_CMP_T_I32
Definition: instructions.hh:21921
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_USHORT
Definition: instructions.hh:36027
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_AND
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_AND(MachInst)
Definition: decoder.cc:7322
gem5::Gcn3ISA::Inst_VOPC__V_CMP_GT_F32
Definition: instructions.hh:11721
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_INTERP_MOV_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_MOV_F32(MachInst)
Definition: decoder.cc:6158
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_O
Definition: instructions.hh:40547
gem5::Gcn3ISA::Inst_SOP2__S_ASHR_I32
Definition: instructions.hh:1135
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL(MachInst)
Definition: decoder.cc:7934
gem5::Gcn3ISA::Inst_SOPK__S_MOVK_I32
Definition: instructions.hh:1543
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_OR_B32
GPUStaticInst * decode_OP_DS__DS_OR_B32(MachInst)
Definition: decoder.cc:6386
gem5::Gcn3ISA::Inst_SOP2__S_ANDN2_B32
Definition: instructions.hh:659
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_EQ_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_I32(MachInst)
Definition: decoder.cc:8859
gem5::Gcn3ISA::Inst_DS__DS_CMPST_B64
Definition: instructions.hh:33043
gem5::Gcn3ISA::Inst_VOP3__V_SQRT_F64
Definition: instructions.hh:26755
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GT_I64
Definition: instructions.hh:22907
gem5::Gcn3ISA::Inst_DS__DS_ADD_SRC2_F32
Definition: instructions.hh:34437
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX3
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX3(MachInst)
Definition: decoder.cc:7262
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_SWIZZLE_B32
GPUStaticInst * decode_OP_DS__DS_SWIZZLE_B32(MachInst)
Definition: decoder.cc:6644
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_STORE_DWORD
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORD(MachInst)
Definition: decoder.cc:8475
gem5::Gcn3ISA::Inst_SOP1__S_MOV_B64
Definition: instructions.hh:2215
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F32(MachInst)
Definition: decoder.cc:4298
gem5::Gcn3ISA::Inst_VOPC__V_CMP_T_I16
Definition: instructions.hh:13999
gem5::Gcn3ISA::Inst_SOP2__S_ORN2_B32
Definition: instructions.hh:727
gem5::Gcn3ISA::Inst_MIMG__IMAGE_LOAD
Definition: instructions.hh:38127
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_RSQ_F64
GPUStaticInst * decode_OP_VOP1__V_RSQ_F64(MachInst)
Definition: decoder.cc:9405
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_TRU_F64
Definition: instructions.hh:20561
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GT_F64
Definition: instructions.hh:19643
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_DIV_FMAS_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_FMAS_F64(MachInst)
Definition: decoder.cc:6062
gem5::Gcn3ISA::Inst_VOP3__V_RNDNE_F16
Definition: instructions.hh:27647
gem5::Gcn3ISA::InFmt_SMEM
Definition: gpu_decoder.hh:1490
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_U16
Definition: instructions.hh:21411
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LT_I16
Definition: instructions.hh:14339
gem5::Gcn3ISA::Inst_VOP3__V_FMA_F64
Definition: instructions.hh:28271
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:8391
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_O
Definition: instructions.hh:39827
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_LSHR_B32
GPUStaticInst * decode_OP_SOP2__S_LSHR_B32(MachInst)
Definition: decoder.cc:3728
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CEIL_F64
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F64(MachInst)
Definition: decoder.cc:5552
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_PKNORM_I16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKNORM_I16_F32(MachInst)
Definition: decoder.cc:6296
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F64(MachInst)
Definition: decoder.cc:4454
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_B64(MachInst)
Definition: decoder.cc:8673
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F16(MachInst)
Definition: decoder.cc:4064
gem5::Gcn3ISA::Inst_SMEM__S_DCACHE_WB
Definition: instructions.hh:5929
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F16(MachInst)
Definition: decoder.cc:4142
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_I32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_I32_F64(MachInst)
Definition: decoder.cc:5426
gem5::Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_LZ_O
Definition: instructions.hh:40943
gem5::Gcn3ISA::Inst_VOP2__V_ADD_U32
Definition: instructions.hh:6993
gem5::Gcn3ISA::Inst_VOP3__V_CMP_T_U32
Definition: instructions.hh:22193
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CNDMASK_B32
GPUStaticInst * decode_OPU_VOP3__V_CNDMASK_B32(MachInst)
Definition: decoder.cc:5126
gem5::Gcn3ISA::Inst_VOP2__V_MUL_HI_U32_U24
Definition: instructions.hh:6449
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I64(MachInst)
Definition: decoder.cc:5042
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NLT_F64
Definition: instructions.hh:13693
gem5::Gcn3ISA::InFmt_DS
Definition: gpu_decoder.hh:1357
gem5::Gcn3ISA::Inst_SOP1__S_FF0_I32_B32
Definition: instructions.hh:2631
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LT_F16
Definition: instructions.hh:11075
gem5::Gcn3ISA::InstFormat::iFmt_VOP1
InFmt_VOP1 iFmt_VOP1
Definition: gpu_decoder.hh:1664
gem5::Gcn3ISA::Inst_DS__DS_CMPST_F64
Definition: instructions.hh:33075
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_RTN_F32
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_F32(MachInst)
Definition: decoder.cc:6596
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_COS_F16
GPUStaticInst * decode_OPU_VOP3__V_COS_F16(MachInst)
Definition: decoder.cc:5834
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_RTN_U64
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_U64(MachInst)
Definition: decoder.cc:6782
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_DIV_SCALE_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_SCALE_F32(MachInst)
Definition: decoder.cc:6044
gem5::Gcn3ISA::InstFormat
Definition: gpu_decoder.hh:1641
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_T_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I16(MachInst)
Definition: decoder.cc:10275
gem5::Gcn3ISA::Inst_SMEM__S_LOAD_DWORD
Definition: instructions.hh:5325
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LE_U64
Definition: instructions.hh:23689
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I32(MachInst)
Definition: decoder.cc:4862
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_RSUB_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_SRC2_U32(MachInst)
Definition: decoder.cc:6938
gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_DEC_X2
Definition: instructions.hh:42687
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_SLEEP
GPUStaticInst * decode_OP_SOPP__S_SLEEP(MachInst)
Definition: decoder.cc:9063
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_F32(MachInst)
Definition: decoder.cc:5468
gem5::Gcn3ISA::Inst_SOPK__S_CMPK_GE_I32
Definition: instructions.hh:1703
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F64(MachInst)
Definition: decoder.cc:10197
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_VCCZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_VCCZ(MachInst)
Definition: decoder.cc:9015
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F64(MachInst)
Definition: decoder.cc:4382
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F64(MachInst)
Definition: decoder.cc:3956
gem5::Gcn3ISA::Inst_SOP2__S_XNOR_B64
Definition: instructions.hh:965
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:7364
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_ASHRREV_I16
GPUStaticInst * decode_OP_VOP2__V_ASHRREV_I16(MachInst)
Definition: decoder.cc:3500
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O(MachInst)
Definition: decoder.cc:7760
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_ADD_U16
GPUStaticInst * decode_OPU_VOP3__V_ADD_U16(MachInst)
Definition: decoder.cc:5330
gem5::Gcn3ISA::Inst_VOP3__V_BFREV_B32
Definition: instructions.hh:26883
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:7280
gem5::Gcn3ISA::Inst_SMEM__S_MEMREALTIME
Definition: instructions.hh:6043
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I32(MachInst)
Definition: decoder.cc:4838
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_L_O
Definition: instructions.hh:39971
gem5::Gcn3ISA::Inst_VOP3__V_MAD_F16
Definition: instructions.hh:29361
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CEIL_F16
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F16(MachInst)
Definition: decoder.cc:5804
gem5::Gcn3ISA::Inst_SOPC__S_CMP_EQ_U64
Definition: instructions.hh:4357
gem5::Gcn3ISA::Inst_VOP1__V_TRUNC_F16
Definition: instructions.hh:10069
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_HI_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_U32_U24(MachInst)
Definition: decoder.cc:5180
gem5::Gcn3ISA::Inst_VOP3__V_CMP_NE_I32
Definition: instructions.hh:21853
gem5::Gcn3ISA::Decoder::decode_OP_SOPP__S_DECPERFLEVEL
GPUStaticInst * decode_OP_SOPP__S_DECPERFLEVEL(MachInst)
Definition: decoder.cc:9105
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LT_I32
Definition: instructions.hh:21717
gem5::Gcn3ISA::Decoder::decode_OP_SMEM__S_MEMTIME
GPUStaticInst * decode_OP_SMEM__S_MEMTIME(MachInst)
Definition: decoder.cc:8535
gem5::Gcn3ISA::Inst_DS__DS_MAX_RTN_I32
Definition: instructions.hh:31647
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ
Definition: instructions.hh:35563
gem5::Gcn3ISA::Inst_SOP1__S_ABS_I32
Definition: instructions.hh:3685
gem5::Gcn3ISA::Inst_VOP3__V_MAX3_U32
Definition: instructions.hh:28595
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_T_I16
Definition: instructions.hh:21377
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_O_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F64(MachInst)
Definition: decoder.cc:10083
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_CL(MachInst)
Definition: decoder.cc:7922
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O
Definition: instructions.hh:39935
gem5::Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
Definition: instructions.hh:38013
gem5::Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY(MachInst)
Definition: decoder.cc:7994
gem5::Gcn3ISA::Inst_VOP3__V_MAD_I16
Definition: instructions.hh:29433
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_OR_B32
GPUStaticInst * decode_OP_VOP2__V_OR_B32(MachInst)
Definition: decoder.cc:3356
gem5::Gcn3ISA::Inst_VOP2__V_MAX_U32
Definition: instructions.hh:6653
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_AND_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_AND_SRC2_B64(MachInst)
Definition: decoder.cc:7130
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LT_F32
Definition: instructions.hh:18453
gem5::Gcn3ISA::Decoder::decode_OP_SOP1__S_NOT_B32
GPUStaticInst * decode_OP_SOP1__S_NOT_B32(MachInst)
Definition: decoder.cc:8583
gem5::Gcn3ISA::Inst_DS__DS_MAX_RTN_F32
Definition: instructions.hh:32089
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:7388
gem5::Gcn3ISA::Inst_VOP3__V_CUBETC_F32
Definition: instructions.hh:28055
gem5::Gcn3ISA::Inst_VOP3__V_ADD_U32
Definition: instructions.hh:24643
gem5::Gcn3ISA::Inst_VOP3__V_MAX_F64
Definition: instructions.hh:29949
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_O(MachInst)
Definition: decoder.cc:7892
gem5::Gcn3ISA::Inst_VOP3__V_CMP_LE_U16
Definition: instructions.hh:20969
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_XNOR_B64
GPUStaticInst * decode_OP_SOP2__S_XNOR_B64(MachInst)
Definition: decoder.cc:3710
gem5::Gcn3ISA::Inst_VOP1__V_COS_F32
Definition: instructions.hh:9273
gem5::Gcn3ISA::Inst_VOP3__V_MIN3_I32
Definition: instructions.hh:28451
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE2_B64
GPUStaticInst * decode_OP_DS__DS_WRITE2_B64(MachInst)
Definition: decoder.cc:6746
gem5::Gcn3ISA::Inst_DS__DS_INC_SRC2_U64
Definition: instructions.hh:34839
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GET_LOD
GPUStaticInst * decode_OP_MIMG__IMAGE_GET_LOD(MachInst)
Definition: decoder.cc:7910
gem5::Gcn3ISA::Inst_VOP3__V_MUL_LEGACY_F32
Definition: instructions.hh:23997
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LE_I64
Definition: instructions.hh:23417
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U32(MachInst)
Definition: decoder.cc:4886
gem5::Gcn3ISA::InstFormat::iFmt_SOPK
InFmt_SOPK iFmt_SOPK
Definition: gpu_decoder.hh:1661
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_READ_I16
GPUStaticInst * decode_OP_DS__DS_READ_I16(MachInst)
Definition: decoder.cc:6632
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I16(MachInst)
Definition: decoder.cc:4562
gem5::Gcn3ISA::Decoder::decode_OP_SOP2__S_LSHL_B32
GPUStaticInst * decode_OP_SOP2__S_LSHL_B32(MachInst)
Definition: decoder.cc:3716
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MUL_F16
GPUStaticInst * decode_OP_VOP2__V_MUL_F16(MachInst)
Definition: decoder.cc:3440
gem5::Gcn3ISA::Inst_DS__DS_AND_B64
Definition: instructions.hh:32813
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_BFE_I32
GPUStaticInst * decode_OPU_VOP3__V_BFE_I32(MachInst)
Definition: decoder.cc:5906
gem5::Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_LG_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LG_I32(MachInst)
Definition: decoder.cc:3830
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F32(MachInst)
Definition: decoder.cc:10035
gem5::Gcn3ISA::Decoder::decode_OP_VOP1__V_TRUNC_F16
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F16(MachInst)
Definition: decoder.cc:9579
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I32(MachInst)
Definition: decoder.cc:4856
gem5::Gcn3ISA::Inst_DS__DS_CMPST_B32
Definition: instructions.hh:31185
gem5::Gcn3ISA::Inst_VOP3__V_CMP_EQ_I16
Definition: instructions.hh:20663
gem5::Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_O
Definition: instructions.hh:39539
gem5::Gcn3ISA::Inst_MIMG__IMAGE_STORE
Definition: instructions.hh:38343
gem5::Gcn3ISA::Inst_VOP3__V_MUL_I32_I24
Definition: instructions.hh:24065
gem5::Gcn3ISA::Inst_VOP3__V_MIN3_F32
Definition: instructions.hh:28415
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_SET_GPR_IDX_ON
GPUStaticInst * decode_OP_SOPC__S_SET_GPR_IDX_ON(MachInst)
Definition: decoder.cc:8961
gem5::Gcn3ISA::Inst_DS__DS_ADD_SRC2_U64
Definition: instructions.hh:34749
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_SRC2_I32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_I32(MachInst)
Definition: decoder.cc:6962
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_RSUB_RTN_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_RTN_U32(MachInst)
Definition: decoder.cc:6482
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GT_I32
Definition: instructions.hh:21819
gem5::Gcn3ISA::Inst_SOP1__S_MOV_B32
Definition: instructions.hh:2183
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LE_F64
Definition: instructions.hh:20153
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U16(MachInst)
Definition: decoder.cc:4622
gem5::Gcn3ISA::Decoder::subDecode_OP_VINTRP
GPUStaticInst * subDecode_OP_VINTRP(MachInst)
Definition: decoder.cc:3188
gem5::Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2
Definition: instructions.hh:37195
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NE_U16
Definition: instructions.hh:21581
gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LT_U16
Definition: instructions.hh:21445
gem5::Gcn3ISA::Inst_VOP3__V_CMP_EQ_F16
Definition: instructions.hh:17399
gem5::Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SBYTE
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SBYTE(MachInst)
Definition: decoder.cc:7196
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U64(MachInst)
Definition: decoder.cc:5102
gem5::Gcn3ISA::Decoder::decode_OP_VOP2__V_MAX_U16
GPUStaticInst * decode_OP_VOP2__V_MAX_U16(MachInst)
Definition: decoder.cc:3518
gem5::Gcn3ISA::Inst_VOP2__V_MUL_I32_I24
Definition: instructions.hh:6347
gem5::Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW(MachInst)
Definition: decoder.cc:7982
gem5::Gcn3ISA::Inst_VOP3__V_SAD_HI_U8
Definition: instructions.hh:28775
gem5::Gcn3ISA::Inst_VOP3__V_CMP_GT_F32
Definition: instructions.hh:18555
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_READ2ST64_B64
GPUStaticInst * decode_OP_DS__DS_READ2ST64_B64(MachInst)
Definition: decoder.cc:6914
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_T_U32
Definition: instructions.hh:15903
gem5::Gcn3ISA::Inst_DS__DS_OR_B64
Definition: instructions.hh:32845
gem5::Gcn3ISA::Inst_DS__DS_MAX_I64
Definition: instructions.hh:32717
gem5::Gcn3ISA::Inst_VOP2__V_SUB_U16
Definition: instructions.hh:7491
gem5::Gcn3ISA::Inst_VOPC__V_CMPX_TRU_F32
Definition: instructions.hh:12639
gem5::Gcn3ISA::Inst_VOP3__V_RCP_F32
Definition: instructions.hh:26563
gem5::Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SUB
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SUB(MachInst)
Definition: decoder.cc:7514
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I32(MachInst)
Definition: decoder.cc:10551
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U64(MachInst)
Definition: decoder.cc:5000
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U32(MachInst)
Definition: decoder.cc:10473
gem5::Gcn3ISA::Inst_VOP1__V_FRACT_F16
Definition: instructions.hh:10133
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:8343
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F16(MachInst)
Definition: decoder.cc:4034
gem5::Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_GT_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_GT_I32(MachInst)
Definition: decoder.cc:8871
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_READ2_B64
GPUStaticInst * decode_OP_DS__DS_READ2_B64(MachInst)
Definition: decoder.cc:6908
gem5::Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_U32(MachInst)
Definition: decoder.cc:6926
gem5::Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORD(MachInst)
Definition: decoder.cc:8217
gem5::Gcn3ISA::Decoder::decode_OPU_VOP3__V_FFBH_I32
GPUStaticInst * decode_OPU_VOP3__V_FFBH_I32(MachInst)
Definition: decoder.cc:5690
gem5::Gcn3ISA::Inst_VOP2__V_MUL_U32_U24
Definition: instructions.hh:6415
gem5::Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F16(MachInst)
Definition: decoder.cc:9753

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