gem5::Uart8250::Registers Class Reference

#include <uart8250.hh>

Inheritance diagram for gem5::Uart8250::Registers:

Classes
class	BankedRegister
class	PairedRegister
class	RWSwitchedRegister

Public Member Functions
	Registers (Uart8250 *uart, const std::string &new_name)
Public Member Functions inherited from gem5::RegisterBank< ByteOrder::little >
constexpr	RegisterBank (const std::string &new_name, Addr new_base)
virtual	~RegisterBank ()
void	addRegisters (std::initializer_list< std::reference_wrapper< RegisterBase >> regs)
void	addRegister (RegisterBase &reg)
Addr	base () const
Addr	size () const
const std::string &	name () const
virtual void	read (Addr addr, void *buf, Addr bytes)
virtual void	write (Addr addr, const void *buf, Addr bytes)

Public Attributes
Register8	rbr = {"rbr"}
Register8	thr = {"thr"}
RWSwitchedRegister	rbrThr
Register8	dll = {"dll"}
BankedRegister	rbrThrDll
Register< Ier >	ier = {"ier", 0}
Register8	dlh = {"dlh"}
BankedRegister	ierDlh
Register< Iir >	iir = {"iir"}
Register8	fcr = {"fcr"}
RWSwitchedRegister	iirFcr
Register< Lcr >	lcr = {"lcr"}
Register8	mcr = {"mcr"}
Register< Lsr >	lsr = {"lsr"}
Register8	msr = {"msr"}
RegisterRaz	sr = {"sr", 1}

Additional Inherited Members
Public Types inherited from gem5::RegisterBank< ByteOrder::little >
using	Register8 = Register< uint8_t >
using	Register8LE = Register< uint8_t, ByteOrder::little >
using	Register8BE = Register< uint8_t, ByteOrder::big >
using	Register16 = Register< uint16_t >
using	Register16LE = Register< uint16_t, ByteOrder::little >
using	Register16BE = Register< uint16_t, ByteOrder::big >
using	Register32 = Register< uint32_t >
using	Register32LE = Register< uint32_t, ByteOrder::little >
using	Register32BE = Register< uint32_t, ByteOrder::big >
using	Register64 = Register< uint64_t >
using	Register64LE = Register< uint64_t, ByteOrder::little >
using	Register64BE = Register< uint64_t, ByteOrder::big >
Static Public Member Functions inherited from gem5::RegisterBank< ByteOrder::little >
static constexpr Data	readWithMask (const Data &value, const Data &bitmask)
static constexpr Data	writeWithMask (const Data &old, const Data &value, const Data &bitmask)

Detailed Description

Definition at line 94 of file uart8250.hh.

Constructor & Destructor Documentation

Registers()

gem5::Uart8250::Registers::Registers	(	Uart8250 *	uart,
		const std::string &	new_name
	)

Definition at line 96 of file uart8250.cc.

References gem5::RegisterBank< ByteOrder::little >::addRegisters(), gem5::Uart::device, ier, ierDlh, iir, iirFcr, lcr, lsr, mcr, msr, rbr, rbrThrDll, gem5::Uart8250::readIir(), gem5::Uart8250::readRbr(), gem5::X86ISA::reg, gem5::Uart8250::Registers::BankedRegister::select(), sr, thr, gem5::UART_MCR_LOOP, gem5::Uart8250::writeIer(), and gem5::Uart8250::writeThr().

Member Data Documentation

dlh

Register8 gem5::Uart8250::Registers::dlh = {"dlh"}

Definition at line 179 of file uart8250.hh.

dll

Register8 gem5::Uart8250::Registers::dll = {"dll"}

Definition at line 174 of file uart8250.hh.

fcr

Register8 gem5::Uart8250::Registers::fcr = {"fcr"}

Definition at line 184 of file uart8250.hh.

ier

Register<Ier> gem5::Uart8250::Registers::ier = {"ier", 0}

Definition at line 178 of file uart8250.hh.

Referenced by gem5::Uart8250::dataAvailable(), gem5::Uart8250::processIntrEvent(), gem5::Uart8250::readRbr(), Registers(), gem5::Uart8250::serialize(), gem5::Uart8250::unserialize(), and gem5::Uart8250::writeThr().

ierDlh

BankedRegister gem5::Uart8250::Registers::ierDlh

Definition at line 180 of file uart8250.hh.

Referenced by Registers().

iir

Register<Iir> gem5::Uart8250::Registers::iir = {"iir"}

Definition at line 183 of file uart8250.hh.

Referenced by Registers().

iirFcr

RWSwitchedRegister gem5::Uart8250::Registers::iirFcr

Definition at line 185 of file uart8250.hh.

Referenced by Registers().

lcr

Register<Lcr> gem5::Uart8250::Registers::lcr = {"lcr"}

Definition at line 188 of file uart8250.hh.

Referenced by Registers(), gem5::Uart8250::serialize(), and gem5::Uart8250::unserialize().

lsr

Register<Lsr> gem5::Uart8250::Registers::lsr = {"lsr"}

Definition at line 190 of file uart8250.hh.

Referenced by Registers().

mcr

Register8 gem5::Uart8250::Registers::mcr = {"mcr"}

Definition at line 189 of file uart8250.hh.

Referenced by Registers(), gem5::Uart8250::serialize(), and gem5::Uart8250::unserialize().

msr

Register8 gem5::Uart8250::Registers::msr = {"msr"}

Definition at line 191 of file uart8250.hh.

Referenced by Registers().

rbr

Register8 gem5::Uart8250::Registers::rbr = {"rbr"}

Definition at line 170 of file uart8250.hh.

Referenced by Registers().

rbrThr

RWSwitchedRegister gem5::Uart8250::Registers::rbrThr

Definition at line 172 of file uart8250.hh.

rbrThrDll

BankedRegister gem5::Uart8250::Registers::rbrThrDll

Definition at line 175 of file uart8250.hh.

Referenced by Registers().

sr

RegisterRaz gem5::Uart8250::Registers::sr = {"sr", 1}

Definition at line 194 of file uart8250.hh.

Referenced by Registers().

thr

Register8 gem5::Uart8250::Registers::thr = {"thr"}

Definition at line 171 of file uart8250.hh.

Referenced by Registers().

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The documentation for this class was generated from the following files:

• dev/serial/uart8250.hh
• dev/serial/uart8250.cc