gem5  v21.2.1.0
All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
decoder.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015-2021 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright notice,
12  * this list of conditions and the following disclaimer in the documentation
13  * and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its
16  * contributors may be used to endorse or promote products derived from this
17  * software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #include <vector>
33 
37 
38 namespace gem5
39 {
40 
41 namespace VegaISA
42 {
44  {
45  } // Decoder
46 
48  {
49  } // ~Decoder
50 
51  /*
52  * These will probably have to be updated according to the Vega ISA manual:
53  * https://developer.amd.com/wp-content/resources/
54  * Vega_Shader_ISA_28July2017.pdf
55  */
569  };
570 
1340  };
1341 
1599  };
1600 
1730  };
1731 
1861  };
1862 
1992  };
1993 
2011  };
2012 
2142  };
2143 
2273  };
2274 
2532  };
2533 
2791  };
2792 
2922  };
2923 
3053  };
3054 
3060  };
3061 
3319  };
3320 
3578  };
3579 
3709  };
3710 
3711  GPUStaticInst*
3713  {
3714  InFmt_SOP1 *enc = &mach_inst->iFmt_SOP1;
3716  return (this->*method)(mach_inst);
3717  } // decode
3718 
3719  GPUStaticInst*
3721  {
3722  InFmt_VOPC *enc = &iFmt->iFmt_VOPC;
3723  IsaDecodeMethod method = tableSubDecode_OP_VOPC[enc->OP];
3724  return (this->*method)(iFmt);
3725  } // subDecode_OP_VOPC
3726 
3727  GPUStaticInst*
3729  {
3730  InFmt_VOP3P *enc = &iFmt->iFmt_VOP3P;
3732  return (this->*method)(iFmt);
3733  } // subDecode_OP_VOP3P
3734 
3735  GPUStaticInst*
3737  {
3738  InFmt_VOP1 *enc = &iFmt->iFmt_VOP1;
3739  IsaDecodeMethod method = tableSubDecode_OP_VOP1[enc->OP];
3740  return (this->*method)(iFmt);
3741  } // subDecode_OP_VOP1
3742 
3743  GPUStaticInst*
3745  {
3746  InFmt_SOP1 *enc = &iFmt->iFmt_SOP1;
3747  IsaDecodeMethod method = tableSubDecode_OP_SOP1[enc->OP];
3748  return (this->*method)(iFmt);
3749  } // subDecode_OP_SOP1
3750 
3751  GPUStaticInst*
3753  {
3754  InFmt_SOPC *enc = &iFmt->iFmt_SOPC;
3755  IsaDecodeMethod method = tableSubDecode_OP_SOPC[enc->OP];
3756  return (this->*method)(iFmt);
3757  } // subDecode_OP_SOPC
3758 
3759  GPUStaticInst*
3761  {
3762  InFmt_SOPP *enc = &iFmt->iFmt_SOPP;
3763  IsaDecodeMethod method = tableSubDecode_OP_SOPP[enc->OP];
3764  return (this->*method)(iFmt);
3765  } // subDecode_OP_SOPP
3766 
3767  GPUStaticInst*
3769  {
3770  InFmt_SMEM *enc = &iFmt->iFmt_SMEM;
3771  IsaDecodeMethod method = tableSubDecode_OP_SMEM[enc->OP];
3772  return (this->*method)(iFmt);
3773  } // subDecode_OP_SMEM
3774 
3775  GPUStaticInst*
3777  {
3778  InFmt_VOP3A *enc = &iFmt->iFmt_VOP3A;
3780  return (this->*method)(iFmt);
3781  } // subDecode_OPU_VOP3
3782 
3783  GPUStaticInst*
3785  {
3786  InFmt_VINTRP *enc = &iFmt->iFmt_VINTRP;
3788  return (this->*method)(iFmt);
3789  } // subDecode_OP_VINTRP
3790 
3791  GPUStaticInst*
3793  {
3794  InFmt_DS *enc = &iFmt->iFmt_DS;
3795  IsaDecodeMethod method = tableSubDecode_OP_DS[enc->OP];
3796  return (this->*method)(iFmt);
3797  } // subDecode_OP_DS
3798 
3799  GPUStaticInst*
3801  {
3802  InFmt_FLAT *enc = &iFmt->iFmt_FLAT;
3803  IsaDecodeMethod method;
3804  switch (enc->SEG) {
3805  case 0:
3806  method = tableSubDecode_OP_FLAT[enc->OP];
3807  break;
3808  case 1:
3809  method = tableSubDecode_OP_SCRATCH[enc->OP];
3810  break;
3811  case 2:
3812  method = tableSubDecode_OP_GLOBAL[enc->OP];
3813  break;
3814  default:
3815  fatal("Invalid SEG for FLAT encoding: %d\n", enc->SEG);
3816  }
3817  return (this->*method)(iFmt);
3818  } // subDecode_OP_FLAT
3819 
3820  GPUStaticInst*
3822  {
3823  InFmt_MUBUF *enc = &iFmt->iFmt_MUBUF;
3825  return (this->*method)(iFmt);
3826  } // subDecode_OP_MUBUF
3827 
3828  GPUStaticInst*
3830  {
3831  InFmt_MTBUF *enc = &iFmt->iFmt_MTBUF;
3833  return (this->*method)(iFmt);
3834  } // subDecode_OP_MTBUF
3835 
3836  GPUStaticInst*
3838  {
3839  InFmt_MIMG *enc = &iFmt->iFmt_MIMG;
3840  IsaDecodeMethod method = tableSubDecode_OP_MIMG[enc->OP];
3841  return (this->*method)(iFmt);
3842  } // subDecode_OP_MIMG
3843 
3844  GPUStaticInst*
3846  {
3847  return new Inst_VOP2__V_CNDMASK_B32(&iFmt->iFmt_VOP2);
3848  } // decode_OP_VOP2__V_CNDMASK_B32
3849 
3850  GPUStaticInst*
3852  {
3853  return new Inst_VOP2__V_ADD_F32(&iFmt->iFmt_VOP2);
3854  } // decode_OP_VOP2__V_ADD_F32
3855 
3856  GPUStaticInst*
3858  {
3859  return new Inst_VOP2__V_SUB_F32(&iFmt->iFmt_VOP2);
3860  } // decode_OP_VOP2__V_SUB_F32
3861 
3862  GPUStaticInst*
3864  {
3865  return new Inst_VOP2__V_SUBREV_F32(&iFmt->iFmt_VOP2);
3866  } // decode_OP_VOP2__V_SUBREV_F32
3867 
3868  GPUStaticInst*
3870  {
3871  return new Inst_VOP2__V_MUL_LEGACY_F32(&iFmt->iFmt_VOP2);
3872  } // decode_OP_VOP2__V_MUL_LEGACY_F32
3873 
3874  GPUStaticInst*
3876  {
3877  return new Inst_VOP2__V_MUL_F32(&iFmt->iFmt_VOP2);
3878  } // decode_OP_VOP2__V_MUL_F32
3879 
3880  GPUStaticInst*
3882  {
3883  return new Inst_VOP2__V_MUL_I32_I24(&iFmt->iFmt_VOP2);
3884  } // decode_OP_VOP2__V_MUL_I32_I24
3885 
3886  GPUStaticInst*
3888  {
3889  return new Inst_VOP2__V_MUL_HI_I32_I24(&iFmt->iFmt_VOP2);
3890  } // decode_OP_VOP2__V_MUL_HI_I32_I24
3891 
3892  GPUStaticInst*
3894  {
3895  return new Inst_VOP2__V_MUL_U32_U24(&iFmt->iFmt_VOP2);
3896  } // decode_OP_VOP2__V_MUL_U32_U24
3897 
3898  GPUStaticInst*
3900  {
3901  return new Inst_VOP2__V_MUL_HI_U32_U24(&iFmt->iFmt_VOP2);
3902  } // decode_OP_VOP2__V_MUL_HI_U32_U24
3903 
3904  GPUStaticInst*
3906  {
3907  return new Inst_VOP2__V_MIN_F32(&iFmt->iFmt_VOP2);
3908  } // decode_OP_VOP2__V_MIN_F32
3909 
3910  GPUStaticInst*
3912  {
3913  return new Inst_VOP2__V_MAX_F32(&iFmt->iFmt_VOP2);
3914  } // decode_OP_VOP2__V_MAX_F32
3915 
3916  GPUStaticInst*
3918  {
3919  return new Inst_VOP2__V_MIN_I32(&iFmt->iFmt_VOP2);
3920  } // decode_OP_VOP2__V_MIN_I32
3921 
3922  GPUStaticInst*
3924  {
3925  return new Inst_VOP2__V_MAX_I32(&iFmt->iFmt_VOP2);
3926  } // decode_OP_VOP2__V_MAX_I32
3927 
3928  GPUStaticInst*
3930  {
3931  return new Inst_VOP2__V_MIN_U32(&iFmt->iFmt_VOP2);
3932  } // decode_OP_VOP2__V_MIN_U32
3933 
3934  GPUStaticInst*
3936  {
3937  return new Inst_VOP2__V_MAX_U32(&iFmt->iFmt_VOP2);
3938  } // decode_OP_VOP2__V_MAX_U32
3939 
3940  GPUStaticInst*
3942  {
3943  return new Inst_VOP2__V_LSHRREV_B32(&iFmt->iFmt_VOP2);
3944  } // decode_OP_VOP2__V_LSHRREV_B32
3945 
3946  GPUStaticInst*
3948  {
3949  return new Inst_VOP2__V_ASHRREV_I32(&iFmt->iFmt_VOP2);
3950  } // decode_OP_VOP2__V_ASHRREV_I32
3951 
3952  GPUStaticInst*
3954  {
3955  return new Inst_VOP2__V_LSHLREV_B32(&iFmt->iFmt_VOP2);
3956  } // decode_OP_VOP2__V_LSHLREV_B32
3957 
3958  GPUStaticInst*
3960  {
3961  return new Inst_VOP2__V_AND_B32(&iFmt->iFmt_VOP2);
3962  } // decode_OP_VOP2__V_AND_B32
3963 
3964  GPUStaticInst*
3966  {
3967  return new Inst_VOP2__V_OR_B32(&iFmt->iFmt_VOP2);
3968  } // decode_OP_VOP2__V_OR_B32
3969 
3970  GPUStaticInst*
3972  {
3973  return new Inst_VOP2__V_XOR_B32(&iFmt->iFmt_VOP2);
3974  } // decode_OP_VOP2__V_XOR_B32
3975 
3976  GPUStaticInst*
3978  {
3979  return new Inst_VOP2__V_MAC_F32(&iFmt->iFmt_VOP2);
3980  } // decode_OP_VOP2__V_MAC_F32
3981 
3982  GPUStaticInst*
3984  {
3985  return new Inst_VOP2__V_MADMK_F32(&iFmt->iFmt_VOP2);
3986  } // decode_OP_VOP2__V_MADMK_F32
3987 
3988  GPUStaticInst*
3990  {
3991  return new Inst_VOP2__V_MADAK_F32(&iFmt->iFmt_VOP2);
3992  } // decode_OP_VOP2__V_MADAK_F32
3993 
3994  GPUStaticInst*
3996  {
3997  return new Inst_VOP2__V_ADD_CO_U32(&iFmt->iFmt_VOP2);
3998  } // decode_OP_VOP2__V_ADD_CO_U32
3999 
4000  GPUStaticInst*
4002  {
4003  return new Inst_VOP2__V_SUB_CO_U32(&iFmt->iFmt_VOP2);
4004  } // decode_OP_VOP2__V_SUB_CO_U32
4005 
4006  GPUStaticInst*
4008  {
4009  return new Inst_VOP2__V_SUBREV_CO_U32(&iFmt->iFmt_VOP2);
4010  } // decode_OP_VOP2__V_SUBREV_CO_U32
4011 
4012  GPUStaticInst*
4014  {
4015  return new Inst_VOP2__V_ADDC_CO_U32(&iFmt->iFmt_VOP2);
4016  } // decode_OP_VOP2__V_ADDC_CO_U32
4017 
4018  GPUStaticInst*
4020  {
4021  return new Inst_VOP2__V_SUBB_CO_U32(&iFmt->iFmt_VOP2);
4022  } // decode_OP_VOP2__V_SUBB_CO_U32
4023 
4024  GPUStaticInst*
4026  {
4027  return new Inst_VOP2__V_SUBBREV_CO_U32(&iFmt->iFmt_VOP2);
4028  } // decode_OP_VOP2__V_SUBBREV_CO_U32
4029 
4030  GPUStaticInst*
4032  {
4033  return new Inst_VOP2__V_ADD_F16(&iFmt->iFmt_VOP2);
4034  } // decode_OP_VOP2__V_ADD_F16
4035 
4036  GPUStaticInst*
4038  {
4039  return new Inst_VOP2__V_SUB_F16(&iFmt->iFmt_VOP2);
4040  } // decode_OP_VOP2__V_SUB_F16
4041 
4042  GPUStaticInst*
4044  {
4045  return new Inst_VOP2__V_SUBREV_F16(&iFmt->iFmt_VOP2);
4046  } // decode_OP_VOP2__V_SUBREV_F16
4047 
4048  GPUStaticInst*
4050  {
4051  return new Inst_VOP2__V_MUL_F16(&iFmt->iFmt_VOP2);
4052  } // decode_OP_VOP2__V_MUL_F16
4053 
4054  GPUStaticInst*
4056  {
4057  return new Inst_VOP2__V_MAC_F16(&iFmt->iFmt_VOP2);
4058  } // decode_OP_VOP2__V_MAC_F16
4059 
4060  GPUStaticInst*
4062  {
4063  return new Inst_VOP2__V_MADMK_F16(&iFmt->iFmt_VOP2);
4064  } // decode_OP_VOP2__V_MADMK_F16
4065 
4066  GPUStaticInst*
4068  {
4069  return new Inst_VOP2__V_MADAK_F16(&iFmt->iFmt_VOP2);
4070  } // decode_OP_VOP2__V_MADAK_F16
4071 
4072  GPUStaticInst*
4074  {
4075  return new Inst_VOP2__V_ADD_U16(&iFmt->iFmt_VOP2);
4076  } // decode_OP_VOP2__V_ADD_U16
4077 
4078  GPUStaticInst*
4080  {
4081  return new Inst_VOP2__V_SUB_U16(&iFmt->iFmt_VOP2);
4082  } // decode_OP_VOP2__V_SUB_U16
4083 
4084  GPUStaticInst*
4086  {
4087  return new Inst_VOP2__V_SUBREV_U16(&iFmt->iFmt_VOP2);
4088  } // decode_OP_VOP2__V_SUBREV_U16
4089 
4090  GPUStaticInst*
4092  {
4093  return new Inst_VOP2__V_MUL_LO_U16(&iFmt->iFmt_VOP2);
4094  } // decode_OP_VOP2__V_MUL_LO_U16
4095 
4096  GPUStaticInst*
4098  {
4099  return new Inst_VOP2__V_LSHLREV_B16(&iFmt->iFmt_VOP2);
4100  } // decode_OP_VOP2__V_LSHLREV_B16
4101 
4102  GPUStaticInst*
4104  {
4105  return new Inst_VOP2__V_LSHRREV_B16(&iFmt->iFmt_VOP2);
4106  } // decode_OP_VOP2__V_LSHRREV_B16
4107 
4108  GPUStaticInst*
4110  {
4111  return new Inst_VOP2__V_ASHRREV_I16(&iFmt->iFmt_VOP2);
4112  } // decode_OP_VOP2__V_ASHRREV_I16
4113 
4114  GPUStaticInst*
4116  {
4117  return new Inst_VOP2__V_MAX_F16(&iFmt->iFmt_VOP2);
4118  } // decode_OP_VOP2__V_MAX_F16
4119 
4120  GPUStaticInst*
4122  {
4123  return new Inst_VOP2__V_MIN_F16(&iFmt->iFmt_VOP2);
4124  } // decode_OP_VOP2__V_MIN_F16
4125 
4126  GPUStaticInst*
4128  {
4129  return new Inst_VOP2__V_MAX_U16(&iFmt->iFmt_VOP2);
4130  } // decode_OP_VOP2__V_MAX_U16
4131 
4132  GPUStaticInst*
4134  {
4135  return new Inst_VOP2__V_MAX_I16(&iFmt->iFmt_VOP2);
4136  } // decode_OP_VOP2__V_MAX_I16
4137 
4138  GPUStaticInst*
4140  {
4141  return new Inst_VOP2__V_MIN_U16(&iFmt->iFmt_VOP2);
4142  } // decode_OP_VOP2__V_MIN_U16
4143 
4144  GPUStaticInst*
4146  {
4147  return new Inst_VOP2__V_MIN_I16(&iFmt->iFmt_VOP2);
4148  } // decode_OP_VOP2__V_MIN_I16
4149 
4150  GPUStaticInst*
4152  {
4153  return new Inst_VOP2__V_LDEXP_F16(&iFmt->iFmt_VOP2);
4154  } // decode_OP_VOP2__V_LDEXP_F16
4155 
4156  GPUStaticInst*
4158  {
4159  return new Inst_VOP2__V_ADD_U32(&iFmt->iFmt_VOP2);
4160  }
4161 
4162  GPUStaticInst*
4164  {
4165  return new Inst_VOP2__V_SUB_U32(&iFmt->iFmt_VOP2);
4166  }
4167 
4168  GPUStaticInst*
4170  {
4171  return new Inst_VOP2__V_SUBREV_U32(&iFmt->iFmt_VOP2);
4172  }
4173 
4174  GPUStaticInst*
4176  {
4177  return new Inst_SOP2__S_ADD_U32(&iFmt->iFmt_SOP2);
4178  } // decode_OP_SOP2__S_ADD_U32
4179 
4180  GPUStaticInst*
4182  {
4183  return new Inst_SOP2__S_SUB_U32(&iFmt->iFmt_SOP2);
4184  } // decode_OP_SOP2__S_SUB_U32
4185 
4186  GPUStaticInst*
4188  {
4189  return new Inst_SOP2__S_ADD_I32(&iFmt->iFmt_SOP2);
4190  } // decode_OP_SOP2__S_ADD_I32
4191 
4192  GPUStaticInst*
4194  {
4195  return new Inst_SOP2__S_SUB_I32(&iFmt->iFmt_SOP2);
4196  } // decode_OP_SOP2__S_SUB_I32
4197 
4198  GPUStaticInst*
4200  {
4201  return new Inst_SOP2__S_ADDC_U32(&iFmt->iFmt_SOP2);
4202  } // decode_OP_SOP2__S_ADDC_U32
4203 
4204  GPUStaticInst*
4206  {
4207  return new Inst_SOP2__S_SUBB_U32(&iFmt->iFmt_SOP2);
4208  } // decode_OP_SOP2__S_SUBB_U32
4209 
4210  GPUStaticInst*
4212  {
4213  return new Inst_SOP2__S_MIN_I32(&iFmt->iFmt_SOP2);
4214  } // decode_OP_SOP2__S_MIN_I32
4215 
4216  GPUStaticInst*
4218  {
4219  return new Inst_SOP2__S_MIN_U32(&iFmt->iFmt_SOP2);
4220  } // decode_OP_SOP2__S_MIN_U32
4221 
4222  GPUStaticInst*
4224  {
4225  return new Inst_SOP2__S_MAX_I32(&iFmt->iFmt_SOP2);
4226  } // decode_OP_SOP2__S_MAX_I32
4227 
4228  GPUStaticInst*
4230  {
4231  return new Inst_SOP2__S_MAX_U32(&iFmt->iFmt_SOP2);
4232  } // decode_OP_SOP2__S_MAX_U32
4233 
4234  GPUStaticInst*
4236  {
4237  return new Inst_SOP2__S_CSELECT_B32(&iFmt->iFmt_SOP2);
4238  } // decode_OP_SOP2__S_CSELECT_B32
4239 
4240  GPUStaticInst*
4242  {
4243  return new Inst_SOP2__S_CSELECT_B64(&iFmt->iFmt_SOP2);
4244  } // decode_OP_SOP2__S_CSELECT_B64
4245 
4246  GPUStaticInst*
4248  {
4249  return new Inst_SOP2__S_AND_B32(&iFmt->iFmt_SOP2);
4250  } // decode_OP_SOP2__S_AND_B32
4251 
4252  GPUStaticInst*
4254  {
4255  return new Inst_SOP2__S_AND_B64(&iFmt->iFmt_SOP2);
4256  } // decode_OP_SOP2__S_AND_B64
4257 
4258  GPUStaticInst*
4260  {
4261  return new Inst_SOP2__S_OR_B32(&iFmt->iFmt_SOP2);
4262  } // decode_OP_SOP2__S_OR_B32
4263 
4264  GPUStaticInst*
4266  {
4267  return new Inst_SOP2__S_OR_B64(&iFmt->iFmt_SOP2);
4268  } // decode_OP_SOP2__S_OR_B64
4269 
4270  GPUStaticInst*
4272  {
4273  return new Inst_SOP2__S_XOR_B32(&iFmt->iFmt_SOP2);
4274  } // decode_OP_SOP2__S_XOR_B32
4275 
4276  GPUStaticInst*
4278  {
4279  return new Inst_SOP2__S_XOR_B64(&iFmt->iFmt_SOP2);
4280  } // decode_OP_SOP2__S_XOR_B64
4281 
4282  GPUStaticInst*
4284  {
4285  return new Inst_SOP2__S_ANDN2_B32(&iFmt->iFmt_SOP2);
4286  } // decode_OP_SOP2__S_ANDN2_B32
4287 
4288  GPUStaticInst*
4290  {
4291  return new Inst_SOP2__S_ANDN2_B64(&iFmt->iFmt_SOP2);
4292  } // decode_OP_SOP2__S_ANDN2_B64
4293 
4294  GPUStaticInst*
4296  {
4297  return new Inst_SOP2__S_ORN2_B32(&iFmt->iFmt_SOP2);
4298  } // decode_OP_SOP2__S_ORN2_B32
4299 
4300  GPUStaticInst*
4302  {
4303  return new Inst_SOP2__S_ORN2_B64(&iFmt->iFmt_SOP2);
4304  } // decode_OP_SOP2__S_ORN2_B64
4305 
4306  GPUStaticInst*
4308  {
4309  return new Inst_SOP2__S_NAND_B32(&iFmt->iFmt_SOP2);
4310  } // decode_OP_SOP2__S_NAND_B32
4311 
4312  GPUStaticInst*
4314  {
4315  return new Inst_SOP2__S_NAND_B64(&iFmt->iFmt_SOP2);
4316  } // decode_OP_SOP2__S_NAND_B64
4317 
4318  GPUStaticInst*
4320  {
4321  return new Inst_SOP2__S_NOR_B32(&iFmt->iFmt_SOP2);
4322  } // decode_OP_SOP2__S_NOR_B32
4323 
4324  GPUStaticInst*
4326  {
4327  return new Inst_SOP2__S_NOR_B64(&iFmt->iFmt_SOP2);
4328  } // decode_OP_SOP2__S_NOR_B64
4329 
4330  GPUStaticInst*
4332  {
4333  return new Inst_SOP2__S_XNOR_B32(&iFmt->iFmt_SOP2);
4334  } // decode_OP_SOP2__S_XNOR_B32
4335 
4336  GPUStaticInst*
4338  {
4339  return new Inst_SOP2__S_XNOR_B64(&iFmt->iFmt_SOP2);
4340  } // decode_OP_SOP2__S_XNOR_B64
4341 
4342  GPUStaticInst*
4344  {
4345  return new Inst_SOP2__S_LSHL_B32(&iFmt->iFmt_SOP2);
4346  } // decode_OP_SOP2__S_LSHL_B32
4347 
4348  GPUStaticInst*
4350  {
4351  return new Inst_SOP2__S_LSHL_B64(&iFmt->iFmt_SOP2);
4352  } // decode_OP_SOP2__S_LSHL_B64
4353 
4354  GPUStaticInst*
4356  {
4357  return new Inst_SOP2__S_LSHR_B32(&iFmt->iFmt_SOP2);
4358  } // decode_OP_SOP2__S_LSHR_B32
4359 
4360  GPUStaticInst*
4362  {
4363  return new Inst_SOP2__S_LSHR_B64(&iFmt->iFmt_SOP2);
4364  } // decode_OP_SOP2__S_LSHR_B64
4365 
4366  GPUStaticInst*
4368  {
4369  return new Inst_SOP2__S_ASHR_I32(&iFmt->iFmt_SOP2);
4370  } // decode_OP_SOP2__S_ASHR_I32
4371 
4372  GPUStaticInst*
4374  {
4375  return new Inst_SOP2__S_ASHR_I64(&iFmt->iFmt_SOP2);
4376  } // decode_OP_SOP2__S_ASHR_I64
4377 
4378  GPUStaticInst*
4380  {
4381  return new Inst_SOP2__S_BFM_B32(&iFmt->iFmt_SOP2);
4382  } // decode_OP_SOP2__S_BFM_B32
4383 
4384  GPUStaticInst*
4386  {
4387  return new Inst_SOP2__S_BFM_B64(&iFmt->iFmt_SOP2);
4388  } // decode_OP_SOP2__S_BFM_B64
4389 
4390  GPUStaticInst*
4392  {
4393  return new Inst_SOP2__S_MUL_I32(&iFmt->iFmt_SOP2);
4394  } // decode_OP_SOP2__S_MUL_I32
4395 
4396  GPUStaticInst*
4398  {
4399  return new Inst_SOP2__S_BFE_U32(&iFmt->iFmt_SOP2);
4400  } // decode_OP_SOP2__S_BFE_U32
4401 
4402  GPUStaticInst*
4404  {
4405  return new Inst_SOP2__S_BFE_I32(&iFmt->iFmt_SOP2);
4406  } // decode_OP_SOP2__S_BFE_I32
4407 
4408  GPUStaticInst*
4410  {
4411  return new Inst_SOP2__S_BFE_U64(&iFmt->iFmt_SOP2);
4412  } // decode_OP_SOP2__S_BFE_U64
4413 
4414  GPUStaticInst*
4416  {
4417  return new Inst_SOP2__S_BFE_I64(&iFmt->iFmt_SOP2);
4418  } // decode_OP_SOP2__S_BFE_I64
4419 
4420  GPUStaticInst*
4422  {
4423  return new Inst_SOP2__S_CBRANCH_G_FORK(&iFmt->iFmt_SOP2);
4424  } // decode_OP_SOP2__S_CBRANCH_G_FORK
4425 
4426  GPUStaticInst*
4428  {
4429  return new Inst_SOP2__S_ABSDIFF_I32(&iFmt->iFmt_SOP2);
4430  } // decode_OP_SOP2__S_ABSDIFF_I32
4431 
4432  GPUStaticInst*
4434  {
4435  return new Inst_SOP2__S_RFE_RESTORE_B64(&iFmt->iFmt_SOP2);
4436  } // decode_OP_SOP2__S_RFE_RESTORE_B64
4437 
4438  GPUStaticInst*
4440  {
4441  fatal("Trying to decode instruction without a class\n");
4442  return nullptr;
4443  }
4444 
4445  GPUStaticInst*
4447  {
4448  return new Inst_SOP2__S_MUL_I32(&iFmt->iFmt_SOP2);
4449  }
4450 
4451  GPUStaticInst*
4453  {
4454  fatal("Trying to decode instruction without a class\n");
4455  return nullptr;
4456  }
4457 
4458  GPUStaticInst*
4460  {
4461  fatal("Trying to decode instruction without a class\n");
4462  return nullptr;
4463  }
4464 
4465  GPUStaticInst*
4467  {
4468  fatal("Trying to decode instruction without a class\n");
4469  return nullptr;
4470  }
4471 
4472  GPUStaticInst*
4474  {
4475  fatal("Trying to decode instruction without a class\n");
4476  return nullptr;
4477  }
4478 
4479  GPUStaticInst*
4481  {
4482  fatal("Trying to decode instruction without a class\n");
4483  return nullptr;
4484  }
4485 
4486  GPUStaticInst*
4488  {
4489  fatal("Trying to decode instruction without a class\n");
4490  return nullptr;
4491  }
4492 
4493  GPUStaticInst*
4495  {
4496  fatal("Trying to decode instruction without a class\n");
4497  return nullptr;
4498  }
4499 
4500  GPUStaticInst*
4502  {
4503  return new Inst_SOPK__S_MOVK_I32(&iFmt->iFmt_SOPK);
4504  } // decode_OP_SOPK__S_MOVK_I32
4505 
4506  GPUStaticInst*
4508  {
4509  return new Inst_SOPK__S_CMOVK_I32(&iFmt->iFmt_SOPK);
4510  } // decode_OP_SOPK__S_CMOVK_I32
4511 
4512  GPUStaticInst*
4514  {
4515  return new Inst_SOPK__S_CMPK_EQ_I32(&iFmt->iFmt_SOPK);
4516  } // decode_OP_SOPK__S_CMPK_EQ_I32
4517 
4518  GPUStaticInst*
4520  {
4521  return new Inst_SOPK__S_CMPK_LG_I32(&iFmt->iFmt_SOPK);
4522  } // decode_OP_SOPK__S_CMPK_LG_I32
4523 
4524  GPUStaticInst*
4526  {
4527  return new Inst_SOPK__S_CMPK_GT_I32(&iFmt->iFmt_SOPK);
4528  } // decode_OP_SOPK__S_CMPK_GT_I32
4529 
4530  GPUStaticInst*
4532  {
4533  return new Inst_SOPK__S_CMPK_GE_I32(&iFmt->iFmt_SOPK);
4534  } // decode_OP_SOPK__S_CMPK_GE_I32
4535 
4536  GPUStaticInst*
4538  {
4539  return new Inst_SOPK__S_CMPK_LT_I32(&iFmt->iFmt_SOPK);
4540  } // decode_OP_SOPK__S_CMPK_LT_I32
4541 
4542  GPUStaticInst*
4544  {
4545  return new Inst_SOPK__S_CMPK_LE_I32(&iFmt->iFmt_SOPK);
4546  } // decode_OP_SOPK__S_CMPK_LE_I32
4547 
4548  GPUStaticInst*
4550  {
4551  return new Inst_SOPK__S_CMPK_EQ_U32(&iFmt->iFmt_SOPK);
4552  } // decode_OP_SOPK__S_CMPK_EQ_U32
4553 
4554  GPUStaticInst*
4556  {
4557  return new Inst_SOPK__S_CMPK_LG_U32(&iFmt->iFmt_SOPK);
4558  } // decode_OP_SOPK__S_CMPK_LG_U32
4559 
4560  GPUStaticInst*
4562  {
4563  return new Inst_SOPK__S_CMPK_GT_U32(&iFmt->iFmt_SOPK);
4564  } // decode_OP_SOPK__S_CMPK_GT_U32
4565 
4566  GPUStaticInst*
4568  {
4569  return new Inst_SOPK__S_CMPK_GE_U32(&iFmt->iFmt_SOPK);
4570  } // decode_OP_SOPK__S_CMPK_GE_U32
4571 
4572  GPUStaticInst*
4574  {
4575  return new Inst_SOPK__S_CMPK_LT_U32(&iFmt->iFmt_SOPK);
4576  } // decode_OP_SOPK__S_CMPK_LT_U32
4577 
4578  GPUStaticInst*
4580  {
4581  return new Inst_SOPK__S_CMPK_LE_U32(&iFmt->iFmt_SOPK);
4582  } // decode_OP_SOPK__S_CMPK_LE_U32
4583 
4584  GPUStaticInst*
4586  {
4587  return new Inst_SOPK__S_ADDK_I32(&iFmt->iFmt_SOPK);
4588  } // decode_OP_SOPK__S_ADDK_I32
4589 
4590  GPUStaticInst*
4592  {
4593  return new Inst_SOPK__S_MULK_I32(&iFmt->iFmt_SOPK);
4594  } // decode_OP_SOPK__S_MULK_I32
4595 
4596  GPUStaticInst*
4598  {
4599  return new Inst_SOPK__S_CBRANCH_I_FORK(&iFmt->iFmt_SOPK);
4600  } // decode_OP_SOPK__S_CBRANCH_I_FORK
4601 
4602  GPUStaticInst*
4604  {
4605  return new Inst_SOPK__S_GETREG_B32(&iFmt->iFmt_SOPK);
4606  } // decode_OP_SOPK__S_GETREG_B32
4607 
4608  GPUStaticInst*
4610  {
4611  return new Inst_SOPK__S_SETREG_B32(&iFmt->iFmt_SOPK);
4612  } // decode_OP_SOPK__S_SETREG_B32
4613 
4614  GPUStaticInst*
4616  {
4617  return new Inst_SOPK__S_SETREG_IMM32_B32(&iFmt->iFmt_SOPK);
4618  } // decode_OP_SOPK__S_SETREG_IMM32_B32
4619 
4620  GPUStaticInst*
4622  {
4623  fatal("Trying to decode instruction without a class\n");
4624  return nullptr;
4625  }
4626 
4627  GPUStaticInst*
4629  {
4630  return new Inst_EXP__EXP(&iFmt->iFmt_EXP);
4631  } // decode_OP_EXP
4632 
4633  GPUStaticInst*
4635  {
4636  return new Inst_VOP3__V_CMP_CLASS_F32(&iFmt->iFmt_VOP3A);
4637  } // decode_OPU_VOP3__V_CMP_CLASS_F32
4638 
4639  GPUStaticInst*
4641  {
4642  return new Inst_VOP3__V_CMPX_CLASS_F32(&iFmt->iFmt_VOP3A);
4643  } // decode_OPU_VOP3__V_CMPX_CLASS_F32
4644 
4645  GPUStaticInst*
4647  {
4648  return new Inst_VOP3__V_CMP_CLASS_F64(&iFmt->iFmt_VOP3A);
4649  } // decode_OPU_VOP3__V_CMP_CLASS_F64
4650 
4651  GPUStaticInst*
4653  {
4654  return new Inst_VOP3__V_CMPX_CLASS_F64(&iFmt->iFmt_VOP3A);
4655  } // decode_OPU_VOP3__V_CMPX_CLASS_F64
4656 
4657  GPUStaticInst*
4659  {
4660  return new Inst_VOP3__V_CMP_CLASS_F16(&iFmt->iFmt_VOP3A);
4661  } // decode_OPU_VOP3__V_CMP_CLASS_F16
4662 
4663  GPUStaticInst*
4665  {
4666  return new Inst_VOP3__V_CMPX_CLASS_F16(&iFmt->iFmt_VOP3A);
4667  } // decode_OPU_VOP3__V_CMPX_CLASS_F16
4668 
4669  GPUStaticInst*
4671  {
4672  return new Inst_VOP3__V_CMP_F_F16(&iFmt->iFmt_VOP3A);
4673  } // decode_OPU_VOP3__V_CMP_F_F16
4674 
4675  GPUStaticInst*
4677  {
4678  return new Inst_VOP3__V_CMP_LT_F16(&iFmt->iFmt_VOP3A);
4679  } // decode_OPU_VOP3__V_CMP_LT_F16
4680 
4681  GPUStaticInst*
4683  {
4684  return new Inst_VOP3__V_CMP_EQ_F16(&iFmt->iFmt_VOP3A);
4685  } // decode_OPU_VOP3__V_CMP_EQ_F16
4686 
4687  GPUStaticInst*
4689  {
4690  return new Inst_VOP3__V_CMP_LE_F16(&iFmt->iFmt_VOP3A);
4691  } // decode_OPU_VOP3__V_CMP_LE_F16
4692 
4693  GPUStaticInst*
4695  {
4696  return new Inst_VOP3__V_CMP_GT_F16(&iFmt->iFmt_VOP3A);
4697  } // decode_OPU_VOP3__V_CMP_GT_F16
4698 
4699  GPUStaticInst*
4701  {
4702  return new Inst_VOP3__V_CMP_LG_F16(&iFmt->iFmt_VOP3A);
4703  } // decode_OPU_VOP3__V_CMP_LG_F16
4704 
4705  GPUStaticInst*
4707  {
4708  return new Inst_VOP3__V_CMP_GE_F16(&iFmt->iFmt_VOP3A);
4709  } // decode_OPU_VOP3__V_CMP_GE_F16
4710 
4711  GPUStaticInst*
4713  {
4714  return new Inst_VOP3__V_CMP_O_F16(&iFmt->iFmt_VOP3A);
4715  } // decode_OPU_VOP3__V_CMP_O_F16
4716 
4717  GPUStaticInst*
4719  {
4720  return new Inst_VOP3__V_CMP_U_F16(&iFmt->iFmt_VOP3A);
4721  } // decode_OPU_VOP3__V_CMP_U_F16
4722 
4723  GPUStaticInst*
4725  {
4726  return new Inst_VOP3__V_CMP_NGE_F16(&iFmt->iFmt_VOP3A);
4727  } // decode_OPU_VOP3__V_CMP_NGE_F16
4728 
4729  GPUStaticInst*
4731  {
4732  return new Inst_VOP3__V_CMP_NLG_F16(&iFmt->iFmt_VOP3A);
4733  } // decode_OPU_VOP3__V_CMP_NLG_F16
4734 
4735  GPUStaticInst*
4737  {
4738  return new Inst_VOP3__V_CMP_NGT_F16(&iFmt->iFmt_VOP3A);
4739  } // decode_OPU_VOP3__V_CMP_NGT_F16
4740 
4741  GPUStaticInst*
4743  {
4744  return new Inst_VOP3__V_CMP_NLE_F16(&iFmt->iFmt_VOP3A);
4745  } // decode_OPU_VOP3__V_CMP_NLE_F16
4746 
4747  GPUStaticInst*
4749  {
4750  return new Inst_VOP3__V_CMP_NEQ_F16(&iFmt->iFmt_VOP3A);
4751  } // decode_OPU_VOP3__V_CMP_NEQ_F16
4752 
4753  GPUStaticInst*
4755  {
4756  return new Inst_VOP3__V_CMP_NLT_F16(&iFmt->iFmt_VOP3A);
4757  } // decode_OPU_VOP3__V_CMP_NLT_F16
4758 
4759  GPUStaticInst*
4761  {
4762  return new Inst_VOP3__V_CMP_TRU_F16(&iFmt->iFmt_VOP3A);
4763  } // decode_OPU_VOP3__V_CMP_TRU_F16
4764 
4765  GPUStaticInst*
4767  {
4768  return new Inst_VOP3__V_CMPX_F_F16(&iFmt->iFmt_VOP3A);
4769  } // decode_OPU_VOP3__V_CMPX_F_F16
4770 
4771  GPUStaticInst*
4773  {
4774  return new Inst_VOP3__V_CMPX_LT_F16(&iFmt->iFmt_VOP3A);
4775  } // decode_OPU_VOP3__V_CMPX_LT_F16
4776 
4777  GPUStaticInst*
4779  {
4780  return new Inst_VOP3__V_CMPX_EQ_F16(&iFmt->iFmt_VOP3A);
4781  } // decode_OPU_VOP3__V_CMPX_EQ_F16
4782 
4783  GPUStaticInst*
4785  {
4786  return new Inst_VOP3__V_CMPX_LE_F16(&iFmt->iFmt_VOP3A);
4787  } // decode_OPU_VOP3__V_CMPX_LE_F16
4788 
4789  GPUStaticInst*
4791  {
4792  return new Inst_VOP3__V_CMPX_GT_F16(&iFmt->iFmt_VOP3A);
4793  } // decode_OPU_VOP3__V_CMPX_GT_F16
4794 
4795  GPUStaticInst*
4797  {
4798  return new Inst_VOP3__V_CMPX_LG_F16(&iFmt->iFmt_VOP3A);
4799  } // decode_OPU_VOP3__V_CMPX_LG_F16
4800 
4801  GPUStaticInst*
4803  {
4804  return new Inst_VOP3__V_CMPX_GE_F16(&iFmt->iFmt_VOP3A);
4805  } // decode_OPU_VOP3__V_CMPX_GE_F16
4806 
4807  GPUStaticInst*
4809  {
4810  return new Inst_VOP3__V_CMPX_O_F16(&iFmt->iFmt_VOP3A);
4811  } // decode_OPU_VOP3__V_CMPX_O_F16
4812 
4813  GPUStaticInst*
4815  {
4816  return new Inst_VOP3__V_CMPX_U_F16(&iFmt->iFmt_VOP3A);
4817  } // decode_OPU_VOP3__V_CMPX_U_F16
4818 
4819  GPUStaticInst*
4821  {
4822  return new Inst_VOP3__V_CMPX_NGE_F16(&iFmt->iFmt_VOP3A);
4823  } // decode_OPU_VOP3__V_CMPX_NGE_F16
4824 
4825  GPUStaticInst*
4827  {
4828  return new Inst_VOP3__V_CMPX_NLG_F16(&iFmt->iFmt_VOP3A);
4829  } // decode_OPU_VOP3__V_CMPX_NLG_F16
4830 
4831  GPUStaticInst*
4833  {
4834  return new Inst_VOP3__V_CMPX_NGT_F16(&iFmt->iFmt_VOP3A);
4835  } // decode_OPU_VOP3__V_CMPX_NGT_F16
4836 
4837  GPUStaticInst*
4839  {
4840  return new Inst_VOP3__V_CMPX_NLE_F16(&iFmt->iFmt_VOP3A);
4841  } // decode_OPU_VOP3__V_CMPX_NLE_F16
4842 
4843  GPUStaticInst*
4845  {
4846  return new Inst_VOP3__V_CMPX_NEQ_F16(&iFmt->iFmt_VOP3A);
4847  } // decode_OPU_VOP3__V_CMPX_NEQ_F16
4848 
4849  GPUStaticInst*
4851  {
4852  return new Inst_VOP3__V_CMPX_NLT_F16(&iFmt->iFmt_VOP3A);
4853  } // decode_OPU_VOP3__V_CMPX_NLT_F16
4854 
4855  GPUStaticInst*
4857  {
4858  return new Inst_VOP3__V_CMPX_TRU_F16(&iFmt->iFmt_VOP3A);
4859  } // decode_OPU_VOP3__V_CMPX_TRU_F16
4860 
4861  GPUStaticInst*
4863  {
4864  return new Inst_VOP3__V_CMP_F_F32(&iFmt->iFmt_VOP3A);
4865  } // decode_OPU_VOP3__V_CMP_F_F32
4866 
4867  GPUStaticInst*
4869  {
4870  return new Inst_VOP3__V_CMP_LT_F32(&iFmt->iFmt_VOP3A);
4871  } // decode_OPU_VOP3__V_CMP_LT_F32
4872 
4873  GPUStaticInst*
4875  {
4876  return new Inst_VOP3__V_CMP_EQ_F32(&iFmt->iFmt_VOP3A);
4877  } // decode_OPU_VOP3__V_CMP_EQ_F32
4878 
4879  GPUStaticInst*
4881  {
4882  return new Inst_VOP3__V_CMP_LE_F32(&iFmt->iFmt_VOP3A);
4883  } // decode_OPU_VOP3__V_CMP_LE_F32
4884 
4885  GPUStaticInst*
4887  {
4888  return new Inst_VOP3__V_CMP_GT_F32(&iFmt->iFmt_VOP3A);
4889  } // decode_OPU_VOP3__V_CMP_GT_F32
4890 
4891  GPUStaticInst*
4893  {
4894  return new Inst_VOP3__V_CMP_LG_F32(&iFmt->iFmt_VOP3A);
4895  } // decode_OPU_VOP3__V_CMP_LG_F32
4896 
4897  GPUStaticInst*
4899  {
4900  return new Inst_VOP3__V_CMP_GE_F32(&iFmt->iFmt_VOP3A);
4901  } // decode_OPU_VOP3__V_CMP_GE_F32
4902 
4903  GPUStaticInst*
4905  {
4906  return new Inst_VOP3__V_CMP_O_F32(&iFmt->iFmt_VOP3A);
4907  } // decode_OPU_VOP3__V_CMP_O_F32
4908 
4909  GPUStaticInst*
4911  {
4912  return new Inst_VOP3__V_CMP_U_F32(&iFmt->iFmt_VOP3A);
4913  } // decode_OPU_VOP3__V_CMP_U_F32
4914 
4915  GPUStaticInst*
4917  {
4918  return new Inst_VOP3__V_CMP_NGE_F32(&iFmt->iFmt_VOP3A);
4919  } // decode_OPU_VOP3__V_CMP_NGE_F32
4920 
4921  GPUStaticInst*
4923  {
4924  return new Inst_VOP3__V_CMP_NLG_F32(&iFmt->iFmt_VOP3A);
4925  } // decode_OPU_VOP3__V_CMP_NLG_F32
4926 
4927  GPUStaticInst*
4929  {
4930  return new Inst_VOP3__V_CMP_NGT_F32(&iFmt->iFmt_VOP3A);
4931  } // decode_OPU_VOP3__V_CMP_NGT_F32
4932 
4933  GPUStaticInst*
4935  {
4936  return new Inst_VOP3__V_CMP_NLE_F32(&iFmt->iFmt_VOP3A);
4937  } // decode_OPU_VOP3__V_CMP_NLE_F32
4938 
4939  GPUStaticInst*
4941  {
4942  return new Inst_VOP3__V_CMP_NEQ_F32(&iFmt->iFmt_VOP3A);
4943  } // decode_OPU_VOP3__V_CMP_NEQ_F32
4944 
4945  GPUStaticInst*
4947  {
4948  return new Inst_VOP3__V_CMP_NLT_F32(&iFmt->iFmt_VOP3A);
4949  } // decode_OPU_VOP3__V_CMP_NLT_F32
4950 
4951  GPUStaticInst*
4953  {
4954  return new Inst_VOP3__V_CMP_TRU_F32(&iFmt->iFmt_VOP3A);
4955  } // decode_OPU_VOP3__V_CMP_TRU_F32
4956 
4957  GPUStaticInst*
4959  {
4960  return new Inst_VOP3__V_CMPX_F_F32(&iFmt->iFmt_VOP3A);
4961  } // decode_OPU_VOP3__V_CMPX_F_F32
4962 
4963  GPUStaticInst*
4965  {
4966  return new Inst_VOP3__V_CMPX_LT_F32(&iFmt->iFmt_VOP3A);
4967  } // decode_OPU_VOP3__V_CMPX_LT_F32
4968 
4969  GPUStaticInst*
4971  {
4972  return new Inst_VOP3__V_CMPX_EQ_F32(&iFmt->iFmt_VOP3A);
4973  } // decode_OPU_VOP3__V_CMPX_EQ_F32
4974 
4975  GPUStaticInst*
4977  {
4978  return new Inst_VOP3__V_CMPX_LE_F32(&iFmt->iFmt_VOP3A);
4979  } // decode_OPU_VOP3__V_CMPX_LE_F32
4980 
4981  GPUStaticInst*
4983  {
4984  return new Inst_VOP3__V_CMPX_GT_F32(&iFmt->iFmt_VOP3A);
4985  } // decode_OPU_VOP3__V_CMPX_GT_F32
4986 
4987  GPUStaticInst*
4989  {
4990  return new Inst_VOP3__V_CMPX_LG_F32(&iFmt->iFmt_VOP3A);
4991  } // decode_OPU_VOP3__V_CMPX_LG_F32
4992 
4993  GPUStaticInst*
4995  {
4996  return new Inst_VOP3__V_CMPX_GE_F32(&iFmt->iFmt_VOP3A);
4997  } // decode_OPU_VOP3__V_CMPX_GE_F32
4998 
4999  GPUStaticInst*
5001  {
5002  return new Inst_VOP3__V_CMPX_O_F32(&iFmt->iFmt_VOP3A);
5003  } // decode_OPU_VOP3__V_CMPX_O_F32
5004 
5005  GPUStaticInst*
5007  {
5008  return new Inst_VOP3__V_CMPX_U_F32(&iFmt->iFmt_VOP3A);
5009  } // decode_OPU_VOP3__V_CMPX_U_F32
5010 
5011  GPUStaticInst*
5013  {
5014  return new Inst_VOP3__V_CMPX_NGE_F32(&iFmt->iFmt_VOP3A);
5015  } // decode_OPU_VOP3__V_CMPX_NGE_F32
5016 
5017  GPUStaticInst*
5019  {
5020  return new Inst_VOP3__V_CMPX_NLG_F32(&iFmt->iFmt_VOP3A);
5021  } // decode_OPU_VOP3__V_CMPX_NLG_F32
5022 
5023  GPUStaticInst*
5025  {
5026  return new Inst_VOP3__V_CMPX_NGT_F32(&iFmt->iFmt_VOP3A);
5027  } // decode_OPU_VOP3__V_CMPX_NGT_F32
5028 
5029  GPUStaticInst*
5031  {
5032  return new Inst_VOP3__V_CMPX_NLE_F32(&iFmt->iFmt_VOP3A);
5033  } // decode_OPU_VOP3__V_CMPX_NLE_F32
5034 
5035  GPUStaticInst*
5037  {
5038  return new Inst_VOP3__V_CMPX_NEQ_F32(&iFmt->iFmt_VOP3A);
5039  } // decode_OPU_VOP3__V_CMPX_NEQ_F32
5040 
5041  GPUStaticInst*
5043  {
5044  return new Inst_VOP3__V_CMPX_NLT_F32(&iFmt->iFmt_VOP3A);
5045  } // decode_OPU_VOP3__V_CMPX_NLT_F32
5046 
5047  GPUStaticInst*
5049  {
5050  return new Inst_VOP3__V_CMPX_TRU_F32(&iFmt->iFmt_VOP3A);
5051  } // decode_OPU_VOP3__V_CMPX_TRU_F32
5052 
5053  GPUStaticInst*
5055  {
5056  return new Inst_VOP3__V_CMP_F_F64(&iFmt->iFmt_VOP3A);
5057  } // decode_OPU_VOP3__V_CMP_F_F64
5058 
5059  GPUStaticInst*
5061  {
5062  return new Inst_VOP3__V_CMP_LT_F64(&iFmt->iFmt_VOP3A);
5063  } // decode_OPU_VOP3__V_CMP_LT_F64
5064 
5065  GPUStaticInst*
5067  {
5068  return new Inst_VOP3__V_CMP_EQ_F64(&iFmt->iFmt_VOP3A);
5069  } // decode_OPU_VOP3__V_CMP_EQ_F64
5070 
5071  GPUStaticInst*
5073  {
5074  return new Inst_VOP3__V_CMP_LE_F64(&iFmt->iFmt_VOP3A);
5075  } // decode_OPU_VOP3__V_CMP_LE_F64
5076 
5077  GPUStaticInst*
5079  {
5080  return new Inst_VOP3__V_CMP_GT_F64(&iFmt->iFmt_VOP3A);
5081  } // decode_OPU_VOP3__V_CMP_GT_F64
5082 
5083  GPUStaticInst*
5085  {
5086  return new Inst_VOP3__V_CMP_LG_F64(&iFmt->iFmt_VOP3A);
5087  } // decode_OPU_VOP3__V_CMP_LG_F64
5088 
5089  GPUStaticInst*
5091  {
5092  return new Inst_VOP3__V_CMP_GE_F64(&iFmt->iFmt_VOP3A);
5093  } // decode_OPU_VOP3__V_CMP_GE_F64
5094 
5095  GPUStaticInst*
5097  {
5098  return new Inst_VOP3__V_CMP_O_F64(&iFmt->iFmt_VOP3A);
5099  } // decode_OPU_VOP3__V_CMP_O_F64
5100 
5101  GPUStaticInst*
5103  {
5104  return new Inst_VOP3__V_CMP_U_F64(&iFmt->iFmt_VOP3A);
5105  } // decode_OPU_VOP3__V_CMP_U_F64
5106 
5107  GPUStaticInst*
5109  {
5110  return new Inst_VOP3__V_CMP_NGE_F64(&iFmt->iFmt_VOP3A);
5111  } // decode_OPU_VOP3__V_CMP_NGE_F64
5112 
5113  GPUStaticInst*
5115  {
5116  return new Inst_VOP3__V_CMP_NLG_F64(&iFmt->iFmt_VOP3A);
5117  } // decode_OPU_VOP3__V_CMP_NLG_F64
5118 
5119  GPUStaticInst*
5121  {
5122  return new Inst_VOP3__V_CMP_NGT_F64(&iFmt->iFmt_VOP3A);
5123  } // decode_OPU_VOP3__V_CMP_NGT_F64
5124 
5125  GPUStaticInst*
5127  {
5128  return new Inst_VOP3__V_CMP_NLE_F64(&iFmt->iFmt_VOP3A);
5129  } // decode_OPU_VOP3__V_CMP_NLE_F64
5130 
5131  GPUStaticInst*
5133  {
5134  return new Inst_VOP3__V_CMP_NEQ_F64(&iFmt->iFmt_VOP3A);
5135  } // decode_OPU_VOP3__V_CMP_NEQ_F64
5136 
5137  GPUStaticInst*
5139  {
5140  return new Inst_VOP3__V_CMP_NLT_F64(&iFmt->iFmt_VOP3A);
5141  } // decode_OPU_VOP3__V_CMP_NLT_F64
5142 
5143  GPUStaticInst*
5145  {
5146  return new Inst_VOP3__V_CMP_TRU_F64(&iFmt->iFmt_VOP3A);
5147  } // decode_OPU_VOP3__V_CMP_TRU_F64
5148 
5149  GPUStaticInst*
5151  {
5152  return new Inst_VOP3__V_CMPX_F_F64(&iFmt->iFmt_VOP3A);
5153  } // decode_OPU_VOP3__V_CMPX_F_F64
5154 
5155  GPUStaticInst*
5157  {
5158  return new Inst_VOP3__V_CMPX_LT_F64(&iFmt->iFmt_VOP3A);
5159  } // decode_OPU_VOP3__V_CMPX_LT_F64
5160 
5161  GPUStaticInst*
5163  {
5164  return new Inst_VOP3__V_CMPX_EQ_F64(&iFmt->iFmt_VOP3A);
5165  } // decode_OPU_VOP3__V_CMPX_EQ_F64
5166 
5167  GPUStaticInst*
5169  {
5170  return new Inst_VOP3__V_CMPX_LE_F64(&iFmt->iFmt_VOP3A);
5171  } // decode_OPU_VOP3__V_CMPX_LE_F64
5172 
5173  GPUStaticInst*
5175  {
5176  return new Inst_VOP3__V_CMPX_GT_F64(&iFmt->iFmt_VOP3A);
5177  } // decode_OPU_VOP3__V_CMPX_GT_F64
5178 
5179  GPUStaticInst*
5181  {
5182  return new Inst_VOP3__V_CMPX_LG_F64(&iFmt->iFmt_VOP3A);
5183  } // decode_OPU_VOP3__V_CMPX_LG_F64
5184 
5185  GPUStaticInst*
5187  {
5188  return new Inst_VOP3__V_CMPX_GE_F64(&iFmt->iFmt_VOP3A);
5189  } // decode_OPU_VOP3__V_CMPX_GE_F64
5190 
5191  GPUStaticInst*
5193  {
5194  return new Inst_VOP3__V_CMPX_O_F64(&iFmt->iFmt_VOP3A);
5195  } // decode_OPU_VOP3__V_CMPX_O_F64
5196 
5197  GPUStaticInst*
5199  {
5200  return new Inst_VOP3__V_CMPX_U_F64(&iFmt->iFmt_VOP3A);
5201  } // decode_OPU_VOP3__V_CMPX_U_F64
5202 
5203  GPUStaticInst*
5205  {
5206  return new Inst_VOP3__V_CMPX_NGE_F64(&iFmt->iFmt_VOP3A);
5207  } // decode_OPU_VOP3__V_CMPX_NGE_F64
5208 
5209  GPUStaticInst*
5211  {
5212  return new Inst_VOP3__V_CMPX_NLG_F64(&iFmt->iFmt_VOP3A);
5213  } // decode_OPU_VOP3__V_CMPX_NLG_F64
5214 
5215  GPUStaticInst*
5217  {
5218  return new Inst_VOP3__V_CMPX_NGT_F64(&iFmt->iFmt_VOP3A);
5219  } // decode_OPU_VOP3__V_CMPX_NGT_F64
5220 
5221  GPUStaticInst*
5223  {
5224  return new Inst_VOP3__V_CMPX_NLE_F64(&iFmt->iFmt_VOP3A);
5225  } // decode_OPU_VOP3__V_CMPX_NLE_F64
5226 
5227  GPUStaticInst*
5229  {
5230  return new Inst_VOP3__V_CMPX_NEQ_F64(&iFmt->iFmt_VOP3A);
5231  } // decode_OPU_VOP3__V_CMPX_NEQ_F64
5232 
5233  GPUStaticInst*
5235  {
5236  return new Inst_VOP3__V_CMPX_NLT_F64(&iFmt->iFmt_VOP3A);
5237  } // decode_OPU_VOP3__V_CMPX_NLT_F64
5238 
5239  GPUStaticInst*
5241  {
5242  return new Inst_VOP3__V_CMPX_TRU_F64(&iFmt->iFmt_VOP3A);
5243  } // decode_OPU_VOP3__V_CMPX_TRU_F64
5244 
5245  GPUStaticInst*
5247  {
5248  return new Inst_VOP3__V_CMP_F_I16(&iFmt->iFmt_VOP3A);
5249  } // decode_OPU_VOP3__V_CMP_F_I16
5250 
5251  GPUStaticInst*
5253  {
5254  return new Inst_VOP3__V_CMP_LT_I16(&iFmt->iFmt_VOP3A);
5255  } // decode_OPU_VOP3__V_CMP_LT_I16
5256 
5257  GPUStaticInst*
5259  {
5260  return new Inst_VOP3__V_CMP_EQ_I16(&iFmt->iFmt_VOP3A);
5261  } // decode_OPU_VOP3__V_CMP_EQ_I16
5262 
5263  GPUStaticInst*
5265  {
5266  return new Inst_VOP3__V_CMP_LE_I16(&iFmt->iFmt_VOP3A);
5267  } // decode_OPU_VOP3__V_CMP_LE_I16
5268 
5269  GPUStaticInst*
5271  {
5272  return new Inst_VOP3__V_CMP_GT_I16(&iFmt->iFmt_VOP3A);
5273  } // decode_OPU_VOP3__V_CMP_GT_I16
5274 
5275  GPUStaticInst*
5277  {
5278  return new Inst_VOP3__V_CMP_NE_I16(&iFmt->iFmt_VOP3A);
5279  } // decode_OPU_VOP3__V_CMP_NE_I16
5280 
5281  GPUStaticInst*
5283  {
5284  return new Inst_VOP3__V_CMP_GE_I16(&iFmt->iFmt_VOP3A);
5285  } // decode_OPU_VOP3__V_CMP_GE_I16
5286 
5287  GPUStaticInst*
5289  {
5290  return new Inst_VOP3__V_CMP_T_I16(&iFmt->iFmt_VOP3A);
5291  } // decode_OPU_VOP3__V_CMP_T_I16
5292 
5293  GPUStaticInst*
5295  {
5296  return new Inst_VOP3__V_CMP_F_U16(&iFmt->iFmt_VOP3A);
5297  } // decode_OPU_VOP3__V_CMP_F_U16
5298 
5299  GPUStaticInst*
5301  {
5302  return new Inst_VOP3__V_CMP_LT_U16(&iFmt->iFmt_VOP3A);
5303  } // decode_OPU_VOP3__V_CMP_LT_U16
5304 
5305  GPUStaticInst*
5307  {
5308  return new Inst_VOP3__V_CMP_EQ_U16(&iFmt->iFmt_VOP3A);
5309  } // decode_OPU_VOP3__V_CMP_EQ_U16
5310 
5311  GPUStaticInst*
5313  {
5314  return new Inst_VOP3__V_CMP_LE_U16(&iFmt->iFmt_VOP3A);
5315  } // decode_OPU_VOP3__V_CMP_LE_U16
5316 
5317  GPUStaticInst*
5319  {
5320  return new Inst_VOP3__V_CMP_GT_U16(&iFmt->iFmt_VOP3A);
5321  } // decode_OPU_VOP3__V_CMP_GT_U16
5322 
5323  GPUStaticInst*
5325  {
5326  return new Inst_VOP3__V_CMP_NE_U16(&iFmt->iFmt_VOP3A);
5327  } // decode_OPU_VOP3__V_CMP_NE_U16
5328 
5329  GPUStaticInst*
5331  {
5332  return new Inst_VOP3__V_CMP_GE_U16(&iFmt->iFmt_VOP3A);
5333  } // decode_OPU_VOP3__V_CMP_GE_U16
5334 
5335  GPUStaticInst*
5337  {
5338  return new Inst_VOP3__V_CMP_T_U16(&iFmt->iFmt_VOP3A);
5339  } // decode_OPU_VOP3__V_CMP_T_U16
5340 
5341  GPUStaticInst*
5343  {
5344  return new Inst_VOP3__V_CMPX_F_I16(&iFmt->iFmt_VOP3A);
5345  } // decode_OPU_VOP3__V_CMPX_F_I16
5346 
5347  GPUStaticInst*
5349  {
5350  return new Inst_VOP3__V_CMPX_LT_I16(&iFmt->iFmt_VOP3A);
5351  } // decode_OPU_VOP3__V_CMPX_LT_I16
5352 
5353  GPUStaticInst*
5355  {
5356  return new Inst_VOP3__V_CMPX_EQ_I16(&iFmt->iFmt_VOP3A);
5357  } // decode_OPU_VOP3__V_CMPX_EQ_I16
5358 
5359  GPUStaticInst*
5361  {
5362  return new Inst_VOP3__V_CMPX_LE_I16(&iFmt->iFmt_VOP3A);
5363  } // decode_OPU_VOP3__V_CMPX_LE_I16
5364 
5365  GPUStaticInst*
5367  {
5368  return new Inst_VOP3__V_CMPX_GT_I16(&iFmt->iFmt_VOP3A);
5369  } // decode_OPU_VOP3__V_CMPX_GT_I16
5370 
5371  GPUStaticInst*
5373  {
5374  return new Inst_VOP3__V_CMPX_NE_I16(&iFmt->iFmt_VOP3A);
5375  } // decode_OPU_VOP3__V_CMPX_NE_I16
5376 
5377  GPUStaticInst*
5379  {
5380  return new Inst_VOP3__V_CMPX_GE_I16(&iFmt->iFmt_VOP3A);
5381  } // decode_OPU_VOP3__V_CMPX_GE_I16
5382 
5383  GPUStaticInst*
5385  {
5386  return new Inst_VOP3__V_CMPX_T_I16(&iFmt->iFmt_VOP3A);
5387  } // decode_OPU_VOP3__V_CMPX_T_I16
5388 
5389  GPUStaticInst*
5391  {
5392  return new Inst_VOP3__V_CMPX_F_U16(&iFmt->iFmt_VOP3A);
5393  } // decode_OPU_VOP3__V_CMPX_F_U16
5394 
5395  GPUStaticInst*
5397  {
5398  return new Inst_VOP3__V_CMPX_LT_U16(&iFmt->iFmt_VOP3A);
5399  } // decode_OPU_VOP3__V_CMPX_LT_U16
5400 
5401  GPUStaticInst*
5403  {
5404  return new Inst_VOP3__V_CMPX_EQ_U16(&iFmt->iFmt_VOP3A);
5405  } // decode_OPU_VOP3__V_CMPX_EQ_U16
5406 
5407  GPUStaticInst*
5409  {
5410  return new Inst_VOP3__V_CMPX_LE_U16(&iFmt->iFmt_VOP3A);
5411  } // decode_OPU_VOP3__V_CMPX_LE_U16
5412 
5413  GPUStaticInst*
5415  {
5416  return new Inst_VOP3__V_CMPX_GT_U16(&iFmt->iFmt_VOP3A);
5417  } // decode_OPU_VOP3__V_CMPX_GT_U16
5418 
5419  GPUStaticInst*
5421  {
5422  return new Inst_VOP3__V_CMPX_NE_U16(&iFmt->iFmt_VOP3A);
5423  } // decode_OPU_VOP3__V_CMPX_NE_U16
5424 
5425  GPUStaticInst*
5427  {
5428  return new Inst_VOP3__V_CMPX_GE_U16(&iFmt->iFmt_VOP3A);
5429  } // decode_OPU_VOP3__V_CMPX_GE_U16
5430 
5431  GPUStaticInst*
5433  {
5434  return new Inst_VOP3__V_CMPX_T_U16(&iFmt->iFmt_VOP3A);
5435  } // decode_OPU_VOP3__V_CMPX_T_U16
5436 
5437  GPUStaticInst*
5439  {
5440  return new Inst_VOP3__V_CMP_F_I32(&iFmt->iFmt_VOP3A);
5441  } // decode_OPU_VOP3__V_CMP_F_I32
5442 
5443  GPUStaticInst*
5445  {
5446  return new Inst_VOP3__V_CMP_LT_I32(&iFmt->iFmt_VOP3A);
5447  } // decode_OPU_VOP3__V_CMP_LT_I32
5448 
5449  GPUStaticInst*
5451  {
5452  return new Inst_VOP3__V_CMP_EQ_I32(&iFmt->iFmt_VOP3A);
5453  } // decode_OPU_VOP3__V_CMP_EQ_I32
5454 
5455  GPUStaticInst*
5457  {
5458  return new Inst_VOP3__V_CMP_LE_I32(&iFmt->iFmt_VOP3A);
5459  } // decode_OPU_VOP3__V_CMP_LE_I32
5460 
5461  GPUStaticInst*
5463  {
5464  return new Inst_VOP3__V_CMP_GT_I32(&iFmt->iFmt_VOP3A);
5465  } // decode_OPU_VOP3__V_CMP_GT_I32
5466 
5467  GPUStaticInst*
5469  {
5470  return new Inst_VOP3__V_CMP_NE_I32(&iFmt->iFmt_VOP3A);
5471  } // decode_OPU_VOP3__V_CMP_NE_I32
5472 
5473  GPUStaticInst*
5475  {
5476  return new Inst_VOP3__V_CMP_GE_I32(&iFmt->iFmt_VOP3A);
5477  } // decode_OPU_VOP3__V_CMP_GE_I32
5478 
5479  GPUStaticInst*
5481  {
5482  return new Inst_VOP3__V_CMP_T_I32(&iFmt->iFmt_VOP3A);
5483  } // decode_OPU_VOP3__V_CMP_T_I32
5484 
5485  GPUStaticInst*
5487  {
5488  return new Inst_VOP3__V_CMP_F_U32(&iFmt->iFmt_VOP3A);
5489  } // decode_OPU_VOP3__V_CMP_F_U32
5490 
5491  GPUStaticInst*
5493  {
5494  return new Inst_VOP3__V_CMP_LT_U32(&iFmt->iFmt_VOP3A);
5495  } // decode_OPU_VOP3__V_CMP_LT_U32
5496 
5497  GPUStaticInst*
5499  {
5500  return new Inst_VOP3__V_CMP_EQ_U32(&iFmt->iFmt_VOP3A);
5501  } // decode_OPU_VOP3__V_CMP_EQ_U32
5502 
5503  GPUStaticInst*
5505  {
5506  return new Inst_VOP3__V_CMP_LE_U32(&iFmt->iFmt_VOP3A);
5507  } // decode_OPU_VOP3__V_CMP_LE_U32
5508 
5509  GPUStaticInst*
5511  {
5512  return new Inst_VOP3__V_CMP_GT_U32(&iFmt->iFmt_VOP3A);
5513  } // decode_OPU_VOP3__V_CMP_GT_U32
5514 
5515  GPUStaticInst*
5517  {
5518  return new Inst_VOP3__V_CMP_NE_U32(&iFmt->iFmt_VOP3A);
5519  } // decode_OPU_VOP3__V_CMP_NE_U32
5520 
5521  GPUStaticInst*
5523  {
5524  return new Inst_VOP3__V_CMP_GE_U32(&iFmt->iFmt_VOP3A);
5525  } // decode_OPU_VOP3__V_CMP_GE_U32
5526 
5527  GPUStaticInst*
5529  {
5530  return new Inst_VOP3__V_CMP_T_U32(&iFmt->iFmt_VOP3A);
5531  } // decode_OPU_VOP3__V_CMP_T_U32
5532 
5533  GPUStaticInst*
5535  {
5536  return new Inst_VOP3__V_CMPX_F_I32(&iFmt->iFmt_VOP3A);
5537  } // decode_OPU_VOP3__V_CMPX_F_I32
5538 
5539  GPUStaticInst*
5541  {
5542  return new Inst_VOP3__V_CMPX_LT_I32(&iFmt->iFmt_VOP3A);
5543  } // decode_OPU_VOP3__V_CMPX_LT_I32
5544 
5545  GPUStaticInst*
5547  {
5548  return new Inst_VOP3__V_CMPX_EQ_I32(&iFmt->iFmt_VOP3A);
5549  } // decode_OPU_VOP3__V_CMPX_EQ_I32
5550 
5551  GPUStaticInst*
5553  {
5554  return new Inst_VOP3__V_CMPX_LE_I32(&iFmt->iFmt_VOP3A);
5555  } // decode_OPU_VOP3__V_CMPX_LE_I32
5556 
5557  GPUStaticInst*
5559  {
5560  return new Inst_VOP3__V_CMPX_GT_I32(&iFmt->iFmt_VOP3A);
5561  } // decode_OPU_VOP3__V_CMPX_GT_I32
5562 
5563  GPUStaticInst*
5565  {
5566  return new Inst_VOP3__V_CMPX_NE_I32(&iFmt->iFmt_VOP3A);
5567  } // decode_OPU_VOP3__V_CMPX_NE_I32
5568 
5569  GPUStaticInst*
5571  {
5572  return new Inst_VOP3__V_CMPX_GE_I32(&iFmt->iFmt_VOP3A);
5573  } // decode_OPU_VOP3__V_CMPX_GE_I32
5574 
5575  GPUStaticInst*
5577  {
5578  return new Inst_VOP3__V_CMPX_T_I32(&iFmt->iFmt_VOP3A);
5579  } // decode_OPU_VOP3__V_CMPX_T_I32
5580 
5581  GPUStaticInst*
5583  {
5584  return new Inst_VOP3__V_CMPX_F_U32(&iFmt->iFmt_VOP3A);
5585  } // decode_OPU_VOP3__V_CMPX_F_U32
5586 
5587  GPUStaticInst*
5589  {
5590  return new Inst_VOP3__V_CMPX_LT_U32(&iFmt->iFmt_VOP3A);
5591  } // decode_OPU_VOP3__V_CMPX_LT_U32
5592 
5593  GPUStaticInst*
5595  {
5596  return new Inst_VOP3__V_CMPX_EQ_U32(&iFmt->iFmt_VOP3A);
5597  } // decode_OPU_VOP3__V_CMPX_EQ_U32
5598 
5599  GPUStaticInst*
5601  {
5602  return new Inst_VOP3__V_CMPX_LE_U32(&iFmt->iFmt_VOP3A);
5603  } // decode_OPU_VOP3__V_CMPX_LE_U32
5604 
5605  GPUStaticInst*
5607  {
5608  return new Inst_VOP3__V_CMPX_GT_U32(&iFmt->iFmt_VOP3A);
5609  } // decode_OPU_VOP3__V_CMPX_GT_U32
5610 
5611  GPUStaticInst*
5613  {
5614  return new Inst_VOP3__V_CMPX_NE_U32(&iFmt->iFmt_VOP3A);
5615  } // decode_OPU_VOP3__V_CMPX_NE_U32
5616 
5617  GPUStaticInst*
5619  {
5620  return new Inst_VOP3__V_CMPX_GE_U32(&iFmt->iFmt_VOP3A);
5621  } // decode_OPU_VOP3__V_CMPX_GE_U32
5622 
5623  GPUStaticInst*
5625  {
5626  return new Inst_VOP3__V_CMPX_T_U32(&iFmt->iFmt_VOP3A);
5627  } // decode_OPU_VOP3__V_CMPX_T_U32
5628 
5629  GPUStaticInst*
5631  {
5632  return new Inst_VOP3__V_CMP_F_I64(&iFmt->iFmt_VOP3A);
5633  } // decode_OPU_VOP3__V_CMP_F_I64
5634 
5635  GPUStaticInst*
5637  {
5638  return new Inst_VOP3__V_CMP_LT_I64(&iFmt->iFmt_VOP3A);
5639  } // decode_OPU_VOP3__V_CMP_LT_I64
5640 
5641  GPUStaticInst*
5643  {
5644  return new Inst_VOP3__V_CMP_EQ_I64(&iFmt->iFmt_VOP3A);
5645  } // decode_OPU_VOP3__V_CMP_EQ_I64
5646 
5647  GPUStaticInst*
5649  {
5650  return new Inst_VOP3__V_CMP_LE_I64(&iFmt->iFmt_VOP3A);
5651  } // decode_OPU_VOP3__V_CMP_LE_I64
5652 
5653  GPUStaticInst*
5655  {
5656  return new Inst_VOP3__V_CMP_GT_I64(&iFmt->iFmt_VOP3A);
5657  } // decode_OPU_VOP3__V_CMP_GT_I64
5658 
5659  GPUStaticInst*
5661  {
5662  return new Inst_VOP3__V_CMP_NE_I64(&iFmt->iFmt_VOP3A);
5663  } // decode_OPU_VOP3__V_CMP_NE_I64
5664 
5665  GPUStaticInst*
5667  {
5668  return new Inst_VOP3__V_CMP_GE_I64(&iFmt->iFmt_VOP3A);
5669  } // decode_OPU_VOP3__V_CMP_GE_I64
5670 
5671  GPUStaticInst*
5673  {
5674  return new Inst_VOP3__V_CMP_T_I64(&iFmt->iFmt_VOP3A);
5675  } // decode_OPU_VOP3__V_CMP_T_I64
5676 
5677  GPUStaticInst*
5679  {
5680  return new Inst_VOP3__V_CMP_F_U64(&iFmt->iFmt_VOP3A);
5681  } // decode_OPU_VOP3__V_CMP_F_U64
5682 
5683  GPUStaticInst*
5685  {
5686  return new Inst_VOP3__V_CMP_LT_U64(&iFmt->iFmt_VOP3A);
5687  } // decode_OPU_VOP3__V_CMP_LT_U64
5688 
5689  GPUStaticInst*
5691  {
5692  return new Inst_VOP3__V_CMP_EQ_U64(&iFmt->iFmt_VOP3A);
5693  } // decode_OPU_VOP3__V_CMP_EQ_U64
5694 
5695  GPUStaticInst*
5697  {
5698  return new Inst_VOP3__V_CMP_LE_U64(&iFmt->iFmt_VOP3A);
5699  } // decode_OPU_VOP3__V_CMP_LE_U64
5700 
5701  GPUStaticInst*
5703  {
5704  return new Inst_VOP3__V_CMP_GT_U64(&iFmt->iFmt_VOP3A);
5705  } // decode_OPU_VOP3__V_CMP_GT_U64
5706 
5707  GPUStaticInst*
5709  {
5710  return new Inst_VOP3__V_CMP_NE_U64(&iFmt->iFmt_VOP3A);
5711  } // decode_OPU_VOP3__V_CMP_NE_U64
5712 
5713  GPUStaticInst*
5715  {
5716  return new Inst_VOP3__V_CMP_GE_U64(&iFmt->iFmt_VOP3A);
5717  } // decode_OPU_VOP3__V_CMP_GE_U64
5718 
5719  GPUStaticInst*
5721  {
5722  return new Inst_VOP3__V_CMP_T_U64(&iFmt->iFmt_VOP3A);
5723  } // decode_OPU_VOP3__V_CMP_T_U64
5724 
5725  GPUStaticInst*
5727  {
5728  return new Inst_VOP3__V_CMPX_F_I64(&iFmt->iFmt_VOP3A);
5729  } // decode_OPU_VOP3__V_CMPX_F_I64
5730 
5731  GPUStaticInst*
5733  {
5734  return new Inst_VOP3__V_CMPX_LT_I64(&iFmt->iFmt_VOP3A);
5735  } // decode_OPU_VOP3__V_CMPX_LT_I64
5736 
5737  GPUStaticInst*
5739  {
5740  return new Inst_VOP3__V_CMPX_EQ_I64(&iFmt->iFmt_VOP3A);
5741  } // decode_OPU_VOP3__V_CMPX_EQ_I64
5742 
5743  GPUStaticInst*
5745  {
5746  return new Inst_VOP3__V_CMPX_LE_I64(&iFmt->iFmt_VOP3A);
5747  } // decode_OPU_VOP3__V_CMPX_LE_I64
5748 
5749  GPUStaticInst*
5751  {
5752  return new Inst_VOP3__V_CMPX_GT_I64(&iFmt->iFmt_VOP3A);
5753  } // decode_OPU_VOP3__V_CMPX_GT_I64
5754 
5755  GPUStaticInst*
5757  {
5758  return new Inst_VOP3__V_CMPX_NE_I64(&iFmt->iFmt_VOP3A);
5759  } // decode_OPU_VOP3__V_CMPX_NE_I64
5760 
5761  GPUStaticInst*
5763  {
5764  return new Inst_VOP3__V_CMPX_GE_I64(&iFmt->iFmt_VOP3A);
5765  } // decode_OPU_VOP3__V_CMPX_GE_I64
5766 
5767  GPUStaticInst*
5769  {
5770  return new Inst_VOP3__V_CMPX_T_I64(&iFmt->iFmt_VOP3A);
5771  } // decode_OPU_VOP3__V_CMPX_T_I64
5772 
5773  GPUStaticInst*
5775  {
5776  return new Inst_VOP3__V_CMPX_F_U64(&iFmt->iFmt_VOP3A);
5777  } // decode_OPU_VOP3__V_CMPX_F_U64
5778 
5779  GPUStaticInst*
5781  {
5782  return new Inst_VOP3__V_CMPX_LT_U64(&iFmt->iFmt_VOP3A);
5783  } // decode_OPU_VOP3__V_CMPX_LT_U64
5784 
5785  GPUStaticInst*
5787  {
5788  return new Inst_VOP3__V_CMPX_EQ_U64(&iFmt->iFmt_VOP3A);
5789  } // decode_OPU_VOP3__V_CMPX_EQ_U64
5790 
5791  GPUStaticInst*
5793  {
5794  return new Inst_VOP3__V_CMPX_LE_U64(&iFmt->iFmt_VOP3A);
5795  } // decode_OPU_VOP3__V_CMPX_LE_U64
5796 
5797  GPUStaticInst*
5799  {
5800  return new Inst_VOP3__V_CMPX_GT_U64(&iFmt->iFmt_VOP3A);
5801  } // decode_OPU_VOP3__V_CMPX_GT_U64
5802 
5803  GPUStaticInst*
5805  {
5806  return new Inst_VOP3__V_CMPX_NE_U64(&iFmt->iFmt_VOP3A);
5807  } // decode_OPU_VOP3__V_CMPX_NE_U64
5808 
5809  GPUStaticInst*
5811  {
5812  return new Inst_VOP3__V_CMPX_GE_U64(&iFmt->iFmt_VOP3A);
5813  } // decode_OPU_VOP3__V_CMPX_GE_U64
5814 
5815  GPUStaticInst*
5817  {
5818  return new Inst_VOP3__V_CMPX_T_U64(&iFmt->iFmt_VOP3A);
5819  } // decode_OPU_VOP3__V_CMPX_T_U64
5820 
5821  GPUStaticInst*
5823  {
5824  return new Inst_VOP3__V_CNDMASK_B32(&iFmt->iFmt_VOP3A);
5825  } // decode_OPU_VOP3__V_CNDMASK_B32
5826 
5827  GPUStaticInst*
5829  {
5830  return new Inst_VOP3__V_ADD_F32(&iFmt->iFmt_VOP3A);
5831  } // decode_OPU_VOP3__V_ADD_F32
5832 
5833  GPUStaticInst*
5835  {
5836  return new Inst_VOP3__V_SUB_F32(&iFmt->iFmt_VOP3A);
5837  } // decode_OPU_VOP3__V_SUB_F32
5838 
5839  GPUStaticInst*
5841  {
5842  return new Inst_VOP3__V_SUBREV_F32(&iFmt->iFmt_VOP3A);
5843  } // decode_OPU_VOP3__V_SUBREV_F32
5844 
5845  GPUStaticInst*
5847  {
5848  return new Inst_VOP3__V_MUL_LEGACY_F32(&iFmt->iFmt_VOP3A);
5849  } // decode_OPU_VOP3__V_MUL_LEGACY_F32
5850 
5851  GPUStaticInst*
5853  {
5854  return new Inst_VOP3__V_MUL_F32(&iFmt->iFmt_VOP3A);
5855  } // decode_OPU_VOP3__V_MUL_F32
5856 
5857  GPUStaticInst*
5859  {
5860  return new Inst_VOP3__V_MUL_I32_I24(&iFmt->iFmt_VOP3A);
5861  } // decode_OPU_VOP3__V_MUL_I32_I24
5862 
5863  GPUStaticInst*
5865  {
5866  return new Inst_VOP3__V_MUL_HI_I32_I24(&iFmt->iFmt_VOP3A);
5867  } // decode_OPU_VOP3__V_MUL_HI_I32_I24
5868 
5869  GPUStaticInst*
5871  {
5872  return new Inst_VOP3__V_MUL_U32_U24(&iFmt->iFmt_VOP3A);
5873  } // decode_OPU_VOP3__V_MUL_U32_U24
5874 
5875  GPUStaticInst*
5877  {
5878  return new Inst_VOP3__V_MUL_HI_U32_U24(&iFmt->iFmt_VOP3A);
5879  } // decode_OPU_VOP3__V_MUL_HI_U32_U24
5880 
5881  GPUStaticInst*
5883  {
5884  return new Inst_VOP3__V_MIN_F32(&iFmt->iFmt_VOP3A);
5885  } // decode_OPU_VOP3__V_MIN_F32
5886 
5887  GPUStaticInst*
5889  {
5890  return new Inst_VOP3__V_MAX_F32(&iFmt->iFmt_VOP3A);
5891  } // decode_OPU_VOP3__V_MAX_F32
5892 
5893  GPUStaticInst*
5895  {
5896  return new Inst_VOP3__V_MIN_I32(&iFmt->iFmt_VOP3A);
5897  } // decode_OPU_VOP3__V_MIN_I32
5898 
5899  GPUStaticInst*
5901  {
5902  return new Inst_VOP3__V_MAX_I32(&iFmt->iFmt_VOP3A);
5903  } // decode_OPU_VOP3__V_MAX_I32
5904 
5905  GPUStaticInst*
5907  {
5908  return new Inst_VOP3__V_MIN_U32(&iFmt->iFmt_VOP3A);
5909  } // decode_OPU_VOP3__V_MIN_U32
5910 
5911  GPUStaticInst*
5913  {
5914  return new Inst_VOP3__V_MAX_U32(&iFmt->iFmt_VOP3A);
5915  } // decode_OPU_VOP3__V_MAX_U32
5916 
5917  GPUStaticInst*
5919  {
5920  return new Inst_VOP3__V_LSHRREV_B32(&iFmt->iFmt_VOP3A);
5921  } // decode_OPU_VOP3__V_LSHRREV_B32
5922 
5923  GPUStaticInst*
5925  {
5926  return new Inst_VOP3__V_ASHRREV_I32(&iFmt->iFmt_VOP3A);
5927  } // decode_OPU_VOP3__V_ASHRREV_I32
5928 
5929  GPUStaticInst*
5931  {
5932  return new Inst_VOP3__V_LSHLREV_B32(&iFmt->iFmt_VOP3A);
5933  } // decode_OPU_VOP3__V_LSHLREV_B32
5934 
5935  GPUStaticInst*
5937  {
5938  return new Inst_VOP3__V_AND_B32(&iFmt->iFmt_VOP3A);
5939  } // decode_OPU_VOP3__V_AND_B32
5940 
5941  GPUStaticInst*
5943  {
5944  return new Inst_VOP3__V_OR_B32(&iFmt->iFmt_VOP3A);
5945  } // decode_OPU_VOP3__V_OR_B32
5946 
5947  GPUStaticInst*
5949  {
5950  return new Inst_VOP3__V_XOR_B32(&iFmt->iFmt_VOP3A);
5951  } // decode_OPU_VOP3__V_XOR_B32
5952 
5953  GPUStaticInst*
5955  {
5956  return new Inst_VOP3__V_MAC_F32(&iFmt->iFmt_VOP3A);
5957  } // decode_OPU_VOP3__V_MAC_F32
5958 
5959  GPUStaticInst*
5961  {
5962  return new Inst_VOP3__V_ADD_CO_U32(&iFmt->iFmt_VOP3B);
5963  } // decode_OPU_VOP3__V_ADD_CO_U32
5964 
5965  GPUStaticInst*
5967  {
5968  return new Inst_VOP3__V_SUB_CO_U32(&iFmt->iFmt_VOP3B);
5969  } // decode_OPU_VOP3__V_SUB_CO_U32
5970 
5971  GPUStaticInst*
5973  {
5974  return new Inst_VOP3__V_SUBREV_CO_U32(&iFmt->iFmt_VOP3B);
5975  } // decode_OPU_VOP3__V_SUBREV_CO_U32
5976 
5977  GPUStaticInst*
5979  {
5980  return new Inst_VOP3__V_ADDC_CO_U32(&iFmt->iFmt_VOP3B);
5981  } // decode_OPU_VOP3__V_ADDC_CO_U32
5982 
5983  GPUStaticInst*
5985  {
5986  return new Inst_VOP3__V_SUBB_CO_U32(&iFmt->iFmt_VOP3B);
5987  } // decode_OPU_VOP3__V_SUBB_CO_U32
5988 
5989  GPUStaticInst*
5991  {
5992  return new Inst_VOP3__V_SUBBREV_CO_U32(&iFmt->iFmt_VOP3B);
5993  } // decode_OPU_VOP3__V_SUBBREV_CO_U32
5994 
5995  GPUStaticInst*
5997  {
5998  return new Inst_VOP3__V_ADD_F16(&iFmt->iFmt_VOP3A);
5999  } // decode_OPU_VOP3__V_ADD_F16
6000 
6001  GPUStaticInst*
6003  {
6004  return new Inst_VOP3__V_SUB_F16(&iFmt->iFmt_VOP3A);
6005  } // decode_OPU_VOP3__V_SUB_F16
6006 
6007  GPUStaticInst*
6009  {
6010  return new Inst_VOP3__V_SUBREV_F16(&iFmt->iFmt_VOP3A);
6011  } // decode_OPU_VOP3__V_SUBREV_F16
6012 
6013  GPUStaticInst*
6015  {
6016  return new Inst_VOP3__V_MUL_F16(&iFmt->iFmt_VOP3A);
6017  } // decode_OPU_VOP3__V_MUL_F16
6018 
6019  GPUStaticInst*
6021  {
6022  return new Inst_VOP3__V_MAC_F16(&iFmt->iFmt_VOP3A);
6023  } // decode_OPU_VOP3__V_MAC_F16
6024 
6025  GPUStaticInst*
6027  {
6028  return new Inst_VOP3__V_ADD_U16(&iFmt->iFmt_VOP3A);
6029  } // decode_OPU_VOP3__V_ADD_U16
6030 
6031  GPUStaticInst*
6033  {
6034  return new Inst_VOP3__V_SUB_U16(&iFmt->iFmt_VOP3A);
6035  } // decode_OPU_VOP3__V_SUB_U16
6036 
6037  GPUStaticInst*
6039  {
6040  return new Inst_VOP3__V_SUBREV_U16(&iFmt->iFmt_VOP3A);
6041  } // decode_OPU_VOP3__V_SUBREV_U16
6042 
6043  GPUStaticInst*
6045  {
6046  return new Inst_VOP3__V_MUL_LO_U16(&iFmt->iFmt_VOP3A);
6047  } // decode_OPU_VOP3__V_MUL_LO_U16
6048 
6049  GPUStaticInst*
6051  {
6052  return new Inst_VOP3__V_LSHLREV_B16(&iFmt->iFmt_VOP3A);
6053  } // decode_OPU_VOP3__V_LSHLREV_B16
6054 
6055  GPUStaticInst*
6057  {
6058  return new Inst_VOP3__V_LSHRREV_B16(&iFmt->iFmt_VOP3A);
6059  } // decode_OPU_VOP3__V_LSHRREV_B16
6060 
6061  GPUStaticInst*
6063  {
6064  return new Inst_VOP3__V_ASHRREV_I16(&iFmt->iFmt_VOP3A);
6065  } // decode_OPU_VOP3__V_ASHRREV_I16
6066 
6067  GPUStaticInst*
6069  {
6070  return new Inst_VOP3__V_MAX_F16(&iFmt->iFmt_VOP3A);
6071  } // decode_OPU_VOP3__V_MAX_F16
6072 
6073  GPUStaticInst*
6075  {
6076  return new Inst_VOP3__V_MIN_F16(&iFmt->iFmt_VOP3A);
6077  } // decode_OPU_VOP3__V_MIN_F16
6078 
6079  GPUStaticInst*
6081  {
6082  return new Inst_VOP3__V_MAX_U16(&iFmt->iFmt_VOP3A);
6083  } // decode_OPU_VOP3__V_MAX_U16
6084 
6085  GPUStaticInst*
6087  {
6088  return new Inst_VOP3__V_MAX_I16(&iFmt->iFmt_VOP3A);
6089  } // decode_OPU_VOP3__V_MAX_I16
6090 
6091  GPUStaticInst*
6093  {
6094  return new Inst_VOP3__V_MIN_U16(&iFmt->iFmt_VOP3A);
6095  } // decode_OPU_VOP3__V_MIN_U16
6096 
6097  GPUStaticInst*
6099  {
6100  return new Inst_VOP3__V_MIN_I16(&iFmt->iFmt_VOP3A);
6101  } // decode_OPU_VOP3__V_MIN_I16
6102 
6103  GPUStaticInst*
6105  {
6106  return new Inst_VOP3__V_LDEXP_F16(&iFmt->iFmt_VOP3A);
6107  } // decode_OPU_VOP3__V_LDEXP_F16
6108 
6109  GPUStaticInst*
6111  {
6112  return new Inst_VOP3__V_NOP(&iFmt->iFmt_VOP3A);
6113  } // decode_OPU_VOP3__V_NOP
6114 
6115  GPUStaticInst*
6117  {
6118  return new Inst_VOP3__V_MOV_B32(&iFmt->iFmt_VOP3A);
6119  } // decode_OPU_VOP3__V_MOV_B32
6120 
6121  GPUStaticInst*
6123  {
6124  return new Inst_VOP3__V_CVT_I32_F64(&iFmt->iFmt_VOP3A);
6125  } // decode_OPU_VOP3__V_CVT_I32_F64
6126 
6127  GPUStaticInst*
6129  {
6130  return new Inst_VOP3__V_CVT_F64_I32(&iFmt->iFmt_VOP3A);
6131  } // decode_OPU_VOP3__V_CVT_F64_I32
6132 
6133  GPUStaticInst*
6135  {
6136  return new Inst_VOP3__V_CVT_F32_I32(&iFmt->iFmt_VOP3A);
6137  } // decode_OPU_VOP3__V_CVT_F32_I32
6138 
6139  GPUStaticInst*
6141  {
6142  return new Inst_VOP3__V_CVT_F32_U32(&iFmt->iFmt_VOP3A);
6143  } // decode_OPU_VOP3__V_CVT_F32_U32
6144 
6145  GPUStaticInst*
6147  {
6148  return new Inst_VOP3__V_CVT_U32_F32(&iFmt->iFmt_VOP3A);
6149  } // decode_OPU_VOP3__V_CVT_U32_F32
6150 
6151  GPUStaticInst*
6153  {
6154  return new Inst_VOP3__V_CVT_I32_F32(&iFmt->iFmt_VOP3A);
6155  } // decode_OPU_VOP3__V_CVT_I32_F32
6156 
6157  GPUStaticInst*
6159  {
6160  return new Inst_VOP3__V_MOV_FED_B32(&iFmt->iFmt_VOP3A);
6161  } // decode_OPU_VOP3__V_MOV_FED_B32
6162 
6163  GPUStaticInst*
6165  {
6166  return new Inst_VOP3__V_CVT_F16_F32(&iFmt->iFmt_VOP3A);
6167  } // decode_OPU_VOP3__V_CVT_F16_F32
6168 
6169  GPUStaticInst*
6171  {
6172  return new Inst_VOP3__V_CVT_F32_F16(&iFmt->iFmt_VOP3A);
6173  } // decode_OPU_VOP3__V_CVT_F32_F16
6174 
6175  GPUStaticInst*
6177  {
6178  return new Inst_VOP3__V_CVT_RPI_I32_F32(&iFmt->iFmt_VOP3A);
6179  } // decode_OPU_VOP3__V_CVT_RPI_I32_F32
6180 
6181  GPUStaticInst*
6183  {
6184  return new Inst_VOP3__V_CVT_FLR_I32_F32(&iFmt->iFmt_VOP3A);
6185  } // decode_OPU_VOP3__V_CVT_FLR_I32_F32
6186 
6187  GPUStaticInst*
6189  {
6190  return new Inst_VOP3__V_CVT_OFF_F32_I4(&iFmt->iFmt_VOP3A);
6191  } // decode_OPU_VOP3__V_CVT_OFF_F32_I4
6192 
6193  GPUStaticInst*
6195  {
6196  return new Inst_VOP3__V_CVT_F32_F64(&iFmt->iFmt_VOP3A);
6197  } // decode_OPU_VOP3__V_CVT_F32_F64
6198 
6199  GPUStaticInst*
6201  {
6202  return new Inst_VOP3__V_CVT_F64_F32(&iFmt->iFmt_VOP3A);
6203  } // decode_OPU_VOP3__V_CVT_F64_F32
6204 
6205  GPUStaticInst*
6207  {
6208  return new Inst_VOP3__V_CVT_F32_UBYTE0(&iFmt->iFmt_VOP3A);
6209  } // decode_OPU_VOP3__V_CVT_F32_UBYTE0
6210 
6211  GPUStaticInst*
6213  {
6214  return new Inst_VOP3__V_CVT_F32_UBYTE1(&iFmt->iFmt_VOP3A);
6215  } // decode_OPU_VOP3__V_CVT_F32_UBYTE1
6216 
6217  GPUStaticInst*
6219  {
6220  return new Inst_VOP3__V_CVT_F32_UBYTE2(&iFmt->iFmt_VOP3A);
6221  } // decode_OPU_VOP3__V_CVT_F32_UBYTE2
6222 
6223  GPUStaticInst*
6225  {
6226  return new Inst_VOP3__V_CVT_F32_UBYTE3(&iFmt->iFmt_VOP3A);
6227  } // decode_OPU_VOP3__V_CVT_F32_UBYTE3
6228 
6229  GPUStaticInst*
6231  {
6232  return new Inst_VOP3__V_CVT_U32_F64(&iFmt->iFmt_VOP3A);
6233  } // decode_OPU_VOP3__V_CVT_U32_F64
6234 
6235  GPUStaticInst*
6237  {
6238  return new Inst_VOP3__V_CVT_F64_U32(&iFmt->iFmt_VOP3A);
6239  } // decode_OPU_VOP3__V_CVT_F64_U32
6240 
6241  GPUStaticInst*
6243  {
6244  return new Inst_VOP3__V_TRUNC_F64(&iFmt->iFmt_VOP3A);
6245  } // decode_OPU_VOP3__V_TRUNC_F64
6246 
6247  GPUStaticInst*
6249  {
6250  return new Inst_VOP3__V_CEIL_F64(&iFmt->iFmt_VOP3A);
6251  } // decode_OPU_VOP3__V_CEIL_F64
6252 
6253  GPUStaticInst*
6255  {
6256  return new Inst_VOP3__V_RNDNE_F64(&iFmt->iFmt_VOP3A);
6257  } // decode_OPU_VOP3__V_RNDNE_F64
6258 
6259  GPUStaticInst*
6261  {
6262  return new Inst_VOP3__V_FLOOR_F64(&iFmt->iFmt_VOP3A);
6263  } // decode_OPU_VOP3__V_FLOOR_F64
6264 
6265  GPUStaticInst*
6267  {
6268  return new Inst_VOP3__V_FRACT_F32(&iFmt->iFmt_VOP3A);
6269  } // decode_OPU_VOP3__V_FRACT_F32
6270 
6271  GPUStaticInst*
6273  {
6274  return new Inst_VOP3__V_TRUNC_F32(&iFmt->iFmt_VOP3A);
6275  } // decode_OPU_VOP3__V_TRUNC_F32
6276 
6277  GPUStaticInst*
6279  {
6280  return new Inst_VOP3__V_CEIL_F32(&iFmt->iFmt_VOP3A);
6281  } // decode_OPU_VOP3__V_CEIL_F32
6282 
6283  GPUStaticInst*
6285  {
6286  return new Inst_VOP3__V_RNDNE_F32(&iFmt->iFmt_VOP3A);
6287  } // decode_OPU_VOP3__V_RNDNE_F32
6288 
6289  GPUStaticInst*
6291  {
6292  return new Inst_VOP3__V_FLOOR_F32(&iFmt->iFmt_VOP3A);
6293  } // decode_OPU_VOP3__V_FLOOR_F32
6294 
6295  GPUStaticInst*
6297  {
6298  return new Inst_VOP3__V_EXP_F32(&iFmt->iFmt_VOP3A);
6299  } // decode_OPU_VOP3__V_EXP_F32
6300 
6301  GPUStaticInst*
6303  {
6304  return new Inst_VOP3__V_LOG_F32(&iFmt->iFmt_VOP3A);
6305  } // decode_OPU_VOP3__V_LOG_F32
6306 
6307  GPUStaticInst*
6309  {
6310  return new Inst_VOP3__V_RCP_F32(&iFmt->iFmt_VOP3A);
6311  } // decode_OPU_VOP3__V_RCP_F32
6312 
6313  GPUStaticInst*
6315  {
6316  return new Inst_VOP3__V_RCP_IFLAG_F32(&iFmt->iFmt_VOP3A);
6317  } // decode_OPU_VOP3__V_RCP_IFLAG_F32
6318 
6319  GPUStaticInst*
6321  {
6322  return new Inst_VOP3__V_RSQ_F32(&iFmt->iFmt_VOP3A);
6323  } // decode_OPU_VOP3__V_RSQ_F32
6324 
6325  GPUStaticInst*
6327  {
6328  return new Inst_VOP3__V_RCP_F64(&iFmt->iFmt_VOP3A);
6329  } // decode_OPU_VOP3__V_RCP_F64
6330 
6331  GPUStaticInst*
6333  {
6334  return new Inst_VOP3__V_RSQ_F64(&iFmt->iFmt_VOP3A);
6335  } // decode_OPU_VOP3__V_RSQ_F64
6336 
6337  GPUStaticInst*
6339  {
6340  return new Inst_VOP3__V_SQRT_F32(&iFmt->iFmt_VOP3A);
6341  } // decode_OPU_VOP3__V_SQRT_F32
6342 
6343  GPUStaticInst*
6345  {
6346  return new Inst_VOP3__V_SQRT_F64(&iFmt->iFmt_VOP3A);
6347  } // decode_OPU_VOP3__V_SQRT_F64
6348 
6349  GPUStaticInst*
6351  {
6352  return new Inst_VOP3__V_SIN_F32(&iFmt->iFmt_VOP3A);
6353  } // decode_OPU_VOP3__V_SIN_F32
6354 
6355  GPUStaticInst*
6357  {
6358  return new Inst_VOP3__V_COS_F32(&iFmt->iFmt_VOP3A);
6359  } // decode_OPU_VOP3__V_COS_F32
6360 
6361  GPUStaticInst*
6363  {
6364  return new Inst_VOP3__V_NOT_B32(&iFmt->iFmt_VOP3A);
6365  } // decode_OPU_VOP3__V_NOT_B32
6366 
6367  GPUStaticInst*
6369  {
6370  return new Inst_VOP3__V_BFREV_B32(&iFmt->iFmt_VOP3A);
6371  } // decode_OPU_VOP3__V_BFREV_B32
6372 
6373  GPUStaticInst*
6375  {
6376  return new Inst_VOP3__V_FFBH_U32(&iFmt->iFmt_VOP3A);
6377  } // decode_OPU_VOP3__V_FFBH_U32
6378 
6379  GPUStaticInst*
6381  {
6382  return new Inst_VOP3__V_FFBL_B32(&iFmt->iFmt_VOP3A);
6383  } // decode_OPU_VOP3__V_FFBL_B32
6384 
6385  GPUStaticInst*
6387  {
6388  return new Inst_VOP3__V_FFBH_I32(&iFmt->iFmt_VOP3A);
6389  } // decode_OPU_VOP3__V_FFBH_I32
6390 
6391  GPUStaticInst*
6393  {
6394  return new Inst_VOP3__V_FREXP_EXP_I32_F64(&iFmt->iFmt_VOP3A);
6395  } // decode_OPU_VOP3__V_FREXP_EXP_I32_F64
6396 
6397  GPUStaticInst*
6399  {
6400  return new Inst_VOP3__V_FREXP_MANT_F64(&iFmt->iFmt_VOP3A);
6401  } // decode_OPU_VOP3__V_FREXP_MANT_F64
6402 
6403  GPUStaticInst*
6405  {
6406  return new Inst_VOP3__V_FRACT_F64(&iFmt->iFmt_VOP3A);
6407  } // decode_OPU_VOP3__V_FRACT_F64
6408 
6409  GPUStaticInst*
6411  {
6412  return new Inst_VOP3__V_FREXP_EXP_I32_F32(&iFmt->iFmt_VOP3A);
6413  } // decode_OPU_VOP3__V_FREXP_EXP_I32_F32
6414 
6415  GPUStaticInst*
6417  {
6418  return new Inst_VOP3__V_FREXP_MANT_F32(&iFmt->iFmt_VOP3A);
6419  } // decode_OPU_VOP3__V_FREXP_MANT_F32
6420 
6421  GPUStaticInst*
6423  {
6424  return new Inst_VOP3__V_CLREXCP(&iFmt->iFmt_VOP3A);
6425  } // decode_OPU_VOP3__V_CLREXCP
6426 
6427  GPUStaticInst*
6429  {
6430  return new Inst_VOP3__V_CVT_F16_U16(&iFmt->iFmt_VOP3A);
6431  } // decode_OPU_VOP3__V_CVT_F16_U16
6432 
6433  GPUStaticInst*
6435  {
6436  return new Inst_VOP3__V_CVT_F16_I16(&iFmt->iFmt_VOP3A);
6437  } // decode_OPU_VOP3__V_CVT_F16_I16
6438 
6439  GPUStaticInst*
6441  {
6442  return new Inst_VOP3__V_CVT_U16_F16(&iFmt->iFmt_VOP3A);
6443  } // decode_OPU_VOP3__V_CVT_U16_F16
6444 
6445  GPUStaticInst*
6447  {
6448  return new Inst_VOP3__V_CVT_I16_F16(&iFmt->iFmt_VOP3A);
6449  } // decode_OPU_VOP3__V_CVT_I16_F16
6450 
6451  GPUStaticInst*
6453  {
6454  return new Inst_VOP3__V_RCP_F16(&iFmt->iFmt_VOP3A);
6455  } // decode_OPU_VOP3__V_RCP_F16
6456 
6457  GPUStaticInst*
6459  {
6460  return new Inst_VOP3__V_SQRT_F16(&iFmt->iFmt_VOP3A);
6461  } // decode_OPU_VOP3__V_SQRT_F16
6462 
6463  GPUStaticInst*
6465  {
6466  return new Inst_VOP3__V_RSQ_F16(&iFmt->iFmt_VOP3A);
6467  } // decode_OPU_VOP3__V_RSQ_F16
6468 
6469  GPUStaticInst*
6471  {
6472  return new Inst_VOP3__V_LOG_F16(&iFmt->iFmt_VOP3A);
6473  } // decode_OPU_VOP3__V_LOG_F16
6474 
6475  GPUStaticInst*
6477  {
6478  return new Inst_VOP3__V_EXP_F16(&iFmt->iFmt_VOP3A);
6479  } // decode_OPU_VOP3__V_EXP_F16
6480 
6481  GPUStaticInst*
6483  {
6484  return new Inst_VOP3__V_FREXP_MANT_F16(&iFmt->iFmt_VOP3A);
6485  } // decode_OPU_VOP3__V_FREXP_MANT_F16
6486 
6487  GPUStaticInst*
6489  {
6490  return new Inst_VOP3__V_FREXP_EXP_I16_F16(&iFmt->iFmt_VOP3A);
6491  } // decode_OPU_VOP3__V_FREXP_EXP_I16_F16
6492 
6493  GPUStaticInst*
6495  {
6496  return new Inst_VOP3__V_FLOOR_F16(&iFmt->iFmt_VOP3A);
6497  } // decode_OPU_VOP3__V_FLOOR_F16
6498 
6499  GPUStaticInst*
6501  {
6502  return new Inst_VOP3__V_CEIL_F16(&iFmt->iFmt_VOP3A);
6503  } // decode_OPU_VOP3__V_CEIL_F16
6504 
6505  GPUStaticInst*
6507  {
6508  return new Inst_VOP3__V_TRUNC_F16(&iFmt->iFmt_VOP3A);
6509  } // decode_OPU_VOP3__V_TRUNC_F16
6510 
6511  GPUStaticInst*
6513  {
6514  return new Inst_VOP3__V_RNDNE_F16(&iFmt->iFmt_VOP3A);
6515  } // decode_OPU_VOP3__V_RNDNE_F16
6516 
6517  GPUStaticInst*
6519  {
6520  return new Inst_VOP3__V_FRACT_F16(&iFmt->iFmt_VOP3A);
6521  } // decode_OPU_VOP3__V_FRACT_F16
6522 
6523  GPUStaticInst*
6525  {
6526  return new Inst_VOP3__V_SIN_F16(&iFmt->iFmt_VOP3A);
6527  } // decode_OPU_VOP3__V_SIN_F16
6528 
6529  GPUStaticInst*
6531  {
6532  return new Inst_VOP3__V_COS_F16(&iFmt->iFmt_VOP3A);
6533  } // decode_OPU_VOP3__V_COS_F16
6534 
6535  GPUStaticInst*
6537  {
6538  return new Inst_VOP3__V_EXP_LEGACY_F32(&iFmt->iFmt_VOP3A);
6539  } // decode_OPU_VOP3__V_EXP_LEGACY_F32
6540 
6541  GPUStaticInst*
6543  {
6544  return new Inst_VOP3__V_LOG_LEGACY_F32(&iFmt->iFmt_VOP3A);
6545  } // decode_OPU_VOP3__V_LOG_LEGACY_F32
6546 
6547  GPUStaticInst*
6549  {
6550  return new Inst_VOP3__V_MAD_LEGACY_F32(&iFmt->iFmt_VOP3A);
6551  } // decode_OPU_VOP3__V_MAD_LEGACY_F32
6552 
6553  GPUStaticInst*
6555  {
6556  return new Inst_VOP3__V_MAD_F32(&iFmt->iFmt_VOP3A);
6557  } // decode_OPU_VOP3__V_MAD_F32
6558 
6559  GPUStaticInst*
6561  {
6562  return new Inst_VOP3__V_MAD_I32_I24(&iFmt->iFmt_VOP3A);
6563  } // decode_OPU_VOP3__V_MAD_I32_I24
6564 
6565  GPUStaticInst*
6567  {
6568  return new Inst_VOP3__V_MAD_U32_U24(&iFmt->iFmt_VOP3A);
6569  } // decode_OPU_VOP3__V_MAD_U32_U24
6570 
6571  GPUStaticInst*
6573  {
6574  return new Inst_VOP3__V_CUBEID_F32(&iFmt->iFmt_VOP3A);
6575  } // decode_OPU_VOP3__V_CUBEID_F32
6576 
6577  GPUStaticInst*
6579  {
6580  return new Inst_VOP3__V_CUBESC_F32(&iFmt->iFmt_VOP3A);
6581  } // decode_OPU_VOP3__V_CUBESC_F32
6582 
6583  GPUStaticInst*
6585  {
6586  return new Inst_VOP3__V_CUBETC_F32(&iFmt->iFmt_VOP3A);
6587  } // decode_OPU_VOP3__V_CUBETC_F32
6588 
6589  GPUStaticInst*
6591  {
6592  return new Inst_VOP3__V_CUBEMA_F32(&iFmt->iFmt_VOP3A);
6593  } // decode_OPU_VOP3__V_CUBEMA_F32
6594 
6595  GPUStaticInst*
6597  {
6598  return new Inst_VOP3__V_BFE_U32(&iFmt->iFmt_VOP3A);
6599  } // decode_OPU_VOP3__V_BFE_U32
6600 
6601  GPUStaticInst*
6603  {
6604  return new Inst_VOP3__V_BFE_I32(&iFmt->iFmt_VOP3A);
6605  } // decode_OPU_VOP3__V_BFE_I32
6606 
6607  GPUStaticInst*
6609  {
6610  return new Inst_VOP3__V_BFI_B32(&iFmt->iFmt_VOP3A);
6611  } // decode_OPU_VOP3__V_BFI_B32
6612 
6613  GPUStaticInst*
6615  {
6616  return new Inst_VOP3__V_FMA_F32(&iFmt->iFmt_VOP3A);
6617  } // decode_OPU_VOP3__V_FMA_F32
6618 
6619  GPUStaticInst*
6621  {
6622  return new Inst_VOP3__V_FMA_F64(&iFmt->iFmt_VOP3A);
6623  } // decode_OPU_VOP3__V_FMA_F64
6624 
6625  GPUStaticInst*
6627  {
6628  return new Inst_VOP3__V_LERP_U8(&iFmt->iFmt_VOP3A);
6629  } // decode_OPU_VOP3__V_LERP_U8
6630 
6631  GPUStaticInst*
6633  {
6634  return new Inst_VOP3__V_ALIGNBIT_B32(&iFmt->iFmt_VOP3A);
6635  } // decode_OPU_VOP3__V_ALIGNBIT_B32
6636 
6637  GPUStaticInst*
6639  {
6640  return new Inst_VOP3__V_ALIGNBYTE_B32(&iFmt->iFmt_VOP3A);
6641  } // decode_OPU_VOP3__V_ALIGNBYTE_B32
6642 
6643  GPUStaticInst*
6645  {
6646  return new Inst_VOP3__V_MIN3_F32(&iFmt->iFmt_VOP3A);
6647  } // decode_OPU_VOP3__V_MIN3_F32
6648 
6649  GPUStaticInst*
6651  {
6652  return new Inst_VOP3__V_MIN3_I32(&iFmt->iFmt_VOP3A);
6653  } // decode_OPU_VOP3__V_MIN3_I32
6654 
6655  GPUStaticInst*
6657  {
6658  return new Inst_VOP3__V_MIN3_U32(&iFmt->iFmt_VOP3A);
6659  } // decode_OPU_VOP3__V_MIN3_U32
6660 
6661  GPUStaticInst*
6663  {
6664  return new Inst_VOP3__V_MAX3_F32(&iFmt->iFmt_VOP3A);
6665  } // decode_OPU_VOP3__V_MAX3_F32
6666 
6667  GPUStaticInst*
6669  {
6670  return new Inst_VOP3__V_MAX3_I32(&iFmt->iFmt_VOP3A);
6671  } // decode_OPU_VOP3__V_MAX3_I32
6672 
6673  GPUStaticInst*
6675  {
6676  return new Inst_VOP3__V_MAX3_U32(&iFmt->iFmt_VOP3A);
6677  } // decode_OPU_VOP3__V_MAX3_U32
6678 
6679  GPUStaticInst*
6681  {
6682  return new Inst_VOP3__V_MED3_F32(&iFmt->iFmt_VOP3A);
6683  } // decode_OPU_VOP3__V_MED3_F32
6684 
6685  GPUStaticInst*
6687  {
6688  return new Inst_VOP3__V_MED3_I32(&iFmt->iFmt_VOP3A);
6689  } // decode_OPU_VOP3__V_MED3_I32
6690 
6691  GPUStaticInst*
6693  {
6694  return new Inst_VOP3__V_MED3_U32(&iFmt->iFmt_VOP3A);
6695  } // decode_OPU_VOP3__V_MED3_U32
6696 
6697  GPUStaticInst*
6699  {
6700  return new Inst_VOP3__V_SAD_U8(&iFmt->iFmt_VOP3A);
6701  } // decode_OPU_VOP3__V_SAD_U8
6702 
6703  GPUStaticInst*
6705  {
6706  return new Inst_VOP3__V_SAD_HI_U8(&iFmt->iFmt_VOP3A);
6707  } // decode_OPU_VOP3__V_SAD_HI_U8
6708 
6709  GPUStaticInst*
6711  {
6712  return new Inst_VOP3__V_SAD_U16(&iFmt->iFmt_VOP3A);
6713  } // decode_OPU_VOP3__V_SAD_U16
6714 
6715  GPUStaticInst*
6717  {
6718  return new Inst_VOP3__V_SAD_U32(&iFmt->iFmt_VOP3A);
6719  } // decode_OPU_VOP3__V_SAD_U32
6720 
6721  GPUStaticInst*
6723  {
6724  return new Inst_VOP3__V_CVT_PK_U8_F32(&iFmt->iFmt_VOP3A);
6725  } // decode_OPU_VOP3__V_CVT_PK_U8_F32
6726 
6727  GPUStaticInst*
6729  {
6730  return new Inst_VOP3__V_DIV_FIXUP_F32(&iFmt->iFmt_VOP3A);
6731  } // decode_OPU_VOP3__V_DIV_FIXUP_F32
6732 
6733  GPUStaticInst*
6735  {
6736  return new Inst_VOP3__V_DIV_FIXUP_F64(&iFmt->iFmt_VOP3A);
6737  } // decode_OPU_VOP3__V_DIV_FIXUP_F64
6738 
6739  GPUStaticInst*
6741  {
6742  return new Inst_VOP3__V_DIV_SCALE_F32(&iFmt->iFmt_VOP3B);
6743  } // decode_OPU_VOP3__V_DIV_SCALE_F32
6744 
6745  GPUStaticInst*
6747  {
6748  return new Inst_VOP3__V_DIV_SCALE_F64(&iFmt->iFmt_VOP3B);
6749  } // decode_OPU_VOP3__V_DIV_SCALE_F64
6750 
6751  GPUStaticInst*
6753  {
6754  return new Inst_VOP3__V_DIV_FMAS_F32(&iFmt->iFmt_VOP3A);
6755  } // decode_OPU_VOP3__V_DIV_FMAS_F32
6756 
6757  GPUStaticInst*
6759  {
6760  return new Inst_VOP3__V_DIV_FMAS_F64(&iFmt->iFmt_VOP3A);
6761  } // decode_OPU_VOP3__V_DIV_FMAS_F64
6762 
6763  GPUStaticInst*
6765  {
6766  return new Inst_VOP3__V_MSAD_U8(&iFmt->iFmt_VOP3A);
6767  } // decode_OPU_VOP3__V_MSAD_U8
6768 
6769  GPUStaticInst*
6771  {
6772  return new Inst_VOP3__V_QSAD_PK_U16_U8(&iFmt->iFmt_VOP3A);
6773  } // decode_OPU_VOP3__V_QSAD_PK_U16_U8
6774 
6775  GPUStaticInst*
6777  {
6778  return new Inst_VOP3__V_MQSAD_PK_U16_U8(&iFmt->iFmt_VOP3A);
6779  } // decode_OPU_VOP3__V_MQSAD_PK_U16_U8
6780 
6781  GPUStaticInst*
6783  {
6784  return new Inst_VOP3__V_MQSAD_U32_U8(&iFmt->iFmt_VOP3A);
6785  } // decode_OPU_VOP3__V_MQSAD_U32_U8
6786 
6787  GPUStaticInst*
6789  {
6790  return new Inst_VOP3__V_MAD_U64_U32(&iFmt->iFmt_VOP3B);
6791  } // decode_OPU_VOP3__V_MAD_U64_U32
6792 
6793  GPUStaticInst*
6795  {
6796  return new Inst_VOP3__V_MAD_I64_I32(&iFmt->iFmt_VOP3B);
6797  } // decode_OPU_VOP3__V_MAD_I64_I32
6798 
6799  GPUStaticInst*
6801  {
6802  return new Inst_VOP3__V_MAD_F16(&iFmt->iFmt_VOP3A);
6803  } // decode_OPU_VOP3__V_MAD_LEGACY_F16
6804 
6805  GPUStaticInst*
6807  {
6808  return new Inst_VOP3__V_MAD_U16(&iFmt->iFmt_VOP3A);
6809  } // decode_OPU_VOP3__V_MAD_LEGACY_U16
6810 
6811  GPUStaticInst*
6813  {
6814  return new Inst_VOP3__V_MAD_I16(&iFmt->iFmt_VOP3A);
6815  } // decode_OPU_VOP3__V_MAD_LEGACY_I16
6816 
6817  GPUStaticInst*
6819  {
6820  return new Inst_VOP3__V_PERM_B32(&iFmt->iFmt_VOP3A);
6821  } // decode_OPU_VOP3__V_PERM_B32
6822 
6823  GPUStaticInst*
6825  {
6826  return new Inst_VOP3__V_FMA_F16(&iFmt->iFmt_VOP3A);
6827  } // decode_OPU_VOP3__V_FMA_LEGACY_F16
6828 
6829  GPUStaticInst*
6831  {
6832  return new Inst_VOP3__V_DIV_FIXUP_F16(&iFmt->iFmt_VOP3A);
6833  } // decode_OPU_VOP3__V_DIV_FIXUP_LEGACY_F16
6834 
6835  GPUStaticInst*
6837  {
6838  return new Inst_VOP3__V_CVT_PKACCUM_U8_F32(&iFmt->iFmt_VOP3A);
6839  } // decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32
6840 
6841  GPUStaticInst*
6843  {
6844  fatal("Trying to decode instruction without a class\n");
6845  return nullptr;
6846  }
6847 
6848  GPUStaticInst*
6850  {
6851  fatal("Trying to decode instruction without a class\n");
6852  return nullptr;
6853  }
6854 
6855  GPUStaticInst*
6857  {
6858  fatal("Trying to decode instruction without a class\n");
6859  return nullptr;
6860  }
6861 
6862  GPUStaticInst*
6864  {
6865  fatal("Trying to decode instruction without a class\n");
6866  return nullptr;
6867  }
6868 
6869  GPUStaticInst*
6871  {
6872  fatal("Trying to decode instruction without a class\n");
6873  return nullptr;
6874  }
6875 
6876  GPUStaticInst*
6878  {
6879  fatal("Trying to decode instruction without a class\n");
6880  return nullptr;
6881  }
6882 
6883  GPUStaticInst*
6885  {
6886  fatal("Trying to decode instruction without a class\n");
6887  return nullptr;
6888  }
6889 
6890  GPUStaticInst*
6892  {
6893  fatal("Trying to decode instruction without a class\n");
6894  return nullptr;
6895  }
6896 
6897  GPUStaticInst*
6899  {
6900  fatal("Trying to decode instruction without a class\n");
6901  return nullptr;
6902  }
6903 
6904  GPUStaticInst*
6906  {
6907  fatal("Trying to decode instruction without a class\n");
6908  return nullptr;
6909  }
6910 
6911  GPUStaticInst*
6913  {
6914  fatal("Trying to decode instruction without a class\n");
6915  return nullptr;
6916  }
6917 
6918  GPUStaticInst*
6920  {
6921  fatal("Trying to decode instruction without a class\n");
6922  return nullptr;
6923  }
6924 
6925  GPUStaticInst*
6927  {
6928  return new Inst_VOP3__V_LSHL_ADD_U32(&iFmt->iFmt_VOP3A);
6929  }
6930 
6931  GPUStaticInst*
6933  {
6934  return new Inst_VOP3__V_ADD_LSHL_U32(&iFmt->iFmt_VOP3A);
6935  }
6936 
6937  GPUStaticInst*
6939  {
6940  return new Inst_VOP3__V_ADD3_U32(&iFmt->iFmt_VOP3A);
6941  }
6942 
6943  GPUStaticInst*
6945  {
6946  return new Inst_VOP3__V_LSHL_OR_B32(&iFmt->iFmt_VOP3A);
6947  }
6948 
6949  GPUStaticInst*
6951  {
6952  return new Inst_VOP3__V_AND_OR_B32(&iFmt->iFmt_VOP3A);
6953  }
6954 
6955  GPUStaticInst*
6957  {
6958  return new Inst_VOP3__V_OR_B32(&iFmt->iFmt_VOP3A);
6959  }
6960 
6961  GPUStaticInst*
6963  {
6964  return new Inst_VOP3__V_MAD_F16(&iFmt->iFmt_VOP3A);
6965  }
6966 
6967  GPUStaticInst*
6969  {
6970  return new Inst_VOP3__V_MAD_U16(&iFmt->iFmt_VOP3A);
6971  }
6972 
6973  GPUStaticInst*
6975  {
6976  return new Inst_VOP3__V_MAD_I16(&iFmt->iFmt_VOP3A);
6977  }
6978 
6979  GPUStaticInst*
6981  {
6982  return new Inst_VOP3__V_FMA_F16(&iFmt->iFmt_VOP3A);
6983  }
6984 
6985  GPUStaticInst*
6987  {
6988  return new Inst_VOP3__V_DIV_FIXUP_F16(&iFmt->iFmt_VOP3A);
6989  }
6990 
6991  GPUStaticInst*
6993  {
6994  return new Inst_VOP3__V_INTERP_P1_F32(&iFmt->iFmt_VOP3A);
6995  } // decode_OPU_VOP3__V_INTERP_P1_F32
6996 
6997  GPUStaticInst*
6999  {
7000  return new Inst_VOP3__V_INTERP_P2_F32(&iFmt->iFmt_VOP3A);
7001  } // decode_OPU_VOP3__V_INTERP_P2_F32
7002 
7003  GPUStaticInst*
7005  {
7006  return new Inst_VOP3__V_INTERP_MOV_F32(&iFmt->iFmt_VOP3A);
7007  } // decode_OPU_VOP3__V_INTERP_MOV_F32
7008 
7009  GPUStaticInst*
7011  {
7012  return new Inst_VOP3__V_INTERP_P1LL_F16(&iFmt->iFmt_VOP3A);
7013  } // decode_OPU_VOP3__V_INTERP_P1LL_F16
7014 
7015  GPUStaticInst*
7017  {
7018  return new Inst_VOP3__V_INTERP_P1LV_F16(&iFmt->iFmt_VOP3A);
7019  } // decode_OPU_VOP3__V_INTERP_P1LV_F16
7020 
7021  GPUStaticInst*
7023  {
7024  fatal("Trying to decode instruction without a class\n");
7025  return nullptr;
7026  }
7027 
7028  GPUStaticInst*
7030  {
7031  return new Inst_VOP3__V_INTERP_P2_F16(&iFmt->iFmt_VOP3A);
7032  } // decode_OPU_VOP3__V_INTERP_P2_F16
7033 
7034  GPUStaticInst*
7036  {
7037  return new Inst_VOP3__V_ADD_F64(&iFmt->iFmt_VOP3A);
7038  } // decode_OPU_VOP3__V_ADD_F64
7039 
7040  GPUStaticInst*
7042  {
7043  return new Inst_VOP3__V_MUL_F64(&iFmt->iFmt_VOP3A);
7044  } // decode_OPU_VOP3__V_MUL_F64
7045 
7046  GPUStaticInst*
7048  {
7049  return new Inst_VOP3__V_MIN_F64(&iFmt->iFmt_VOP3A);
7050  } // decode_OPU_VOP3__V_MIN_F64
7051 
7052  GPUStaticInst*
7054  {
7055  return new Inst_VOP3__V_MAX_F64(&iFmt->iFmt_VOP3A);
7056  } // decode_OPU_VOP3__V_MAX_F64
7057 
7058  GPUStaticInst*
7060  {
7061  return new Inst_VOP3__V_LDEXP_F64(&iFmt->iFmt_VOP3A);
7062  } // decode_OPU_VOP3__V_LDEXP_F64
7063 
7064  GPUStaticInst*
7066  {
7067  return new Inst_VOP3__V_MUL_LO_U32(&iFmt->iFmt_VOP3A);
7068  } // decode_OPU_VOP3__V_MUL_LO_U32
7069 
7070  GPUStaticInst*
7072  {
7073  return new Inst_VOP3__V_MUL_HI_U32(&iFmt->iFmt_VOP3A);
7074  } // decode_OPU_VOP3__V_MUL_HI_U32
7075 
7076  GPUStaticInst*
7078  {
7079  return new Inst_VOP3__V_MUL_HI_I32(&iFmt->iFmt_VOP3A);
7080  } // decode_OPU_VOP3__V_MUL_HI_I32
7081 
7082  GPUStaticInst*
7084  {
7085  return new Inst_VOP3__V_LDEXP_F32(&iFmt->iFmt_VOP3A);
7086  } // decode_OPU_VOP3__V_LDEXP_F32
7087 
7088  GPUStaticInst*
7090  {
7091  return new Inst_VOP3__V_READLANE_B32(&iFmt->iFmt_VOP3A);
7092  } // decode_OPU_VOP3__V_READLANE_B32
7093 
7094  GPUStaticInst*
7096  {
7097  return new Inst_VOP3__V_WRITELANE_B32(&iFmt->iFmt_VOP3A);
7098  } // decode_OPU_VOP3__V_WRITELANE_B32
7099 
7100  GPUStaticInst*
7102  {
7103  return new Inst_VOP3__V_BCNT_U32_B32(&iFmt->iFmt_VOP3A);
7104  } // decode_OPU_VOP3__V_BCNT_U32_B32
7105 
7106  GPUStaticInst*
7108  {
7109  return new Inst_VOP3__V_MBCNT_LO_U32_B32(&iFmt->iFmt_VOP3A);
7110  } // decode_OPU_VOP3__V_MBCNT_LO_U32_B32
7111 
7112  GPUStaticInst*
7114  {
7115  return new Inst_VOP3__V_MBCNT_HI_U32_B32(&iFmt->iFmt_VOP3A);
7116  } // decode_OPU_VOP3__V_MBCNT_HI_U32_B32
7117 
7118  GPUStaticInst*
7120  {
7121  return new Inst_VOP3__V_LSHLREV_B64(&iFmt->iFmt_VOP3A);
7122  } // decode_OPU_VOP3__V_LSHLREV_B64
7123 
7124  GPUStaticInst*
7126  {
7127  return new Inst_VOP3__V_LSHRREV_B64(&iFmt->iFmt_VOP3A);
7128  } // decode_OPU_VOP3__V_LSHRREV_B64
7129 
7130  GPUStaticInst*
7132  {
7133  return new Inst_VOP3__V_ASHRREV_I64(&iFmt->iFmt_VOP3A);
7134  } // decode_OPU_VOP3__V_ASHRREV_I64
7135 
7136  GPUStaticInst*
7138  {
7139  return new Inst_VOP3__V_TRIG_PREOP_F64(&iFmt->iFmt_VOP3A);
7140  } // decode_OPU_VOP3__V_TRIG_PREOP_F64
7141 
7142  GPUStaticInst*
7144  {
7145  return new Inst_VOP3__V_BFM_B32(&iFmt->iFmt_VOP3A);
7146  } // decode_OPU_VOP3__V_BFM_B32
7147 
7148  GPUStaticInst*
7150  {
7151  return new Inst_VOP3__V_CVT_PKNORM_I16_F32(&iFmt->iFmt_VOP3A);
7152  } // decode_OPU_VOP3__V_CVT_PKNORM_I16_F32
7153 
7154  GPUStaticInst*
7156  {
7157  return new Inst_VOP3__V_CVT_PKNORM_U16_F32(&iFmt->iFmt_VOP3A);
7158  } // decode_OPU_VOP3__V_CVT_PKNORM_U16_F32
7159 
7160  GPUStaticInst*
7162  {
7163  return new Inst_VOP3__V_CVT_PKRTZ_F16_F32(&iFmt->iFmt_VOP3A);
7164  } // decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32
7165 
7166  GPUStaticInst*
7168  {
7169  return new Inst_VOP3__V_CVT_PK_U16_U32(&iFmt->iFmt_VOP3A);
7170  } // decode_OPU_VOP3__V_CVT_PK_U16_U32
7171 
7172  GPUStaticInst*
7174  {
7175  return new Inst_VOP3__V_CVT_PK_I16_I32(&iFmt->iFmt_VOP3A);
7176  } // decode_OPU_VOP3__V_CVT_PK_I16_I32
7177 
7178  GPUStaticInst*
7180  {
7181  fatal("Trying to decode instruction without a class\n");
7182  return nullptr;
7183  }
7184 
7185  GPUStaticInst*
7187  {
7188  fatal("Trying to decode instruction without a class\n");
7189  return nullptr;
7190  }
7191 
7192  GPUStaticInst*
7194  {
7195  fatal("Trying to decode instruction without a class\n");
7196  return nullptr;
7197  }
7198 
7199  GPUStaticInst*
7201  {
7202  fatal("Trying to decode instruction without a class\n");
7203  return nullptr;
7204  }
7205 
7206  GPUStaticInst*
7208  {
7209  fatal("Trying to decode instruction without a class\n");
7210  return nullptr;
7211  }
7212 
7213  GPUStaticInst*
7215  {
7216  fatal("Trying to decode instruction without a class\n");
7217  return nullptr;
7218  }
7219 
7220  GPUStaticInst*
7222  {
7223  fatal("Trying to decode instruction without a class\n");
7224  return nullptr;
7225  }
7226 
7227  GPUStaticInst*
7229  {
7230  return new Inst_DS__DS_ADD_U32(&iFmt->iFmt_DS);
7231  } // decode_OP_DS__DS_ADD_U32
7232 
7233  GPUStaticInst*
7235  {
7236  return new Inst_DS__DS_SUB_U32(&iFmt->iFmt_DS);
7237  } // decode_OP_DS__DS_SUB_U32
7238 
7239  GPUStaticInst*
7241  {
7242  return new Inst_DS__DS_RSUB_U32(&iFmt->iFmt_DS);
7243  } // decode_OP_DS__DS_RSUB_U32
7244 
7245  GPUStaticInst*
7247  {
7248  return new Inst_DS__DS_INC_U32(&iFmt->iFmt_DS);
7249  } // decode_OP_DS__DS_INC_U32
7250 
7251  GPUStaticInst*
7253  {
7254  return new Inst_DS__DS_DEC_U32(&iFmt->iFmt_DS);
7255  } // decode_OP_DS__DS_DEC_U32
7256 
7257  GPUStaticInst*
7259  {
7260  return new Inst_DS__DS_MIN_I32(&iFmt->iFmt_DS);
7261  } // decode_OP_DS__DS_MIN_I32
7262 
7263  GPUStaticInst*
7265  {
7266  return new Inst_DS__DS_MAX_I32(&iFmt->iFmt_DS);
7267  } // decode_OP_DS__DS_MAX_I32
7268 
7269  GPUStaticInst*
7271  {
7272  return new Inst_DS__DS_MIN_U32(&iFmt->iFmt_DS);
7273  } // decode_OP_DS__DS_MIN_U32
7274 
7275  GPUStaticInst*
7277  {
7278  return new Inst_DS__DS_MAX_U32(&iFmt->iFmt_DS);
7279  } // decode_OP_DS__DS_MAX_U32
7280 
7281  GPUStaticInst*
7283  {
7284  return new Inst_DS__DS_AND_B32(&iFmt->iFmt_DS);
7285  } // decode_OP_DS__DS_AND_B32
7286 
7287  GPUStaticInst*
7289  {
7290  return new Inst_DS__DS_OR_B32(&iFmt->iFmt_DS);
7291  } // decode_OP_DS__DS_OR_B32
7292 
7293  GPUStaticInst*
7295  {
7296  return new Inst_DS__DS_XOR_B32(&iFmt->iFmt_DS);
7297  } // decode_OP_DS__DS_XOR_B32
7298 
7299  GPUStaticInst*
7301  {
7302  return new Inst_DS__DS_MSKOR_B32(&iFmt->iFmt_DS);
7303  } // decode_OP_DS__DS_MSKOR_B32
7304 
7305  GPUStaticInst*
7307  {
7308  return new Inst_DS__DS_WRITE_B32(&iFmt->iFmt_DS);
7309  } // decode_OP_DS__DS_WRITE_B32
7310 
7311  GPUStaticInst*
7313  {
7314  return new Inst_DS__DS_WRITE2_B32(&iFmt->iFmt_DS);
7315  } // decode_OP_DS__DS_WRITE2_B32
7316 
7317  GPUStaticInst*
7319  {
7320  return new Inst_DS__DS_WRITE2ST64_B32(&iFmt->iFmt_DS);
7321  } // decode_OP_DS__DS_WRITE2ST64_B32
7322 
7323  GPUStaticInst*
7325  {
7326  return new Inst_DS__DS_CMPST_B32(&iFmt->iFmt_DS);
7327  } // decode_OP_DS__DS_CMPST_B32
7328 
7329  GPUStaticInst*
7331  {
7332  return new Inst_DS__DS_CMPST_F32(&iFmt->iFmt_DS);
7333  } // decode_OP_DS__DS_CMPST_F32
7334 
7335  GPUStaticInst*
7337  {
7338  return new Inst_DS__DS_MIN_F32(&iFmt->iFmt_DS);
7339  } // decode_OP_DS__DS_MIN_F32
7340 
7341  GPUStaticInst*
7343  {
7344  return new Inst_DS__DS_MAX_F32(&iFmt->iFmt_DS);
7345  } // decode_OP_DS__DS_MAX_F32
7346 
7347  GPUStaticInst*
7349  {
7350  return new Inst_DS__DS_NOP(&iFmt->iFmt_DS);
7351  } // decode_OP_DS__DS_NOP
7352 
7353  GPUStaticInst*
7355  {
7356  return new Inst_DS__DS_ADD_F32(&iFmt->iFmt_DS);
7357  } // decode_OP_DS__DS_ADD_F32
7358 
7359  GPUStaticInst*
7361  {
7362  fatal("Trying to decode instruction without a class\n");
7363  return nullptr;
7364  }
7365 
7366  GPUStaticInst*
7368  {
7369  return new Inst_DS__DS_WRITE_B8(&iFmt->iFmt_DS);
7370  } // decode_OP_DS__DS_WRITE_B8
7371 
7372  GPUStaticInst*
7374  {
7375  return new Inst_DS__DS_WRITE_B16(&iFmt->iFmt_DS);
7376  } // decode_OP_DS__DS_WRITE_B16
7377 
7378  GPUStaticInst*
7380  {
7381  return new Inst_DS__DS_ADD_RTN_U32(&iFmt->iFmt_DS);
7382  } // decode_OP_DS__DS_ADD_RTN_U32
7383 
7384  GPUStaticInst*
7386  {
7387  return new Inst_DS__DS_SUB_RTN_U32(&iFmt->iFmt_DS);
7388  } // decode_OP_DS__DS_SUB_RTN_U32
7389 
7390  GPUStaticInst*
7392  {
7393  return new Inst_DS__DS_RSUB_RTN_U32(&iFmt->iFmt_DS);
7394  } // decode_OP_DS__DS_RSUB_RTN_U32
7395 
7396  GPUStaticInst*
7398  {
7399  return new Inst_DS__DS_INC_RTN_U32(&iFmt->iFmt_DS);
7400  } // decode_OP_DS__DS_INC_RTN_U32
7401 
7402  GPUStaticInst*
7404  {
7405  return new Inst_DS__DS_DEC_RTN_U32(&iFmt->iFmt_DS);
7406  } // decode_OP_DS__DS_DEC_RTN_U32
7407 
7408  GPUStaticInst*
7410  {
7411  return new Inst_DS__DS_MIN_RTN_I32(&iFmt->iFmt_DS);
7412  } // decode_OP_DS__DS_MIN_RTN_I32
7413 
7414  GPUStaticInst*
7416  {
7417  return new Inst_DS__DS_MAX_RTN_I32(&iFmt->iFmt_DS);
7418  } // decode_OP_DS__DS_MAX_RTN_I32
7419 
7420  GPUStaticInst*
7422  {
7423  return new Inst_DS__DS_MIN_RTN_U32(&iFmt->iFmt_DS);
7424  } // decode_OP_DS__DS_MIN_RTN_U32
7425 
7426  GPUStaticInst*
7428  {
7429  return new Inst_DS__DS_MAX_RTN_U32(&iFmt->iFmt_DS);
7430  } // decode_OP_DS__DS_MAX_RTN_U32
7431 
7432  GPUStaticInst*
7434  {
7435  return new Inst_DS__DS_AND_RTN_B32(&iFmt->iFmt_DS);
7436  } // decode_OP_DS__DS_AND_RTN_B32
7437 
7438  GPUStaticInst*
7440  {
7441  return new Inst_DS__DS_OR_RTN_B32(&iFmt->iFmt_DS);
7442  } // decode_OP_DS__DS_OR_RTN_B32
7443 
7444  GPUStaticInst*
7446  {
7447  return new Inst_DS__DS_XOR_RTN_B32(&iFmt->iFmt_DS);
7448  } // decode_OP_DS__DS_XOR_RTN_B32
7449 
7450  GPUStaticInst*
7452  {
7453  return new Inst_DS__DS_MSKOR_RTN_B32(&iFmt->iFmt_DS);
7454  } // decode_OP_DS__DS_MSKOR_RTN_B32
7455 
7456  GPUStaticInst*
7458  {
7459  return new Inst_DS__DS_WRXCHG_RTN_B32(&iFmt->iFmt_DS);
7460  } // decode_OP_DS__DS_WRXCHG_RTN_B32
7461 
7462  GPUStaticInst*
7464  {
7465  return new Inst_DS__DS_WRXCHG2_RTN_B32(&iFmt->iFmt_DS);
7466  } // decode_OP_DS__DS_WRXCHG2_RTN_B32
7467 
7468  GPUStaticInst*
7470  {
7471  return new Inst_DS__DS_WRXCHG2ST64_RTN_B32(&iFmt->iFmt_DS);
7472  } // decode_OP_DS__DS_WRXCHG2ST64_RTN_B32
7473 
7474  GPUStaticInst*
7476  {
7477  return new Inst_DS__DS_CMPST_RTN_B32(&iFmt->iFmt_DS);
7478  } // decode_OP_DS__DS_CMPST_RTN_B32
7479 
7480  GPUStaticInst*
7482  {
7483  return new Inst_DS__DS_CMPST_RTN_F32(&iFmt->iFmt_DS);
7484  } // decode_OP_DS__DS_CMPST_RTN_F32
7485 
7486  GPUStaticInst*
7488  {
7489  return new Inst_DS__DS_MIN_RTN_F32(&iFmt->iFmt_DS);
7490  } // decode_OP_DS__DS_MIN_RTN_F32
7491 
7492  GPUStaticInst*
7494  {
7495  return new Inst_DS__DS_MAX_RTN_F32(&iFmt->iFmt_DS);
7496  } // decode_OP_DS__DS_MAX_RTN_F32
7497 
7498  GPUStaticInst*
7500  {
7501  return new Inst_DS__DS_WRAP_RTN_B32(&iFmt->iFmt_DS);
7502  } // decode_OP_DS__DS_WRAP_RTN_B32
7503 
7504  GPUStaticInst*
7506  {
7507  return new Inst_DS__DS_ADD_RTN_F32(&iFmt->iFmt_DS);
7508  } // decode_OP_DS__DS_ADD_RTN_F32
7509 
7510  GPUStaticInst*
7512  {
7513  return new Inst_DS__DS_READ_B32(&iFmt->iFmt_DS);
7514  } // decode_OP_DS__DS_READ_B32
7515 
7516  GPUStaticInst*
7518  {
7519  return new Inst_DS__DS_READ2_B32(&iFmt->iFmt_DS);
7520  } // decode_OP_DS__DS_READ2_B32
7521 
7522  GPUStaticInst*
7524  {
7525  return new Inst_DS__DS_READ2ST64_B32(&iFmt->iFmt_DS);
7526  } // decode_OP_DS__DS_READ2ST64_B32
7527 
7528  GPUStaticInst*
7530  {
7531  return new Inst_DS__DS_READ_I8(&iFmt->iFmt_DS);
7532  } // decode_OP_DS__DS_READ_I8
7533 
7534  GPUStaticInst*
7536  {
7537  return new Inst_DS__DS_READ_U8(&iFmt->iFmt_DS);
7538  } // decode_OP_DS__DS_READ_U8
7539 
7540  GPUStaticInst*
7542  {
7543  return new Inst_DS__DS_READ_I16(&iFmt->iFmt_DS);
7544  } // decode_OP_DS__DS_READ_I16
7545 
7546  GPUStaticInst*
7548  {
7549  return new Inst_DS__DS_READ_U16(&iFmt->iFmt_DS);
7550  } // decode_OP_DS__DS_READ_U16
7551 
7552  GPUStaticInst*
7554  {
7555  return new Inst_DS__DS_SWIZZLE_B32(&iFmt->iFmt_DS);
7556  } // decode_OP_DS__DS_SWIZZLE_B32
7557 
7558  GPUStaticInst*
7560  {
7561  return new Inst_DS__DS_PERMUTE_B32(&iFmt->iFmt_DS);
7562  } // decode_OP_DS__DS_PERMUTE_B32
7563 
7564  GPUStaticInst*
7566  {
7567  return new Inst_DS__DS_BPERMUTE_B32(&iFmt->iFmt_DS);
7568  } // decode_OP_DS__DS_BPERMUTE_B32
7569 
7570  GPUStaticInst*
7572  {
7573  return new Inst_DS__DS_ADD_U64(&iFmt->iFmt_DS);
7574  } // decode_OP_DS__DS_ADD_U64
7575 
7576  GPUStaticInst*
7578  {
7579  return new Inst_DS__DS_SUB_U64(&iFmt->iFmt_DS);
7580  } // decode_OP_DS__DS_SUB_U64
7581 
7582  GPUStaticInst*
7584  {
7585  return new Inst_DS__DS_RSUB_U64(&iFmt->iFmt_DS);
7586  } // decode_OP_DS__DS_RSUB_U64
7587 
7588  GPUStaticInst*
7590  {
7591  return new Inst_DS__DS_INC_U64(&iFmt->iFmt_DS);
7592  } // decode_OP_DS__DS_INC_U64
7593 
7594  GPUStaticInst*
7596  {
7597  return new Inst_DS__DS_DEC_U64(&iFmt->iFmt_DS);
7598  } // decode_OP_DS__DS_DEC_U64
7599 
7600  GPUStaticInst*
7602  {
7603  return new Inst_DS__DS_MIN_I64(&iFmt->iFmt_DS);
7604  } // decode_OP_DS__DS_MIN_I64
7605 
7606  GPUStaticInst*
7608  {
7609  return new Inst_DS__DS_MAX_I64(&iFmt->iFmt_DS);
7610  } // decode_OP_DS__DS_MAX_I64
7611 
7612  GPUStaticInst*
7614  {
7615  return new Inst_DS__DS_MIN_U64(&iFmt->iFmt_DS);
7616  } // decode_OP_DS__DS_MIN_U64
7617 
7618  GPUStaticInst*
7620  {
7621  return new Inst_DS__DS_MAX_U64(&iFmt->iFmt_DS);
7622  } // decode_OP_DS__DS_MAX_U64
7623 
7624  GPUStaticInst*
7626  {
7627  return new Inst_DS__DS_AND_B64(&iFmt->iFmt_DS);
7628  } // decode_OP_DS__DS_AND_B64
7629 
7630  GPUStaticInst*
7632  {
7633  return new Inst_DS__DS_OR_B64(&iFmt->iFmt_DS);
7634  } // decode_OP_DS__DS_OR_B64
7635 
7636  GPUStaticInst*
7638  {
7639  return new Inst_DS__DS_XOR_B64(&iFmt->iFmt_DS);
7640  } // decode_OP_DS__DS_XOR_B64
7641 
7642  GPUStaticInst*
7644  {
7645  return new Inst_DS__DS_MSKOR_B64(&iFmt->iFmt_DS);
7646  } // decode_OP_DS__DS_MSKOR_B64
7647 
7648  GPUStaticInst*
7650  {
7651  return new Inst_DS__DS_WRITE_B64(&iFmt->iFmt_DS);
7652  } // decode_OP_DS__DS_WRITE_B64
7653 
7654  GPUStaticInst*
7656  {
7657  return new Inst_DS__DS_WRITE2_B64(&iFmt->iFmt_DS);
7658  } // decode_OP_DS__DS_WRITE2_B64
7659 
7660  GPUStaticInst*
7662  {
7663  return new Inst_DS__DS_WRITE2ST64_B64(&iFmt->iFmt_DS);
7664  } // decode_OP_DS__DS_WRITE2ST64_B64
7665 
7666  GPUStaticInst*
7668  {
7669  return new Inst_DS__DS_CMPST_B64(&iFmt->iFmt_DS);
7670  } // decode_OP_DS__DS_CMPST_B64
7671 
7672  GPUStaticInst*
7674  {
7675  return new Inst_DS__DS_CMPST_F64(&iFmt->iFmt_DS);
7676  } // decode_OP_DS__DS_CMPST_F64
7677 
7678  GPUStaticInst*
7680  {
7681  return new Inst_DS__DS_MIN_F64(&iFmt->iFmt_DS);
7682  } // decode_OP_DS__DS_MIN_F64
7683 
7684  GPUStaticInst*
7686  {
7687  return new Inst_DS__DS_MAX_F64(&iFmt->iFmt_DS);
7688  } // decode_OP_DS__DS_MAX_F64
7689 
7690  GPUStaticInst*
7692  {
7693  fatal("Trying to decode instruction without a class\n");
7694  return nullptr;
7695  }
7696 
7697  GPUStaticInst*
7699  {
7700  fatal("Trying to decode instruction without a class\n");
7701  return nullptr;
7702  }
7703 
7704  GPUStaticInst*
7706  {
7707  fatal("Trying to decode instruction without a class\n");
7708  return nullptr;
7709  }
7710 
7711  GPUStaticInst*
7713  {
7714  fatal("Trying to decode instruction without a class\n");
7715  return nullptr;
7716  }
7717 
7718  GPUStaticInst*
7720  {
7721  fatal("Trying to decode instruction without a class\n");
7722  return nullptr;
7723  }
7724 
7725  GPUStaticInst*
7727  {
7728  fatal("Trying to decode instruction without a class\n");
7729  return nullptr;
7730  }
7731 
7732  GPUStaticInst*
7734  {
7735  fatal("Trying to decode instruction without a class\n");
7736  return nullptr;
7737  }
7738 
7739  GPUStaticInst*
7741  {
7742  fatal("Trying to decode instruction without a class\n");
7743  return nullptr;
7744  }
7745 
7746  GPUStaticInst*
7748  {
7749  return new Inst_DS__DS_ADD_RTN_U64(&iFmt->iFmt_DS);
7750  } // decode_OP_DS__DS_ADD_RTN_U64
7751 
7752  GPUStaticInst*
7754  {
7755  return new Inst_DS__DS_SUB_RTN_U64(&iFmt->iFmt_DS);
7756  } // decode_OP_DS__DS_SUB_RTN_U64
7757 
7758  GPUStaticInst*
7760  {
7761  return new Inst_DS__DS_RSUB_RTN_U64(&iFmt->iFmt_DS);
7762  } // decode_OP_DS__DS_RSUB_RTN_U64
7763 
7764  GPUStaticInst*
7766  {
7767  return new Inst_DS__DS_INC_RTN_U64(&iFmt->iFmt_DS);
7768  } // decode_OP_DS__DS_INC_RTN_U64
7769 
7770  GPUStaticInst*
7772  {
7773  return new Inst_DS__DS_DEC_RTN_U64(&iFmt->iFmt_DS);
7774  } // decode_OP_DS__DS_DEC_RTN_U64
7775 
7776  GPUStaticInst*
7778  {
7779  return new Inst_DS__DS_MIN_RTN_I64(&iFmt->iFmt_DS);
7780  } // decode_OP_DS__DS_MIN_RTN_I64
7781 
7782  GPUStaticInst*
7784  {
7785  return new Inst_DS__DS_MAX_RTN_I64(&iFmt->iFmt_DS);
7786  } // decode_OP_DS__DS_MAX_RTN_I64
7787 
7788  GPUStaticInst*
7790  {
7791  return new Inst_DS__DS_MIN_RTN_U64(&iFmt->iFmt_DS);
7792  } // decode_OP_DS__DS_MIN_RTN_U64
7793 
7794  GPUStaticInst*
7796  {
7797  return new Inst_DS__DS_MAX_RTN_U64(&iFmt->iFmt_DS);
7798  } // decode_OP_DS__DS_MAX_RTN_U64
7799 
7800  GPUStaticInst*
7802  {
7803  return new Inst_DS__DS_AND_RTN_B64(&iFmt->iFmt_DS);
7804  } // decode_OP_DS__DS_AND_RTN_B64
7805 
7806  GPUStaticInst*
7808  {
7809  return new Inst_DS__DS_OR_RTN_B64(&iFmt->iFmt_DS);
7810  } // decode_OP_DS__DS_OR_RTN_B64
7811 
7812  GPUStaticInst*
7814  {
7815  return new Inst_DS__DS_XOR_RTN_B64(&iFmt->iFmt_DS);
7816  } // decode_OP_DS__DS_XOR_RTN_B64
7817 
7818  GPUStaticInst*
7820  {
7821  return new Inst_DS__DS_MSKOR_RTN_B64(&iFmt->iFmt_DS);
7822  } // decode_OP_DS__DS_MSKOR_RTN_B64
7823 
7824  GPUStaticInst*
7826  {
7827  return new Inst_DS__DS_WRXCHG_RTN_B64(&iFmt->iFmt_DS);
7828  } // decode_OP_DS__DS_WRXCHG_RTN_B64
7829 
7830  GPUStaticInst*
7832  {
7833  return new Inst_DS__DS_WRXCHG2_RTN_B64(&iFmt->iFmt_DS);
7834  } // decode_OP_DS__DS_WRXCHG2_RTN_B64
7835 
7836  GPUStaticInst*
7838  {
7839  return new Inst_DS__DS_WRXCHG2ST64_RTN_B64(&iFmt->iFmt_DS);
7840  } // decode_OP_DS__DS_WRXCHG2ST64_RTN_B64
7841 
7842  GPUStaticInst*
7844  {
7845  return new Inst_DS__DS_CMPST_RTN_B64(&iFmt->iFmt_DS);
7846  } // decode_OP_DS__DS_CMPST_RTN_B64
7847 
7848  GPUStaticInst*
7850  {
7851  return new Inst_DS__DS_CMPST_RTN_F64(&iFmt->iFmt_DS);
7852  } // decode_OP_DS__DS_CMPST_RTN_F64
7853 
7854  GPUStaticInst*
7856  {
7857  return new Inst_DS__DS_MIN_RTN_F64(&iFmt->iFmt_DS);
7858  } // decode_OP_DS__DS_MIN_RTN_F64
7859 
7860  GPUStaticInst*
7862  {
7863  return new Inst_DS__DS_MAX_RTN_F64(&iFmt->iFmt_DS);
7864  } // decode_OP_DS__DS_MAX_RTN_F64
7865 
7866  GPUStaticInst*
7868  {
7869  return new Inst_DS__DS_READ_B64(&iFmt->iFmt_DS);
7870  } // decode_OP_DS__DS_READ_B64
7871 
7872  GPUStaticInst*
7874  {
7875  return new Inst_DS__DS_READ2_B64(&iFmt->iFmt_DS);
7876  } // decode_OP_DS__DS_READ2_B64
7877 
7878  GPUStaticInst*
7880  {
7881  return new Inst_DS__DS_READ2ST64_B64(&iFmt->iFmt_DS);
7882  } // decode_OP_DS__DS_READ2ST64_B64
7883 
7884  GPUStaticInst*
7886  {
7887  return new Inst_DS__DS_CONDXCHG32_RTN_B64(&iFmt->iFmt_DS);
7888  } // decode_OP_DS__DS_CONDXCHG32_RTN_B64
7889 
7890  GPUStaticInst*
7892  {
7893  return new Inst_DS__DS_ADD_SRC2_U32(&iFmt->iFmt_DS);
7894  } // decode_OP_DS__DS_ADD_SRC2_U32
7895 
7896  GPUStaticInst*
7898  {
7899  return new Inst_DS__DS_SUB_SRC2_U32(&iFmt->iFmt_DS);
7900  } // decode_OP_DS__DS_SUB_SRC2_U32
7901 
7902  GPUStaticInst*
7904  {
7905  return new Inst_DS__DS_RSUB_SRC2_U32(&iFmt->iFmt_DS);
7906  } // decode_OP_DS__DS_RSUB_SRC2_U32
7907 
7908  GPUStaticInst*
7910  {
7911  return new Inst_DS__DS_INC_SRC2_U32(&iFmt->iFmt_DS);
7912  } // decode_OP_DS__DS_INC_SRC2_U32
7913 
7914  GPUStaticInst*
7916  {
7917  return new Inst_DS__DS_DEC_SRC2_U32(&iFmt->iFmt_DS);
7918  } // decode_OP_DS__DS_DEC_SRC2_U32
7919 
7920  GPUStaticInst*
7922  {
7923  return new Inst_DS__DS_MIN_SRC2_I32(&iFmt->iFmt_DS);
7924  } // decode_OP_DS__DS_MIN_SRC2_I32
7925 
7926  GPUStaticInst*
7928  {
7929  return new Inst_DS__DS_MAX_SRC2_I32(&iFmt->iFmt_DS);
7930  } // decode_OP_DS__DS_MAX_SRC2_I32
7931 
7932  GPUStaticInst*
7934  {
7935  return new Inst_DS__DS_MIN_SRC2_U32(&iFmt->iFmt_DS);
7936  } // decode_OP_DS__DS_MIN_SRC2_U32
7937 
7938  GPUStaticInst*
7940  {
7941  return new Inst_DS__DS_MAX_SRC2_U32(&iFmt->iFmt_DS);
7942  } // decode_OP_DS__DS_MAX_SRC2_U32
7943 
7944  GPUStaticInst*
7946  {
7947  return new Inst_DS__DS_AND_SRC2_B32(&iFmt->iFmt_DS);
7948  } // decode_OP_DS__DS_AND_SRC2_B32
7949 
7950  GPUStaticInst*
7952  {
7953  return new Inst_DS__DS_OR_SRC2_B32(&iFmt->iFmt_DS);
7954  } // decode_OP_DS__DS_OR_SRC2_B32
7955 
7956  GPUStaticInst*
7958  {
7959  return new Inst_DS__DS_XOR_SRC2_B32(&iFmt->iFmt_DS);
7960  } // decode_OP_DS__DS_XOR_SRC2_B32
7961 
7962  GPUStaticInst*
7964  {
7965  return new Inst_DS__DS_WRITE_SRC2_B32(&iFmt->iFmt_DS);
7966  } // decode_OP_DS__DS_WRITE_SRC2_B32
7967 
7968  GPUStaticInst*
7970  {
7971  return new Inst_DS__DS_MIN_SRC2_F32(&iFmt->iFmt_DS);
7972  } // decode_OP_DS__DS_MIN_SRC2_F32
7973 
7974  GPUStaticInst*
7976  {
7977  return new Inst_DS__DS_MAX_SRC2_F32(&iFmt->iFmt_DS);
7978  } // decode_OP_DS__DS_MAX_SRC2_F32
7979 
7980  GPUStaticInst*
7982  {
7983  return new Inst_DS__DS_ADD_SRC2_F32(&iFmt->iFmt_DS);
7984  } // decode_OP_DS__DS_ADD_SRC2_F32
7985 
7986  GPUStaticInst*
7988  {
7989  return new Inst_DS__DS_GWS_SEMA_RELEASE_ALL(&iFmt->iFmt_DS);
7990  } // decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL
7991 
7992  GPUStaticInst*
7994  {
7995  return new Inst_DS__DS_GWS_INIT(&iFmt->iFmt_DS);
7996  } // decode_OP_DS__DS_GWS_INIT
7997 
7998  GPUStaticInst*
8000  {
8001  return new Inst_DS__DS_GWS_SEMA_V(&iFmt->iFmt_DS);
8002  } // decode_OP_DS__DS_GWS_SEMA_V
8003 
8004  GPUStaticInst*
8006  {
8007  return new Inst_DS__DS_GWS_SEMA_BR(&iFmt->iFmt_DS);
8008  } // decode_OP_DS__DS_GWS_SEMA_BR
8009 
8010  GPUStaticInst*
8012  {
8013  return new Inst_DS__DS_GWS_SEMA_P(&iFmt->iFmt_DS);
8014  } // decode_OP_DS__DS_GWS_SEMA_P
8015 
8016  GPUStaticInst*
8018  {
8019  return new Inst_DS__DS_GWS_BARRIER(&iFmt->iFmt_DS);
8020  } // decode_OP_DS__DS_GWS_BARRIER
8021 
8022  GPUStaticInst*
8024  {
8025  fatal("Trying to decode instruction without a class\n");
8026  return nullptr;
8027  }
8028 
8029  GPUStaticInst*
8031  {
8032  return new Inst_DS__DS_CONSUME(&iFmt->iFmt_DS);
8033  } // decode_OP_DS__DS_CONSUME
8034 
8035  GPUStaticInst*
8037  {
8038  return new Inst_DS__DS_APPEND(&iFmt->iFmt_DS);
8039  } // decode_OP_DS__DS_APPEND
8040 
8041  GPUStaticInst*
8043  {
8044  return new Inst_DS__DS_ORDERED_COUNT(&iFmt->iFmt_DS);
8045  } // decode_OP_DS__DS_ORDERED_COUNT
8046 
8047  GPUStaticInst*
8049  {
8050  return new Inst_DS__DS_ADD_SRC2_U64(&iFmt->iFmt_DS);
8051  } // decode_OP_DS__DS_ADD_SRC2_U64
8052 
8053  GPUStaticInst*
8055  {
8056  return new Inst_DS__DS_SUB_SRC2_U64(&iFmt->iFmt_DS);
8057  } // decode_OP_DS__DS_SUB_SRC2_U64
8058 
8059  GPUStaticInst*
8061  {
8062  return new Inst_DS__DS_RSUB_SRC2_U64(&iFmt->iFmt_DS);
8063  } // decode_OP_DS__DS_RSUB_SRC2_U64
8064 
8065  GPUStaticInst*
8067  {
8068  return new Inst_DS__DS_INC_SRC2_U64(&iFmt->iFmt_DS);
8069  } // decode_OP_DS__DS_INC_SRC2_U64
8070 
8071  GPUStaticInst*
8073  {
8074  return new Inst_DS__DS_DEC_SRC2_U64(&iFmt->iFmt_DS);
8075  } // decode_OP_DS__DS_DEC_SRC2_U64
8076 
8077  GPUStaticInst*
8079  {
8080  return new Inst_DS__DS_MIN_SRC2_I64(&iFmt->iFmt_DS);
8081  } // decode_OP_DS__DS_MIN_SRC2_I64
8082 
8083  GPUStaticInst*
8085  {
8086  return new Inst_DS__DS_MAX_SRC2_I64(&iFmt->iFmt_DS);
8087  } // decode_OP_DS__DS_MAX_SRC2_I64
8088 
8089  GPUStaticInst*
8091  {
8092  return new Inst_DS__DS_MIN_SRC2_U64(&iFmt->iFmt_DS);
8093  } // decode_OP_DS__DS_MIN_SRC2_U64
8094 
8095  GPUStaticInst*
8097  {
8098  return new Inst_DS__DS_MAX_SRC2_U64(&iFmt->iFmt_DS);
8099  } // decode_OP_DS__DS_MAX_SRC2_U64
8100 
8101  GPUStaticInst*
8103  {
8104  return new Inst_DS__DS_AND_SRC2_B64(&iFmt->iFmt_DS);
8105  } // decode_OP_DS__DS_AND_SRC2_B64
8106 
8107  GPUStaticInst*
8109  {
8110  return new Inst_DS__DS_OR_SRC2_B64(&iFmt->iFmt_DS);
8111  } // decode_OP_DS__DS_OR_SRC2_B64
8112 
8113  GPUStaticInst*
8115  {
8116  return new Inst_DS__DS_XOR_SRC2_B64(&iFmt->iFmt_DS);
8117  } // decode_OP_DS__DS_XOR_SRC2_B64
8118 
8119  GPUStaticInst*
8121  {
8122  return new Inst_DS__DS_WRITE_SRC2_B64(&iFmt->iFmt_DS);
8123  } // decode_OP_DS__DS_WRITE_SRC2_B64
8124 
8125  GPUStaticInst*
8127  {
8128  return new Inst_DS__DS_MIN_SRC2_F64(&iFmt->iFmt_DS);
8129  } // decode_OP_DS__DS_MIN_SRC2_F64
8130 
8131  GPUStaticInst*
8133  {
8134  return new Inst_DS__DS_MAX_SRC2_F64(&iFmt->iFmt_DS);
8135  } // decode_OP_DS__DS_MAX_SRC2_F64
8136 
8137  GPUStaticInst*
8139  {
8140  return new Inst_DS__DS_WRITE_B96(&iFmt->iFmt_DS);
8141  } // decode_OP_DS__DS_WRITE_B96
8142 
8143  GPUStaticInst*
8145  {
8146  return new Inst_DS__DS_WRITE_B128(&iFmt->iFmt_DS);
8147  } // decode_OP_DS__DS_WRITE_B128
8148 
8149  GPUStaticInst*
8151  {
8152  return new Inst_DS__DS_READ_B96(&iFmt->iFmt_DS);
8153  } // decode_OP_DS__DS_READ_B96
8154 
8155  GPUStaticInst*
8157  {
8158  return new Inst_DS__DS_READ_B128(&iFmt->iFmt_DS);
8159  } // decode_OP_DS__DS_READ_B128
8160 
8161  GPUStaticInst*
8163  {
8164  return new Inst_FLAT__FLAT_LOAD_UBYTE(&iFmt->iFmt_FLAT);
8165  } // decode_OP_FLAT__FLAT_LOAD_UBYTE
8166 
8167  GPUStaticInst*
8169  {
8170  return new Inst_FLAT__FLAT_LOAD_SBYTE(&iFmt->iFmt_FLAT);
8171  } // decode_OP_FLAT__FLAT_LOAD_SBYTE
8172 
8173  GPUStaticInst*
8175  {
8176  return new Inst_FLAT__FLAT_LOAD_USHORT(&iFmt->iFmt_FLAT);
8177  } // decode_OP_FLAT__FLAT_LOAD_USHORT
8178 
8179  GPUStaticInst*
8181  {
8182  return new Inst_FLAT__FLAT_LOAD_SSHORT(&iFmt->iFmt_FLAT);
8183  } // decode_OP_FLAT__FLAT_LOAD_SSHORT
8184 
8185  GPUStaticInst*
8187  {
8188  return new Inst_FLAT__FLAT_LOAD_DWORD(&iFmt->iFmt_FLAT);
8189  } // decode_OP_FLAT__FLAT_LOAD_DWORD
8190 
8191  GPUStaticInst*
8193  {
8194  return new Inst_FLAT__FLAT_LOAD_DWORDX2(&iFmt->iFmt_FLAT);
8195  } // decode_OP_FLAT__FLAT_LOAD_DWORDX2
8196 
8197  GPUStaticInst*
8199  {
8200  return new Inst_FLAT__FLAT_LOAD_DWORDX3(&iFmt->iFmt_FLAT);
8201  } // decode_OP_FLAT__FLAT_LOAD_DWORDX3
8202 
8203  GPUStaticInst*
8205  {
8206  return new Inst_FLAT__FLAT_LOAD_DWORDX4(&iFmt->iFmt_FLAT);
8207  } // decode_OP_FLAT__FLAT_LOAD_DWORDX4
8208 
8209  GPUStaticInst*
8211  {
8212  return new Inst_FLAT__FLAT_STORE_BYTE(&iFmt->iFmt_FLAT);
8213  } // decode_OP_FLAT__FLAT_STORE_BYTE
8214 
8215  GPUStaticInst*
8217  {
8218  fatal("Trying to decode instruction without a class\n");
8219  return nullptr;
8220  }
8221 
8222  GPUStaticInst*
8224  {
8225  return new Inst_FLAT__FLAT_STORE_SHORT(&iFmt->iFmt_FLAT);
8226  } // decode_OP_FLAT__FLAT_STORE_SHORT
8227 
8228  GPUStaticInst*
8230  {
8231  fatal("Trying to decode instruction without a class\n");
8232  return nullptr;
8233  }
8234 
8235  GPUStaticInst*
8237  {
8238  return new Inst_FLAT__FLAT_STORE_DWORD(&iFmt->iFmt_FLAT);
8239  } // decode_OP_FLAT__FLAT_STORE_DWORD
8240 
8241  GPUStaticInst*
8243  {
8244  return new Inst_FLAT__FLAT_STORE_DWORDX2(&iFmt->iFmt_FLAT);
8245  } // decode_OP_FLAT__FLAT_STORE_DWORDX2
8246 
8247  GPUStaticInst*
8249  {
8250  return new Inst_FLAT__FLAT_STORE_DWORDX3(&iFmt->iFmt_FLAT);
8251  } // decode_OP_FLAT__FLAT_STORE_DWORDX3
8252 
8253  GPUStaticInst*
8255  {
8256  return new Inst_FLAT__FLAT_STORE_DWORDX4(&iFmt->iFmt_FLAT);
8257  } // decode_OP_FLAT__FLAT_STORE_DWORDX4
8258 
8259  GPUStaticInst*
8261  {
8262  fatal("Trying to decode instruction without a class\n");
8263  return nullptr;
8264  }
8265 
8266  GPUStaticInst*
8268  {
8269  fatal("Trying to decode instruction without a class\n");
8270  return nullptr;
8271  }
8272 
8273  GPUStaticInst*
8275  {
8276  fatal("Trying to decode instruction without a class\n");
8277  return nullptr;
8278  }
8279 
8280  GPUStaticInst*
8282  {
8283  fatal("Trying to decode instruction without a class\n");
8284  return nullptr;
8285  }
8286 
8287  GPUStaticInst*
8289  {
8290  fatal("Trying to decode instruction without a class\n");
8291  return nullptr;
8292  }
8293 
8294  GPUStaticInst*
8296  {
8297  fatal("Trying to decode instruction without a class\n");
8298  return nullptr;
8299  }
8300 
8301  GPUStaticInst*
8303  {
8304  return new Inst_FLAT__FLAT_ATOMIC_SWAP(&iFmt->iFmt_FLAT);
8305  } // decode_OP_FLAT__FLAT_ATOMIC_SWAP
8306 
8307  GPUStaticInst*
8309  {
8310  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP(&iFmt->iFmt_FLAT);
8311  } // decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP
8312 
8313  GPUStaticInst*
8315  {
8316  return new Inst_FLAT__FLAT_ATOMIC_ADD(&iFmt->iFmt_FLAT);
8317  } // decode_OP_FLAT__FLAT_ATOMIC_ADD
8318 
8319  GPUStaticInst*
8321  {
8322  return new Inst_FLAT__FLAT_ATOMIC_SUB(&iFmt->iFmt_FLAT);
8323  } // decode_OP_FLAT__FLAT_ATOMIC_SUB
8324 
8325  GPUStaticInst*
8327  {
8328  return new Inst_FLAT__FLAT_ATOMIC_SMIN(&iFmt->iFmt_FLAT);
8329  } // decode_OP_FLAT__FLAT_ATOMIC_SMIN
8330 
8331  GPUStaticInst*
8333  {
8334  return new Inst_FLAT__FLAT_ATOMIC_UMIN(&iFmt->iFmt_FLAT);
8335  } // decode_OP_FLAT__FLAT_ATOMIC_UMIN
8336 
8337  GPUStaticInst*
8339  {
8340  return new Inst_FLAT__FLAT_ATOMIC_SMAX(&iFmt->iFmt_FLAT);
8341  } // decode_OP_FLAT__FLAT_ATOMIC_SMAX
8342 
8343  GPUStaticInst*
8345  {
8346  return new Inst_FLAT__FLAT_ATOMIC_UMAX(&iFmt->iFmt_FLAT);
8347  } // decode_OP_FLAT__FLAT_ATOMIC_UMAX
8348 
8349  GPUStaticInst*
8351  {
8352  return new Inst_FLAT__FLAT_ATOMIC_AND(&iFmt->iFmt_FLAT);
8353  } // decode_OP_FLAT__FLAT_ATOMIC_AND
8354 
8355  GPUStaticInst*
8357  {
8358  return new Inst_FLAT__FLAT_ATOMIC_OR(&iFmt->iFmt_FLAT);
8359  } // decode_OP_FLAT__FLAT_ATOMIC_OR
8360 
8361  GPUStaticInst*
8363  {
8364  return new Inst_FLAT__FLAT_ATOMIC_XOR(&iFmt->iFmt_FLAT);
8365  } // decode_OP_FLAT__FLAT_ATOMIC_XOR
8366 
8367  GPUStaticInst*
8369  {
8370  return new Inst_FLAT__FLAT_ATOMIC_INC(&iFmt->iFmt_FLAT);
8371  } // decode_OP_FLAT__FLAT_ATOMIC_INC
8372 
8373  GPUStaticInst*
8375  {
8376  return new Inst_FLAT__FLAT_ATOMIC_DEC(&iFmt->iFmt_FLAT);
8377  } // decode_OP_FLAT__FLAT_ATOMIC_DEC
8378 
8379  GPUStaticInst*
8381  {
8382  return new Inst_FLAT__FLAT_ATOMIC_SWAP_X2(&iFmt->iFmt_FLAT);
8383  } // decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2
8384 
8385  GPUStaticInst*
8387  {
8388  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2(&iFmt->iFmt_FLAT);
8389  } // decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2
8390 
8391  GPUStaticInst*
8393  {
8394  return new Inst_FLAT__FLAT_ATOMIC_ADD_X2(&iFmt->iFmt_FLAT);
8395  } // decode_OP_FLAT__FLAT_ATOMIC_ADD_X2
8396 
8397  GPUStaticInst*
8399  {
8400  return new Inst_FLAT__FLAT_ATOMIC_SUB_X2(&iFmt->iFmt_FLAT);
8401  } // decode_OP_FLAT__FLAT_ATOMIC_SUB_X2
8402 
8403  GPUStaticInst*
8405  {
8406  return new Inst_FLAT__FLAT_ATOMIC_SMIN_X2(&iFmt->iFmt_FLAT);
8407  } // decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2
8408 
8409  GPUStaticInst*
8411  {
8412  return new Inst_FLAT__FLAT_ATOMIC_UMIN_X2(&iFmt->iFmt_FLAT);
8413  } // decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2
8414 
8415  GPUStaticInst*
8417  {
8418  return new Inst_FLAT__FLAT_ATOMIC_SMAX_X2(&iFmt->iFmt_FLAT);
8419  } // decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2
8420 
8421  GPUStaticInst*
8423  {
8424  return new Inst_FLAT__FLAT_ATOMIC_UMAX_X2(&iFmt->iFmt_FLAT);
8425  } // decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2
8426 
8427  GPUStaticInst*
8429  {
8430  return new Inst_FLAT__FLAT_ATOMIC_AND_X2(&iFmt->iFmt_FLAT);
8431  } // decode_OP_FLAT__FLAT_ATOMIC_AND_X2
8432 
8433  GPUStaticInst*
8435  {
8436  return new Inst_FLAT__FLAT_ATOMIC_OR_X2(&iFmt->iFmt_FLAT);
8437  } // decode_OP_FLAT__FLAT_ATOMIC_OR_X2
8438 
8439  GPUStaticInst*
8441  {
8442  return new Inst_FLAT__FLAT_ATOMIC_XOR_X2(&iFmt->iFmt_FLAT);
8443  } // decode_OP_FLAT__FLAT_ATOMIC_XOR_X2
8444 
8445  GPUStaticInst*
8447  {
8448  return new Inst_FLAT__FLAT_ATOMIC_INC_X2(&iFmt->iFmt_FLAT);
8449  } // decode_OP_FLAT__FLAT_ATOMIC_INC_X2
8450 
8451  GPUStaticInst*
8453  {
8454  return new Inst_FLAT__FLAT_ATOMIC_DEC_X2(&iFmt->iFmt_FLAT);
8455  } // decode_OP_FLAT__FLAT_ATOMIC_DEC_X2
8456 
8457  GPUStaticInst*
8459  {
8460  return new Inst_FLAT__FLAT_LOAD_UBYTE(&iFmt->iFmt_FLAT);
8461  }
8462 
8463  GPUStaticInst*
8465  {
8466  return new Inst_FLAT__FLAT_LOAD_SBYTE(&iFmt->iFmt_FLAT);
8467  }
8468 
8469  GPUStaticInst*
8471  {
8472  return new Inst_FLAT__FLAT_LOAD_USHORT(&iFmt->iFmt_FLAT);
8473  }
8474 
8475  GPUStaticInst*
8477  {
8478  return new Inst_FLAT__FLAT_LOAD_SSHORT(&iFmt->iFmt_FLAT);
8479  }
8480 
8481  GPUStaticInst*
8483  {
8484  return new Inst_FLAT__FLAT_LOAD_DWORD(&iFmt->iFmt_FLAT);
8485  }
8486 
8487  GPUStaticInst*
8489  {
8490  return new Inst_FLAT__FLAT_LOAD_DWORDX2(&iFmt->iFmt_FLAT);
8491  }
8492 
8493  GPUStaticInst*
8495  {
8496  return new Inst_FLAT__FLAT_LOAD_DWORDX3(&iFmt->iFmt_FLAT);
8497  }
8498 
8499  GPUStaticInst*
8501  {
8502  return new Inst_FLAT__FLAT_LOAD_DWORDX4(&iFmt->iFmt_FLAT);
8503  }
8504 
8505  GPUStaticInst*
8507  {
8508  return new Inst_FLAT__FLAT_STORE_BYTE(&iFmt->iFmt_FLAT);
8509  }
8510 
8511  GPUStaticInst*
8513  {
8514  fatal("Trying to decode instruction without a class\n");
8515  return nullptr;
8516  }
8517 
8518  GPUStaticInst*
8520  {
8521  return new Inst_FLAT__FLAT_STORE_SHORT(&iFmt->iFmt_FLAT);
8522  }
8523 
8524  GPUStaticInst*
8526  {
8527  fatal("Trying to decode instruction without a class\n");
8528  return nullptr;
8529  }
8530 
8531  GPUStaticInst*
8533  {
8534  return new Inst_FLAT__FLAT_STORE_DWORD(&iFmt->iFmt_FLAT);
8535  return nullptr;
8536  }
8537 
8538  GPUStaticInst*
8540  {
8541  return new Inst_FLAT__FLAT_STORE_DWORDX2(&iFmt->iFmt_FLAT);
8542  }
8543 
8544  GPUStaticInst*
8546  {
8547  return new Inst_FLAT__FLAT_STORE_DWORDX3(&iFmt->iFmt_FLAT);
8548  }
8549 
8550  GPUStaticInst*
8552  {
8553  return new Inst_FLAT__FLAT_STORE_DWORDX4(&iFmt->iFmt_FLAT);
8554  }
8555 
8556  GPUStaticInst*
8558  {
8559  fatal("Trying to decode instruction without a class\n");
8560  return nullptr;
8561  }
8562 
8563  GPUStaticInst*
8565  {
8566  fatal("Trying to decode instruction without a class\n");
8567  return nullptr;
8568  }
8569 
8570  GPUStaticInst*
8572  {
8573  fatal("Trying to decode instruction without a class\n");
8574  return nullptr;
8575  }
8576 
8577  GPUStaticInst*
8579  {
8580  fatal("Trying to decode instruction without a class\n");
8581  return nullptr;
8582  }
8583 
8584  GPUStaticInst*
8586  {
8587  fatal("Trying to decode instruction without a class\n");
8588  return nullptr;
8589  }
8590 
8591  GPUStaticInst*
8593  {
8594  fatal("Trying to decode instruction without a class\n");
8595  return nullptr;
8596  }
8597 
8598  GPUStaticInst*
8600  {
8601  return new Inst_FLAT__FLAT_ATOMIC_SWAP(&iFmt->iFmt_FLAT);
8602  }
8603 
8604  GPUStaticInst*
8606  {
8607  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP(&iFmt->iFmt_FLAT);
8608  }
8609 
8610  GPUStaticInst*
8612  {
8613  return new Inst_FLAT__FLAT_ATOMIC_ADD(&iFmt->iFmt_FLAT);
8614  }
8615 
8616  GPUStaticInst*
8618  {
8619  return new Inst_FLAT__FLAT_ATOMIC_SUB(&iFmt->iFmt_FLAT);
8620  }
8621 
8622  GPUStaticInst*
8624  {
8625  return new Inst_FLAT__FLAT_ATOMIC_SMIN(&iFmt->iFmt_FLAT);
8626  }
8627 
8628  GPUStaticInst*
8630  {
8631  return new Inst_FLAT__FLAT_ATOMIC_UMIN(&iFmt->iFmt_FLAT);
8632  }
8633 
8634  GPUStaticInst*
8636  {
8637  return new Inst_FLAT__FLAT_ATOMIC_SMAX(&iFmt->iFmt_FLAT);
8638  }
8639 
8640  GPUStaticInst*
8642  {
8643  return new Inst_FLAT__FLAT_ATOMIC_UMAX(&iFmt->iFmt_FLAT);
8644  }
8645 
8646  GPUStaticInst*
8648  {
8649  return new Inst_FLAT__FLAT_ATOMIC_AND(&iFmt->iFmt_FLAT);
8650  }
8651 
8652  GPUStaticInst*
8654  {
8655  return new Inst_FLAT__FLAT_ATOMIC_OR(&iFmt->iFmt_FLAT);
8656  }
8657 
8658  GPUStaticInst*
8660  {
8661  return new Inst_FLAT__FLAT_ATOMIC_XOR(&iFmt->iFmt_FLAT);
8662  }
8663 
8664  GPUStaticInst*
8666  {
8667  return new Inst_FLAT__FLAT_ATOMIC_INC(&iFmt->iFmt_FLAT);
8668  }
8669 
8670  GPUStaticInst*
8672  {
8673  return new Inst_FLAT__FLAT_ATOMIC_DEC(&iFmt->iFmt_FLAT);
8674  }
8675 
8676  GPUStaticInst*
8678  {
8679  return new Inst_FLAT__FLAT_ATOMIC_SWAP_X2(&iFmt->iFmt_FLAT);
8680  }
8681 
8682  GPUStaticInst*
8684  {
8685  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2(&iFmt->iFmt_FLAT);
8686  }
8687 
8688  GPUStaticInst*
8690  {
8691  return new Inst_FLAT__FLAT_ATOMIC_ADD_X2(&iFmt->iFmt_FLAT);
8692  }
8693 
8694  GPUStaticInst*
8696  {
8697  return new Inst_FLAT__FLAT_ATOMIC_SUB_X2(&iFmt->iFmt_FLAT);
8698  }
8699 
8700  GPUStaticInst*
8702  {
8703  return new Inst_FLAT__FLAT_ATOMIC_SMIN_X2(&iFmt->iFmt_FLAT);
8704  }
8705 
8706  GPUStaticInst*
8708  {
8709  return new Inst_FLAT__FLAT_ATOMIC_UMIN_X2(&iFmt->iFmt_FLAT);
8710  }
8711 
8712  GPUStaticInst*
8714  {
8715  return new Inst_FLAT__FLAT_ATOMIC_SMAX_X2(&iFmt->iFmt_FLAT);
8716  }
8717 
8718  GPUStaticInst*
8720  {
8721  return new Inst_FLAT__FLAT_ATOMIC_UMAX_X2(&iFmt->iFmt_FLAT);
8722  }
8723 
8724  GPUStaticInst*
8726  {
8727  return new Inst_FLAT__FLAT_ATOMIC_AND_X2(&iFmt->iFmt_FLAT);
8728  }
8729 
8730  GPUStaticInst*
8732  {
8733  return new Inst_FLAT__FLAT_ATOMIC_OR_X2(&iFmt->iFmt_FLAT);
8734  }
8735 
8736  GPUStaticInst*
8738  {
8739  return new Inst_FLAT__FLAT_ATOMIC_XOR_X2(&iFmt->iFmt_FLAT);
8740  }
8741 
8742  GPUStaticInst*
8744  {
8745  return new Inst_FLAT__FLAT_ATOMIC_INC_X2(&iFmt->iFmt_FLAT);
8746  }
8747 
8748  GPUStaticInst*
8750  {
8751  return new Inst_FLAT__FLAT_ATOMIC_DEC_X2(&iFmt->iFmt_FLAT);
8752  }
8753 
8754  GPUStaticInst*
8756  {
8757  return new Inst_MIMG__IMAGE_LOAD(&iFmt->iFmt_MIMG);
8758  } // decode_OP_MIMG__IMAGE_LOAD
8759 
8760  GPUStaticInst*
8762  {
8763  return new Inst_MIMG__IMAGE_LOAD_MIP(&iFmt->iFmt_MIMG);
8764  } // decode_OP_MIMG__IMAGE_LOAD_MIP
8765 
8766  GPUStaticInst*
8768  {
8769  return new Inst_MIMG__IMAGE_LOAD_PCK(&iFmt->iFmt_MIMG);
8770  } // decode_OP_MIMG__IMAGE_LOAD_PCK
8771 
8772  GPUStaticInst*
8774  {
8775  return new Inst_MIMG__IMAGE_LOAD_PCK_SGN(&iFmt->iFmt_MIMG);
8776  } // decode_OP_MIMG__IMAGE_LOAD_PCK_SGN
8777 
8778  GPUStaticInst*
8780  {
8781  return new Inst_MIMG__IMAGE_LOAD_MIP_PCK(&iFmt->iFmt_MIMG);
8782  } // decode_OP_MIMG__IMAGE_LOAD_MIP_PCK
8783 
8784  GPUStaticInst*
8786  {
8787  return new Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN(&iFmt->iFmt_MIMG);
8788  } // decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN
8789 
8790  GPUStaticInst*
8792  {
8793  return new Inst_MIMG__IMAGE_STORE(&iFmt->iFmt_MIMG);
8794  } // decode_OP_MIMG__IMAGE_STORE
8795 
8796  GPUStaticInst*
8798  {
8799  return new Inst_MIMG__IMAGE_STORE_MIP(&iFmt->iFmt_MIMG);
8800  } // decode_OP_MIMG__IMAGE_STORE_MIP
8801 
8802  GPUStaticInst*
8804  {
8805  return new Inst_MIMG__IMAGE_STORE_PCK(&iFmt->iFmt_MIMG);
8806  } // decode_OP_MIMG__IMAGE_STORE_PCK
8807 
8808  GPUStaticInst*
8810  {
8811  return new Inst_MIMG__IMAGE_STORE_MIP_PCK(&iFmt->iFmt_MIMG);
8812  } // decode_OP_MIMG__IMAGE_STORE_MIP_PCK
8813 
8814  GPUStaticInst*
8816  {
8817  return new Inst_MIMG__IMAGE_GET_RESINFO(&iFmt->iFmt_MIMG);
8818  } // decode_OP_MIMG__IMAGE_GET_RESINFO
8819 
8820  GPUStaticInst*
8822  {
8823  return new Inst_MIMG__IMAGE_ATOMIC_SWAP(&iFmt->iFmt_MIMG);
8824  } // decode_OP_MIMG__IMAGE_ATOMIC_SWAP
8825 
8826  GPUStaticInst*
8828  {
8829  return new Inst_MIMG__IMAGE_ATOMIC_CMPSWAP(&iFmt->iFmt_MIMG);
8830  } // decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP
8831 
8832  GPUStaticInst*
8834  {
8835  return new Inst_MIMG__IMAGE_ATOMIC_ADD(&iFmt->iFmt_MIMG);
8836  } // decode_OP_MIMG__IMAGE_ATOMIC_ADD
8837 
8838  GPUStaticInst*
8840  {
8841  return new Inst_MIMG__IMAGE_ATOMIC_SUB(&iFmt->iFmt_MIMG);
8842  } // decode_OP_MIMG__IMAGE_ATOMIC_SUB
8843 
8844  GPUStaticInst*
8846  {
8847  return new Inst_MIMG__IMAGE_ATOMIC_SMIN(&iFmt->iFmt_MIMG);
8848  } // decode_OP_MIMG__IMAGE_ATOMIC_SMIN
8849 
8850  GPUStaticInst*
8852  {
8853  return new Inst_MIMG__IMAGE_ATOMIC_UMIN(&iFmt->iFmt_MIMG);
8854  } // decode_OP_MIMG__IMAGE_ATOMIC_UMIN
8855 
8856  GPUStaticInst*
8858  {
8859  return new Inst_MIMG__IMAGE_ATOMIC_SMAX(&iFmt->iFmt_MIMG);
8860  } // decode_OP_MIMG__IMAGE_ATOMIC_SMAX
8861 
8862  GPUStaticInst*
8864  {
8865  return new Inst_MIMG__IMAGE_ATOMIC_UMAX(&iFmt->iFmt_MIMG);
8866  } // decode_OP_MIMG__IMAGE_ATOMIC_UMAX
8867 
8868  GPUStaticInst*
8870  {
8871  return new Inst_MIMG__IMAGE_ATOMIC_AND(&iFmt->iFmt_MIMG);
8872  } // decode_OP_MIMG__IMAGE_ATOMIC_AND
8873 
8874  GPUStaticInst*
8876  {
8877  return new Inst_MIMG__IMAGE_ATOMIC_OR(&iFmt->iFmt_MIMG);
8878  } // decode_OP_MIMG__IMAGE_ATOMIC_OR
8879 
8880  GPUStaticInst*
8882  {
8883  return new Inst_MIMG__IMAGE_ATOMIC_XOR(&iFmt->iFmt_MIMG);
8884  } // decode_OP_MIMG__IMAGE_ATOMIC_XOR
8885 
8886  GPUStaticInst*
8888  {
8889  return new Inst_MIMG__IMAGE_ATOMIC_INC(&iFmt->iFmt_MIMG);
8890  } // decode_OP_MIMG__IMAGE_ATOMIC_INC
8891 
8892  GPUStaticInst*
8894  {
8895  return new Inst_MIMG__IMAGE_ATOMIC_DEC(&iFmt->iFmt_MIMG);
8896  } // decode_OP_MIMG__IMAGE_ATOMIC_DEC
8897 
8898  GPUStaticInst*
8900  {
8901  return new Inst_MIMG__IMAGE_SAMPLE(&iFmt->iFmt_MIMG);
8902  } // decode_OP_MIMG__IMAGE_SAMPLE
8903 
8904  GPUStaticInst*
8906  {
8907  return new Inst_MIMG__IMAGE_SAMPLE_CL(&iFmt->iFmt_MIMG);
8908  } // decode_OP_MIMG__IMAGE_SAMPLE_CL
8909 
8910  GPUStaticInst*
8912  {
8913  return new Inst_MIMG__IMAGE_SAMPLE_D(&iFmt->iFmt_MIMG);
8914  } // decode_OP_MIMG__IMAGE_SAMPLE_D
8915 
8916  GPUStaticInst*
8918  {
8919  return new Inst_MIMG__IMAGE_SAMPLE_D_CL(&iFmt->iFmt_MIMG);
8920  } // decode_OP_MIMG__IMAGE_SAMPLE_D_CL
8921 
8922  GPUStaticInst*
8924  {
8925  return new Inst_MIMG__IMAGE_SAMPLE_L(&iFmt->iFmt_MIMG);
8926  } // decode_OP_MIMG__IMAGE_SAMPLE_L
8927 
8928  GPUStaticInst*
8930  {
8931  return new Inst_MIMG__IMAGE_SAMPLE_B(&iFmt->iFmt_MIMG);
8932  } // decode_OP_MIMG__IMAGE_SAMPLE_B
8933 
8934  GPUStaticInst*
8936  {
8937  return new Inst_MIMG__IMAGE_SAMPLE_B_CL(&iFmt->iFmt_MIMG);
8938  } // decode_OP_MIMG__IMAGE_SAMPLE_B_CL
8939 
8940  GPUStaticInst*
8942  {
8943  return new Inst_MIMG__IMAGE_SAMPLE_LZ(&iFmt->iFmt_MIMG);
8944  } // decode_OP_MIMG__IMAGE_SAMPLE_LZ
8945 
8946  GPUStaticInst*
8948  {
8949  return new Inst_MIMG__IMAGE_SAMPLE_C(&iFmt->iFmt_MIMG);
8950  } // decode_OP_MIMG__IMAGE_SAMPLE_C
8951 
8952  GPUStaticInst*
8954  {
8955  return new Inst_MIMG__IMAGE_SAMPLE_C_CL(&iFmt->iFmt_MIMG);
8956  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CL
8957 
8958  GPUStaticInst*
8960  {
8961  return new Inst_MIMG__IMAGE_SAMPLE_C_D(&iFmt->iFmt_MIMG);
8962  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D
8963 
8964  GPUStaticInst*
8966  {
8967  return new Inst_MIMG__IMAGE_SAMPLE_C_D_CL(&iFmt->iFmt_MIMG);
8968  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL
8969 
8970  GPUStaticInst*
8972  {
8973  return new Inst_MIMG__IMAGE_SAMPLE_C_L(&iFmt->iFmt_MIMG);
8974  } // decode_OP_MIMG__IMAGE_SAMPLE_C_L
8975 
8976  GPUStaticInst*
8978  {
8979  return new Inst_MIMG__IMAGE_SAMPLE_C_B(&iFmt->iFmt_MIMG);
8980  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B
8981 
8982  GPUStaticInst*
8984  {
8985  return new Inst_MIMG__IMAGE_SAMPLE_C_B_CL(&iFmt->iFmt_MIMG);
8986  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL
8987 
8988  GPUStaticInst*
8990  {
8991  return new Inst_MIMG__IMAGE_SAMPLE_C_LZ(&iFmt->iFmt_MIMG);
8992  } // decode_OP_MIMG__IMAGE_SAMPLE_C_LZ
8993 
8994  GPUStaticInst*
8996  {
8997  return new Inst_MIMG__IMAGE_SAMPLE_O(&iFmt->iFmt_MIMG);
8998  } // decode_OP_MIMG__IMAGE_SAMPLE_O
8999 
9000  GPUStaticInst*
9002  {
9003  return new Inst_MIMG__IMAGE_SAMPLE_CL_O(&iFmt->iFmt_MIMG);
9004  } // decode_OP_MIMG__IMAGE_SAMPLE_CL_O
9005 
9006  GPUStaticInst*
9008  {
9009  return new Inst_MIMG__IMAGE_SAMPLE_D_O(&iFmt->iFmt_MIMG);
9010  } // decode_OP_MIMG__IMAGE_SAMPLE_D_O
9011 
9012  GPUStaticInst*
9014  {
9015  return new Inst_MIMG__IMAGE_SAMPLE_D_CL_O(&iFmt->iFmt_MIMG);
9016  } // decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O
9017 
9018  GPUStaticInst*
9020  {
9021  return new Inst_MIMG__IMAGE_SAMPLE_L_O(&iFmt->iFmt_MIMG);
9022  } // decode_OP_MIMG__IMAGE_SAMPLE_L_O
9023 
9024  GPUStaticInst*
9026  {
9027  return new Inst_MIMG__IMAGE_SAMPLE_B_O(&iFmt->iFmt_MIMG);
9028  } // decode_OP_MIMG__IMAGE_SAMPLE_B_O
9029 
9030  GPUStaticInst*
9032  {
9033  return new Inst_MIMG__IMAGE_SAMPLE_B_CL_O(&iFmt->iFmt_MIMG);
9034  } // decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O
9035 
9036  GPUStaticInst*
9038  {
9039  return new Inst_MIMG__IMAGE_SAMPLE_LZ_O(&iFmt->iFmt_MIMG);
9040  } // decode_OP_MIMG__IMAGE_SAMPLE_LZ_O
9041 
9042  GPUStaticInst*
9044  {
9045  return new Inst_MIMG__IMAGE_SAMPLE_C_O(&iFmt->iFmt_MIMG);
9046  } // decode_OP_MIMG__IMAGE_SAMPLE_C_O
9047 
9048  GPUStaticInst*
9050  {
9051  return new Inst_MIMG__IMAGE_SAMPLE_C_CL_O(&iFmt->iFmt_MIMG);
9052  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O
9053 
9054  GPUStaticInst*
9056  {
9057  return new Inst_MIMG__IMAGE_SAMPLE_C_D_O(&iFmt->iFmt_MIMG);
9058  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_O
9059 
9060  GPUStaticInst*
9062  {
9063  return new Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O(&iFmt->iFmt_MIMG);
9064  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O
9065 
9066  GPUStaticInst*
9068  {
9069  return new Inst_MIMG__IMAGE_SAMPLE_C_L_O(&iFmt->iFmt_MIMG);
9070  } // decode_OP_MIMG__IMAGE_SAMPLE_C_L_O
9071 
9072  GPUStaticInst*
9074  {
9075  return new Inst_MIMG__IMAGE_SAMPLE_C_B_O(&iFmt->iFmt_MIMG);
9076  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_O
9077 
9078  GPUStaticInst*
9080  {
9081  return new Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O(&iFmt->iFmt_MIMG);
9082  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O
9083 
9084  GPUStaticInst*
9086  {
9087  return new Inst_MIMG__IMAGE_SAMPLE_C_LZ_O(&iFmt->iFmt_MIMG);
9088  } // decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O
9089 
9090  GPUStaticInst*
9092  {
9093  return new Inst_MIMG__IMAGE_GATHER4(&iFmt->iFmt_MIMG);
9094  } // decode_OP_MIMG__IMAGE_GATHER4
9095 
9096  GPUStaticInst*
9098  {
9099  return new Inst_MIMG__IMAGE_GATHER4_CL(&iFmt->iFmt_MIMG);
9100  } // decode_OP_MIMG__IMAGE_GATHER4_CL
9101 
9102  GPUStaticInst*
9104  {
9105  fatal("Trying to decode instruction without a class\n");
9106  return nullptr;
9107  }
9108 
9109  GPUStaticInst*
9111  {
9112  return new Inst_MIMG__IMAGE_GATHER4_L(&iFmt->iFmt_MIMG);
9113  } // decode_OP_MIMG__IMAGE_GATHER4_L
9114 
9115  GPUStaticInst*
9117  {
9118  return new Inst_MIMG__IMAGE_GATHER4_B(&iFmt->iFmt_MIMG);
9119  } // decode_OP_MIMG__IMAGE_GATHER4_B
9120 
9121  GPUStaticInst*
9123  {
9124  return new Inst_MIMG__IMAGE_GATHER4_B_CL(&iFmt->iFmt_MIMG);
9125  } // decode_OP_MIMG__IMAGE_GATHER4_B_CL
9126 
9127  GPUStaticInst*
9129  {
9130  return new Inst_MIMG__IMAGE_GATHER4_LZ(&iFmt->iFmt_MIMG);
9131  } // decode_OP_MIMG__IMAGE_GATHER4_LZ
9132 
9133  GPUStaticInst*
9135  {
9136  return new Inst_MIMG__IMAGE_GATHER4_C(&iFmt->iFmt_MIMG);
9137  } // decode_OP_MIMG__IMAGE_GATHER4_C
9138 
9139  GPUStaticInst*
9141  {
9142  return new Inst_MIMG__IMAGE_GATHER4_C_CL(&iFmt->iFmt_MIMG);
9143  } // decode_OP_MIMG__IMAGE_GATHER4_C_CL
9144 
9145  GPUStaticInst*
9147  {
9148  fatal("Trying to decode instruction without a class\n");
9149  return nullptr;
9150  }
9151 
9152  GPUStaticInst*
9154  {
9155  fatal("Trying to decode instruction without a class\n");
9156  return nullptr;
9157  }
9158 
9159  GPUStaticInst*
9161  {
9162  return new Inst_MIMG__IMAGE_GATHER4_C_L(&iFmt->iFmt_MIMG);
9163  } // decode_OP_MIMG__IMAGE_GATHER4_C_L
9164 
9165  GPUStaticInst*
9167  {
9168  return new Inst_MIMG__IMAGE_GATHER4_C_B(&iFmt->iFmt_MIMG);
9169  } // decode_OP_MIMG__IMAGE_GATHER4_C_B
9170 
9171  GPUStaticInst*
9173  {
9174  return new Inst_MIMG__IMAGE_GATHER4_C_B_CL(&iFmt->iFmt_MIMG);
9175  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_CL
9176 
9177  GPUStaticInst*
9179  {
9180  return new Inst_MIMG__IMAGE_GATHER4_C_LZ(&iFmt->iFmt_MIMG);
9181  } // decode_OP_MIMG__IMAGE_GATHER4_C_LZ
9182 
9183  GPUStaticInst*
9185  {
9186  return new Inst_MIMG__IMAGE_GATHER4_O(&iFmt->iFmt_MIMG);
9187  } // decode_OP_MIMG__IMAGE_GATHER4_O
9188 
9189  GPUStaticInst*
9191  {
9192  return new Inst_MIMG__IMAGE_GATHER4_CL_O(&iFmt->iFmt_MIMG);
9193  } // decode_OP_MIMG__IMAGE_GATHER4_CL_O
9194 
9195  GPUStaticInst*
9197  {
9198  return new Inst_MIMG__IMAGE_GATHER4_L_O(&iFmt->iFmt_MIMG);
9199  } // decode_OP_MIMG__IMAGE_GATHER4_L_O
9200 
9201  GPUStaticInst*
9203  {
9204  return new Inst_MIMG__IMAGE_GATHER4_B_O(&iFmt->iFmt_MIMG);
9205  } // decode_OP_MIMG__IMAGE_GATHER4_B_O
9206 
9207  GPUStaticInst*
9209  {
9210  return new Inst_MIMG__IMAGE_GATHER4_B_CL_O(&iFmt->iFmt_MIMG);
9211  } // decode_OP_MIMG__IMAGE_GATHER4_B_CL_O
9212 
9213  GPUStaticInst*
9215  {
9216  return new Inst_MIMG__IMAGE_GATHER4_LZ_O(&iFmt->iFmt_MIMG);
9217  } // decode_OP_MIMG__IMAGE_GATHER4_LZ_O
9218 
9219  GPUStaticInst*
9221  {
9222  return new Inst_MIMG__IMAGE_GATHER4_C_O(&iFmt->iFmt_MIMG);
9223  } // decode_OP_MIMG__IMAGE_GATHER4_C_O
9224 
9225  GPUStaticInst*
9227  {
9228  return new Inst_MIMG__IMAGE_GATHER4_C_CL_O(&iFmt->iFmt_MIMG);
9229  } // decode_OP_MIMG__IMAGE_GATHER4_C_CL_O
9230 
9231  GPUStaticInst*
9233  {
9234  return new Inst_MIMG__IMAGE_GATHER4_C_L_O(&iFmt->iFmt_MIMG);
9235  } // decode_OP_MIMG__IMAGE_GATHER4_C_L_O
9236 
9237  GPUStaticInst*
9239  {
9240  return new Inst_MIMG__IMAGE_GATHER4_C_B_O(&iFmt->iFmt_MIMG);
9241  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_O
9242 
9243  GPUStaticInst*
9245  {
9246  return new Inst_MIMG__IMAGE_GATHER4_C_B_CL_O(&iFmt->iFmt_MIMG);
9247  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O
9248 
9249  GPUStaticInst*
9251  {
9252  return new Inst_MIMG__IMAGE_GATHER4_C_LZ_O(&iFmt->iFmt_MIMG);
9253  } // decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O
9254 
9255  GPUStaticInst*
9257  {
9258  return new Inst_MIMG__IMAGE_GET_LOD(&iFmt->iFmt_MIMG);
9259  } // decode_OP_MIMG__IMAGE_GET_LOD
9260 
9261  GPUStaticInst*
9263  {
9264  return new Inst_MIMG__IMAGE_SAMPLE_CD(&iFmt->iFmt_MIMG);
9265  } // decode_OP_MIMG__IMAGE_SAMPLE_CD
9266 
9267  GPUStaticInst*
9269  {
9270  return new Inst_MIMG__IMAGE_SAMPLE_CD_CL(&iFmt->iFmt_MIMG);
9271  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_CL
9272 
9273  GPUStaticInst*
9275  {
9276  return new Inst_MIMG__IMAGE_SAMPLE_C_CD(&iFmt->iFmt_MIMG);
9277  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD
9278 
9279  GPUStaticInst*
9281  {
9282  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_CL(&iFmt->iFmt_MIMG);
9283  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL
9284 
9285  GPUStaticInst*
9287  {
9288  return new Inst_MIMG__IMAGE_SAMPLE_CD_O(&iFmt->iFmt_MIMG);
9289  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_O
9290 
9291  GPUStaticInst*
9293  {
9294  return new Inst_MIMG__IMAGE_SAMPLE_CD_CL_O(&iFmt->iFmt_MIMG);
9295  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O
9296 
9297  GPUStaticInst*
9299  {
9300  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_O(&iFmt->iFmt_MIMG);
9301  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O
9302 
9303  GPUStaticInst*
9305  {
9306  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O(&iFmt->iFmt_MIMG);
9307  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O
9308 
9309  GPUStaticInst*
9311  {
9312  return new Inst_MTBUF__TBUFFER_LOAD_FORMAT_X(&iFmt->iFmt_MTBUF);
9313  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X
9314 
9315  GPUStaticInst*
9317  {
9319  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY
9320 
9321  GPUStaticInst*
9323  {
9325  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
9326 
9327  GPUStaticInst*
9329  {
9331  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
9332 
9333  GPUStaticInst*
9335  {
9337  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X
9338 
9339  GPUStaticInst*
9341  {
9343  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY
9344 
9345  GPUStaticInst*
9347  {
9349  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ
9350 
9351  GPUStaticInst*
9353  {
9355  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW
9356 
9357  GPUStaticInst*
9359  {
9361  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
9362 
9363  GPUStaticInst*
9365  {
9367  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
9368 
9369  GPUStaticInst*
9371  {
9373  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
9374 
9375  GPUStaticInst*
9377  {
9379  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
9380 
9381  GPUStaticInst*
9383  {
9385  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X
9386 
9387  GPUStaticInst*
9389  {
9391  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
9392 
9393  GPUStaticInst*
9395  {
9397  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
9398 
9399  GPUStaticInst*
9401  {
9402  return new
9404  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
9405 
9406  GPUStaticInst*
9408  {
9409  return new Inst_MUBUF__BUFFER_LOAD_FORMAT_X(&iFmt->iFmt_MUBUF);
9410  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X
9411 
9412  GPUStaticInst*
9414  {
9415  return new Inst_MUBUF__BUFFER_LOAD_FORMAT_XY(&iFmt->iFmt_MUBUF);
9416  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY
9417 
9418  GPUStaticInst*
9420  {
9422  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ
9423 
9424  GPUStaticInst*
9426  {
9428  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW
9429 
9430  GPUStaticInst*
9432  {
9433  return new Inst_MUBUF__BUFFER_STORE_FORMAT_X(&iFmt->iFmt_MUBUF);
9434  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_X
9435 
9436  GPUStaticInst*
9438  {
9440  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY
9441 
9442  GPUStaticInst*
9444  {
9446  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ
9447 
9448  GPUStaticInst*
9450  {
9452  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW
9453 
9454  GPUStaticInst*
9456  {
9458  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X
9459 
9460  GPUStaticInst*
9462  {
9464  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
9465 
9466  GPUStaticInst*
9468  {
9470  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
9471 
9472  GPUStaticInst*
9474  {
9476  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
9477 
9478  GPUStaticInst*
9480  {
9482  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X
9483 
9484  GPUStaticInst*
9486  {
9488  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY
9489 
9490  GPUStaticInst*
9492  {
9494  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
9495 
9496  GPUStaticInst*
9498  {
9500  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
9501 
9502  GPUStaticInst*
9504  {
9505  return new Inst_MUBUF__BUFFER_LOAD_UBYTE(&iFmt->iFmt_MUBUF);
9506  } // decode_OP_MUBUF__BUFFER_LOAD_UBYTE
9507 
9508  GPUStaticInst*
9510  {
9511  return new Inst_MUBUF__BUFFER_LOAD_SBYTE(&iFmt->iFmt_MUBUF);
9512  } // decode_OP_MUBUF__BUFFER_LOAD_SBYTE
9513 
9514  GPUStaticInst*
9516  {
9517  return new Inst_MUBUF__BUFFER_LOAD_USHORT(&iFmt->iFmt_MUBUF);
9518  } // decode_OP_MUBUF__BUFFER_LOAD_USHORT
9519 
9520  GPUStaticInst*
9522  {
9523  return new Inst_MUBUF__BUFFER_LOAD_SSHORT(&iFmt->iFmt_MUBUF);
9524  } // decode_OP_MUBUF__BUFFER_LOAD_SSHORT
9525 
9526  GPUStaticInst*
9528  {
9529  return new Inst_MUBUF__BUFFER_LOAD_DWORD(&iFmt->iFmt_MUBUF);
9530  } // decode_OP_MUBUF__BUFFER_LOAD_DWORD
9531 
9532  GPUStaticInst*
9534  {
9535  return new Inst_MUBUF__BUFFER_LOAD_DWORDX2(&iFmt->iFmt_MUBUF);
9536  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX2
9537 
9538  GPUStaticInst*
9540  {
9541  return new Inst_MUBUF__BUFFER_LOAD_DWORDX3(&iFmt->iFmt_MUBUF);
9542  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX3
9543 
9544  GPUStaticInst*
9546  {
9547  return new Inst_MUBUF__BUFFER_LOAD_DWORDX4(&iFmt->iFmt_MUBUF);
9548  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX4
9549 
9550  GPUStaticInst*
9552  {
9553  return new Inst_MUBUF__BUFFER_STORE_BYTE(&iFmt->iFmt_MUBUF);
9554  } // decode_OP_MUBUF__BUFFER_STORE_BYTE
9555 
9556  GPUStaticInst*
9558  {
9559  fatal("Trying to decode instruction without a class\n");
9560  return nullptr;
9561  }
9562 
9563  GPUStaticInst*
9565  {
9566  return new Inst_MUBUF__BUFFER_STORE_SHORT(&iFmt->iFmt_MUBUF);
9567  } // decode_OP_MUBUF__BUFFER_STORE_SHORT
9568 
9569  GPUStaticInst*
9571  {
9572  fatal("Trying to decode instruction without a class\n");
9573  return nullptr;
9574  }
9575 
9576  GPUStaticInst*
9578  {
9579  return new Inst_MUBUF__BUFFER_STORE_DWORD(&iFmt->iFmt_MUBUF);
9580  } // decode_OP_MUBUF__BUFFER_STORE_DWORD
9581 
9582  GPUStaticInst*
9584  {
9585  return new Inst_MUBUF__BUFFER_STORE_DWORDX2(&iFmt->iFmt_MUBUF);
9586  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX2
9587 
9588  GPUStaticInst*
9590  {
9591  return new Inst_MUBUF__BUFFER_STORE_DWORDX3(&iFmt->iFmt_MUBUF);
9592  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX3
9593 
9594  GPUStaticInst*
9596  {
9597  return new Inst_MUBUF__BUFFER_STORE_DWORDX4(&iFmt->iFmt_MUBUF);
9598  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX4
9599 
9600  GPUStaticInst*
9602  {
9604  } // decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD
9605 
9606  GPUStaticInst*
9608  {
9609  return new Inst_MUBUF__BUFFER_WBINVL1(&iFmt->iFmt_MUBUF);
9610  } // decode_OP_MUBUF__BUFFER_WBINVL1
9611 
9612  GPUStaticInst*
9614  {
9615  return new Inst_MUBUF__BUFFER_WBINVL1_VOL(&iFmt->iFmt_MUBUF);
9616  } // decode_OP_MUBUF__BUFFER_WBINVL1_VOL
9617 
9618  GPUStaticInst*
9620  {
9621  return new Inst_MUBUF__BUFFER_ATOMIC_SWAP(&iFmt->iFmt_MUBUF);
9622  } // decode_OP_MUBUF__BUFFER_ATOMIC_SWAP
9623 
9624  GPUStaticInst*
9626  {
9627  return new Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP(&iFmt->iFmt_MUBUF);
9628  } // decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP
9629 
9630  GPUStaticInst*
9632  {
9633  return new Inst_MUBUF__BUFFER_ATOMIC_ADD(&iFmt->iFmt_MUBUF);
9634  } // decode_OP_MUBUF__BUFFER_ATOMIC_ADD
9635 
9636  GPUStaticInst*
9638  {
9639  return new Inst_MUBUF__BUFFER_ATOMIC_SUB(&iFmt->iFmt_MUBUF);
9640  } // decode_OP_MUBUF__BUFFER_ATOMIC_SUB
9641 
9642  GPUStaticInst*
9644  {
9645  return new Inst_MUBUF__BUFFER_ATOMIC_SMIN(&iFmt->iFmt_MUBUF);
9646  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMIN
9647 
9648  GPUStaticInst*
9650  {
9651  return new Inst_MUBUF__BUFFER_ATOMIC_UMIN(&iFmt->iFmt_MUBUF);
9652  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMIN
9653 
9654  GPUStaticInst*
9656  {
9657  return new Inst_MUBUF__BUFFER_ATOMIC_SMAX(&iFmt->iFmt_MUBUF);
9658  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMAX
9659 
9660  GPUStaticInst*
9662  {
9663  return new Inst_MUBUF__BUFFER_ATOMIC_UMAX(&iFmt->iFmt_MUBUF);
9664  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMAX
9665 
9666  GPUStaticInst*
9668  {
9669  return new Inst_MUBUF__BUFFER_ATOMIC_AND(&iFmt->iFmt_MUBUF);
9670  } // decode_OP_MUBUF__BUFFER_ATOMIC_AND
9671 
9672  GPUStaticInst*
9674  {
9675  return new Inst_MUBUF__BUFFER_ATOMIC_OR(&iFmt->iFmt_MUBUF);
9676  } // decode_OP_MUBUF__BUFFER_ATOMIC_OR
9677 
9678  GPUStaticInst*
9680  {
9681  return new Inst_MUBUF__BUFFER_ATOMIC_XOR(&iFmt->iFmt_MUBUF);
9682  } // decode_OP_MUBUF__BUFFER_ATOMIC_XOR
9683 
9684  GPUStaticInst*
9686  {
9687  return new Inst_MUBUF__BUFFER_ATOMIC_INC(&iFmt->iFmt_MUBUF);
9688  } // decode_OP_MUBUF__BUFFER_ATOMIC_INC
9689 
9690  GPUStaticInst*
9692  {
9693  return new Inst_MUBUF__BUFFER_ATOMIC_DEC(&iFmt->iFmt_MUBUF);
9694  } // decode_OP_MUBUF__BUFFER_ATOMIC_DEC
9695 
9696  GPUStaticInst*
9698  {
9699  return new Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2(&iFmt->iFmt_MUBUF);
9700  } // decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2
9701 
9702  GPUStaticInst*
9704  {
9706  } // decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
9707 
9708  GPUStaticInst*
9710  {
9711  return new Inst_MUBUF__BUFFER_ATOMIC_ADD_X2(&iFmt->iFmt_MUBUF);
9712  } // decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2
9713 
9714  GPUStaticInst*
9716  {
9717  return new Inst_MUBUF__BUFFER_ATOMIC_SUB_X2(&iFmt->iFmt_MUBUF);
9718  } // decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2
9719 
9720  GPUStaticInst*
9722  {
9723  return new Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2(&iFmt->iFmt_MUBUF);
9724  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2
9725 
9726  GPUStaticInst*
9728  {
9729  return new Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2(&iFmt->iFmt_MUBUF);
9730  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2
9731 
9732  GPUStaticInst*
9734  {
9735  return new Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2(&iFmt->iFmt_MUBUF);
9736  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2
9737 
9738  GPUStaticInst*
9740  {
9741  return new Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2(&iFmt->iFmt_MUBUF);
9742  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2
9743 
9744  GPUStaticInst*
9746  {
9747  return new Inst_MUBUF__BUFFER_ATOMIC_AND_X2(&iFmt->iFmt_MUBUF);
9748  } // decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2
9749 
9750  GPUStaticInst*
9752  {
9753  return new Inst_MUBUF__BUFFER_ATOMIC_OR_X2(&iFmt->iFmt_MUBUF);
9754  } // decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2
9755 
9756  GPUStaticInst*
9758  {
9759  return new Inst_MUBUF__BUFFER_ATOMIC_XOR_X2(&iFmt->iFmt_MUBUF);
9760  } // decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2
9761 
9762  GPUStaticInst*
9764  {
9765  return new Inst_MUBUF__BUFFER_ATOMIC_INC_X2(&iFmt->iFmt_MUBUF);
9766  } // decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2
9767 
9768  GPUStaticInst*
9770  {
9771  return new Inst_MUBUF__BUFFER_ATOMIC_DEC_X2(&iFmt->iFmt_MUBUF);
9772  } // decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2
9773 
9774  GPUStaticInst*
9776  {
9777  fatal("Trying to decode instruction without a class\n");
9778  return nullptr;
9779  }
9780 
9781  GPUStaticInst*
9783  {
9784  fatal("Trying to decode instruction without a class\n");
9785  return nullptr;
9786  }
9787 
9788  GPUStaticInst*
9790  {
9791  fatal("Trying to decode instruction without a class\n");
9792  return nullptr;
9793  }
9794 
9795  GPUStaticInst*
9797  {
9798  fatal("Trying to decode instruction without a class\n");
9799  return nullptr;
9800  }
9801 
9802  GPUStaticInst*
9804  {
9805  fatal("Trying to decode instruction without a class\n");
9806  return nullptr;
9807  }
9808 
9809  GPUStaticInst*
9811  {
9812  fatal("Trying to decode instruction without a class\n");
9813  return nullptr;
9814  }
9815 
9816  GPUStaticInst*
9818  {
9819  fatal("Trying to decode instruction without a class\n");
9820  return nullptr;
9821  }
9822 
9823  GPUStaticInst*
9825  {
9826  fatal("Trying to decode instruction without a class\n");
9827  return nullptr;
9828  }
9829 
9830  GPUStaticInst*
9832  {
9833  fatal("Trying to decode instruction without a class\n");
9834  return nullptr;
9835  }
9836 
9837  GPUStaticInst*
9839  {
9840  fatal("Trying to decode instruction without a class\n");
9841  return nullptr;
9842  }
9843 
9844  GPUStaticInst*
9846  {
9847  fatal("Trying to decode instruction without a class\n");
9848  return nullptr;
9849  }
9850 
9851  GPUStaticInst*
9853  {
9854  fatal("Trying to decode instruction without a class\n");
9855  return nullptr;
9856  }
9857 
9858  GPUStaticInst*
9860  {
9861  fatal("Trying to decode instruction without a class\n");
9862  return nullptr;
9863  }
9864 
9865  GPUStaticInst*
9867  {
9868  fatal("Trying to decode instruction without a class\n");
9869  return nullptr;
9870  }
9871 
9872  GPUStaticInst*
9874  {
9875  fatal("Trying to decode instruction without a class\n");
9876  return nullptr;
9877  }
9878 
9879  GPUStaticInst*
9881  {
9882  fatal("Trying to decode instruction without a class\n");
9883  return nullptr;
9884  }
9885 
9886  GPUStaticInst*
9888  {
9889  fatal("Trying to decode instruction without a class\n");
9890  return nullptr;
9891  }
9892 
9893  GPUStaticInst*
9895  {
9896  fatal("Trying to decode instruction without a class\n");
9897  return nullptr;
9898  }
9899 
9900  GPUStaticInst*
9902  {
9903  fatal("Trying to decode instruction without a class\n");
9904  return nullptr;
9905  }
9906 
9907  GPUStaticInst*
9909  {
9910  fatal("Trying to decode instruction without a class\n");
9911  return nullptr;
9912  }
9913 
9914  GPUStaticInst*
9916  {
9917  fatal("Trying to decode instruction without a class\n");
9918  return nullptr;
9919  }
9920 
9921  GPUStaticInst*
9923  {
9924  fatal("Trying to decode instruction without a class\n");
9925  return nullptr;
9926  }
9927 
9928  GPUStaticInst*
9930  {
9931  return new Inst_SMEM__S_LOAD_DWORD(&iFmt->iFmt_SMEM);
9932  } // decode_OP_SMEM__S_LOAD_DWORD
9933 
9934  GPUStaticInst*
9936  {
9937  return new Inst_SMEM__S_LOAD_DWORDX2(&iFmt->iFmt_SMEM);
9938  } // decode_OP_SMEM__S_LOAD_DWORDX2
9939 
9940  GPUStaticInst*
9942  {
9943  return new Inst_SMEM__S_LOAD_DWORDX4(&iFmt->iFmt_SMEM);
9944  } // decode_OP_SMEM__S_LOAD_DWORDX4
9945 
9946  GPUStaticInst*
9948  {
9949  return new Inst_SMEM__S_LOAD_DWORDX8(&iFmt->iFmt_SMEM);
9950  } // decode_OP_SMEM__S_LOAD_DWORDX8
9951 
9952  GPUStaticInst*
9954  {
9955  return new Inst_SMEM__S_LOAD_DWORDX16(&iFmt->iFmt_SMEM);
9956  } // decode_OP_SMEM__S_LOAD_DWORDX16
9957 
9958  GPUStaticInst*
9960  {
9961  fatal("Trying to decode instruction without a class\n");
9962  return nullptr;
9963  }
9964 
9965  GPUStaticInst*
9967  {
9968  fatal("Trying to decode instruction without a class\n");
9969  return nullptr;
9970  }
9971 
9972  GPUStaticInst*
9974  {
9975  fatal("Trying to decode instruction without a class\n");
9976  return nullptr;
9977  }
9978 
9979  GPUStaticInst*
9981  {
9982  return new Inst_SMEM__S_BUFFER_LOAD_DWORD(&iFmt->iFmt_SMEM);
9983  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORD
9984 
9985  GPUStaticInst*
9987  {
9988  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX2(&iFmt->iFmt_SMEM);
9989  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2
9990 
9991  GPUStaticInst*
9993  {
9994  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX4(&iFmt->iFmt_SMEM);
9995  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4
9996 
9997  GPUStaticInst*
9999  {
10000  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX8(&iFmt->iFmt_SMEM);
10001  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8
10002 
10003  GPUStaticInst*
10005  {
10006  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX16(&iFmt->iFmt_SMEM);
10007  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16
10008 
10009  GPUStaticInst*
10011  {
10012  return new Inst_SMEM__S_STORE_DWORD(&iFmt->iFmt_SMEM);
10013  } // decode_OP_SMEM__S_STORE_DWORD
10014 
10015  GPUStaticInst*
10017  {
10018  return new Inst_SMEM__S_STORE_DWORDX2(&iFmt->iFmt_SMEM);
10019  } // decode_OP_SMEM__S_STORE_DWORDX2
10020 
10021  GPUStaticInst*
10023  {
10024  return new Inst_SMEM__S_STORE_DWORDX4(&iFmt->iFmt_SMEM);
10025  } // decode_OP_SMEM__S_STORE_DWORDX4
10026 
10027  GPUStaticInst*
10029  {
10030  fatal("Trying to decode instruction without a class\n");
10031  return nullptr;
10032  }
10033 
10034  GPUStaticInst*
10036  {
10037  fatal("Trying to decode instruction without a class\n");
10038  return nullptr;
10039  }
10040 
10041  GPUStaticInst*
10043  {
10044  fatal("Trying to decode instruction without a class\n");
10045  return nullptr;
10046  }
10047 
10048  GPUStaticInst*
10050  {
10051  return new Inst_SMEM__S_BUFFER_STORE_DWORD(&iFmt->iFmt_SMEM);
10052  } // decode_OP_SMEM__S_BUFFER_STORE_DWORD
10053 
10054  GPUStaticInst*
10056  {
10057  return new Inst_SMEM__S_BUFFER_STORE_DWORDX2(&iFmt->iFmt_SMEM);
10058  } // decode_OP_SMEM__S_BUFFER_STORE_DWORDX2
10059 
10060  GPUStaticInst*
10062  {
10063  return new Inst_SMEM__S_BUFFER_STORE_DWORDX4(&iFmt->iFmt_SMEM);
10064  } // decode_OP_SMEM__S_BUFFER_STORE_DWORDX4
10065 
10066  GPUStaticInst*
10068  {
10069  fatal("Trying to decode instruction without a class\n");
10070  return nullptr;
10071  }
10072  GPUStaticInst*
10074  {
10075  fatal("Trying to decode instruction without a class\n");
10076  return nullptr;
10077  }
10078  GPUStaticInst*
10080  {
10081  fatal("Trying to decode instruction without a class\n");
10082  return nullptr;
10083  }
10084  GPUStaticInst*
10086  {
10087  fatal("Trying to decode instruction without a class\n");
10088  return nullptr;
10089  }
10090  GPUStaticInst*
10092  {
10093  fatal("Trying to decode instruction without a class\n");
10094  return nullptr;
10095  }
10096  GPUStaticInst*
10098  {
10099  fatal("Trying to decode instruction without a class\n");
10100  return nullptr;
10101  }
10102  GPUStaticInst*
10104  {
10105  fatal("Trying to decode instruction without a class\n");
10106  return nullptr;
10107  }
10108  GPUStaticInst*
10110  {
10111  fatal("Trying to decode instruction without a class\n");
10112  return nullptr;
10113  }
10114 
10115  GPUStaticInst*
10117  {
10118  return new Inst_SMEM__S_DCACHE_INV(&iFmt->iFmt_SMEM);
10119  } // decode_OP_SMEM__S_DCACHE_INV
10120 
10121  GPUStaticInst*
10123  {
10124  return new Inst_SMEM__S_DCACHE_WB(&iFmt->iFmt_SMEM);
10125  } // decode_OP_SMEM__S_DCACHE_WB
10126 
10127  GPUStaticInst*
10129  {
10130  return new Inst_SMEM__S_DCACHE_INV_VOL(&iFmt->iFmt_SMEM);
10131  } // decode_OP_SMEM__S_DCACHE_INV_VOL
10132 
10133  GPUStaticInst*
10135  {
10136  return new Inst_SMEM__S_DCACHE_WB_VOL(&iFmt->iFmt_SMEM);
10137  } // decode_OP_SMEM__S_DCACHE_WB_VOL
10138 
10139  GPUStaticInst*
10141  {
10142  return new Inst_SMEM__S_MEMTIME(&iFmt->iFmt_SMEM);
10143  } // decode_OP_SMEM__S_MEMTIME
10144 
10145  GPUStaticInst*
10147  {
10148  return new Inst_SMEM__S_MEMREALTIME(&iFmt->iFmt_SMEM);
10149  } // decode_OP_SMEM__S_MEMREALTIME
10150 
10151  GPUStaticInst*
10153  {
10154  return new Inst_SMEM__S_ATC_PROBE(&iFmt->iFmt_SMEM);
10155  } // decode_OP_SMEM__S_ATC_PROBE
10156 
10157  GPUStaticInst*
10159  {
10160  return new Inst_SMEM__S_ATC_PROBE_BUFFER(&iFmt->iFmt_SMEM);
10161  } // decode_OP_SMEM__S_ATC_PROBE_BUFFER
10162 
10163  GPUStaticInst*
10165  {
10166  fatal("Trying to decode instruction without a class\n");
10167  return nullptr;
10168  }
10169 
10170  GPUStaticInst*
10172  {
10173  fatal("Trying to decode instruction without a class\n");
10174  return nullptr;
10175  }
10176 
10177  GPUStaticInst*
10179  {
10180  fatal("Trying to decode instruction without a class\n");
10181  return nullptr;
10182  }
10183 
10184  GPUStaticInst*
10186  {
10187  fatal("Trying to decode instruction without a class\n");
10188  return nullptr;
10189  }
10190 
10191  GPUStaticInst*
10193  {
10194  fatal("Trying to decode instruction without a class\n");
10195  return nullptr;
10196  }
10197 
10198  GPUStaticInst*
10200  {
10201  fatal("Trying to decode instruction without a class\n");
10202  return nullptr;
10203  }
10204 
10205  GPUStaticInst*
10207  {
10208  fatal("Trying to decode instruction without a class\n");
10209  return nullptr;
10210  }
10211 
10212  GPUStaticInst*
10214  {
10215  fatal("Trying to decode instruction without a class\n");
10216  return nullptr;
10217  }
10218 
10219  GPUStaticInst*
10221  {
10222  fatal("Trying to decode instruction without a class\n");
10223  return nullptr;
10224  }
10225 
10226  GPUStaticInst*
10228  {
10229  fatal("Trying to decode instruction without a class\n");
10230  return nullptr;
10231  }
10232 
10233  GPUStaticInst*
10235  {
10236  fatal("Trying to decode instruction without a class\n");
10237  return nullptr;
10238  }
10239 
10240  GPUStaticInst*
10242  {
10243  fatal("Trying to decode instruction without a class\n");
10244  return nullptr;
10245  }
10246 
10247  GPUStaticInst*
10249  {
10250  fatal("Trying to decode instruction without a class\n");
10251  return nullptr;
10252  }
10253 
10254  GPUStaticInst*
10256  {
10257  fatal("Trying to decode instruction without a class\n");
10258  return nullptr;
10259  }
10260 
10261  GPUStaticInst*
10263  {
10264  fatal("Trying to decode instruction without a class\n");
10265  return nullptr;
10266  }
10267 
10268  GPUStaticInst*
10270  {
10271  fatal("Trying to decode instruction without a class\n");
10272  return nullptr;
10273  }
10274 
10275  GPUStaticInst*
10277  {
10278  fatal("Trying to decode instruction without a class\n");
10279  return nullptr;
10280  }
10281 
10282  GPUStaticInst*
10284  {
10285  fatal("Trying to decode instruction without a class\n");
10286  return nullptr;
10287  }
10288 
10289  GPUStaticInst*
10291  {
10292  fatal("Trying to decode instruction without a class\n");
10293  return nullptr;
10294  }
10295 
10296  GPUStaticInst*
10298  {
10299  fatal("Trying to decode instruction without a class\n");
10300  return nullptr;
10301  }
10302 
10303  GPUStaticInst*
10305  {
10306  fatal("Trying to decode instruction without a class\n");
10307  return nullptr;
10308  }
10309 
10310  GPUStaticInst*
10312  {
10313  fatal("Trying to decode instruction without a class\n");
10314  return nullptr;
10315  }
10316 
10317  GPUStaticInst*
10319  {
10320  fatal("Trying to decode instruction without a class\n");
10321  return nullptr;
10322  }
10323 
10324  GPUStaticInst*
10326  {
10327  fatal("Trying to decode instruction without a class\n");
10328  return nullptr;
10329  }
10330 
10331  GPUStaticInst*
10333  {
10334  fatal("Trying to decode instruction without a class\n");
10335  return nullptr;
10336  }
10337 
10338  GPUStaticInst*
10340  {
10341  fatal("Trying to decode instruction without a class\n");
10342  return nullptr;
10343  }
10344 
10345  GPUStaticInst*
10347  {
10348  fatal("Trying to decode instruction without a class\n");
10349  return nullptr;
10350  }
10351 
10352  GPUStaticInst*
10354  {
10355  fatal("Trying to decode instruction without a class\n");
10356  return nullptr;
10357  }
10358 
10359  GPUStaticInst*
10361  {
10362  fatal("Trying to decode instruction without a class\n");
10363  return nullptr;
10364  }
10365 
10366  GPUStaticInst*
10368  {
10369  fatal("Trying to decode instruction without a class\n");
10370  return nullptr;
10371  }
10372 
10373  GPUStaticInst*
10375  {
10376  fatal("Trying to decode instruction without a class\n");
10377  return nullptr;
10378  }
10379 
10380  GPUStaticInst*
10382  {
10383  fatal("Trying to decode instruction without a class\n");
10384  return nullptr;
10385  }
10386 
10387  GPUStaticInst*
10389  {
10390  fatal("Trying to decode instruction without a class\n");
10391  return nullptr;
10392  }
10393 
10394  GPUStaticInst*
10396  {
10397  fatal("Trying to decode instruction without a class\n");
10398  return nullptr;
10399  }
10400 
10401  GPUStaticInst*
10403  {
10404  fatal("Trying to decode instruction without a class\n");
10405  return nullptr;
10406  }
10407 
10408  GPUStaticInst*
10410  {
10411  fatal("Trying to decode instruction without a class\n");
10412  return nullptr;
10413  }
10414 
10415  GPUStaticInst*
10417  {
10418  fatal("Trying to decode instruction without a class\n");
10419  return nullptr;
10420  }
10421 
10422  GPUStaticInst*
10424  {
10425  fatal("Trying to decode instruction without a class\n");
10426  return nullptr;
10427  }
10428 
10429  GPUStaticInst*
10431  {
10432  fatal("Trying to decode instruction without a class\n");
10433  return nullptr;
10434  }
10435 
10436  GPUStaticInst*
10438  {
10439  fatal("Trying to decode instruction without a class\n");
10440  return nullptr;
10441  }
10442 
10443  GPUStaticInst*
10445  {
10446  fatal("Trying to decode instruction without a class\n");
10447  return nullptr;
10448  }
10449 
10450  GPUStaticInst*
10452  {
10453  fatal("Trying to decode instruction without a class\n");
10454  return nullptr;
10455  }
10456 
10457  GPUStaticInst*
10459  {
10460  fatal("Trying to decode instruction without a class\n");
10461  return nullptr;
10462  }
10463 
10464  GPUStaticInst*
10466  {
10467  fatal("Trying to decode instruction without a class\n");
10468  return nullptr;
10469  }
10470 
10471  GPUStaticInst*
10473  {
10474  fatal("Trying to decode instruction without a class\n");
10475  return nullptr;
10476  }
10477 
10478  GPUStaticInst*
10480  {
10481  fatal("Trying to decode instruction without a class\n");
10482  return nullptr;
10483  }
10484 
10485  GPUStaticInst*
10487  {
10488  fatal("Trying to decode instruction without a class\n");
10489  return nullptr;
10490  }
10491 
10492  GPUStaticInst*
10494  {
10495  fatal("Trying to decode instruction without a class\n");
10496  return nullptr;
10497  }
10498 
10499  GPUStaticInst*
10501  {
10502  fatal("Trying to decode instruction without a class\n");
10503  return nullptr;
10504  }
10505 
10506  GPUStaticInst*
10508  {
10509  fatal("Trying to decode instruction without a class\n");
10510  return nullptr;
10511  }
10512 
10513  GPUStaticInst*
10515  {
10516  fatal("Trying to decode instruction without a class\n");
10517  return nullptr;
10518  }
10519 
10520  GPUStaticInst*
10522  {
10523  fatal("Trying to decode instruction without a class\n");
10524  return nullptr;
10525  }
10526 
10527  GPUStaticInst*
10529  {
10530  fatal("Trying to decode instruction without a class\n");
10531  return nullptr;
10532  }
10533 
10534  GPUStaticInst*
10536  {
10537  fatal("Trying to decode instruction without a class\n");
10538  return nullptr;
10539  }
10540 
10541  GPUStaticInst*
10543  {
10544  return new Inst_SOP1__S_MOV_B32(&iFmt->iFmt_SOP1);
10545  } // decode_OP_SOP1__S_MOV_B32
10546 
10547  GPUStaticInst*
10549  {
10550  return new Inst_SOP1__S_MOV_B64(&iFmt->iFmt_SOP1);
10551  } // decode_OP_SOP1__S_MOV_B64
10552 
10553  GPUStaticInst*
10555  {
10556  return new Inst_SOP1__S_CMOV_B32(&iFmt->iFmt_SOP1);
10557  } // decode_OP_SOP1__S_CMOV_B32
10558 
10559  GPUStaticInst*
10561  {
10562  return new Inst_SOP1__S_CMOV_B64(&iFmt->iFmt_SOP1);
10563  } // decode_OP_SOP1__S_CMOV_B64
10564 
10565  GPUStaticInst*
10567  {
10568  return new Inst_SOP1__S_NOT_B32(&iFmt->iFmt_SOP1);
10569  } // decode_OP_SOP1__S_NOT_B32
10570 
10571  GPUStaticInst*
10573  {
10574  return new Inst_SOP1__S_NOT_B64(&iFmt->iFmt_SOP1);
10575  } // decode_OP_SOP1__S_NOT_B64
10576 
10577  GPUStaticInst*
10579  {
10580  return new Inst_SOP1__S_WQM_B32(&iFmt->iFmt_SOP1);
10581  } // decode_OP_SOP1__S_WQM_B32
10582 
10583  GPUStaticInst*
10585  {
10586  return new Inst_SOP1__S_WQM_B64(&iFmt->iFmt_SOP1);
10587  } // decode_OP_SOP1__S_WQM_B64
10588 
10589  GPUStaticInst*
10591  {
10592  return new Inst_SOP1__S_BREV_B32(&iFmt->iFmt_SOP1);
10593  } // decode_OP_SOP1__S_BREV_B32
10594 
10595  GPUStaticInst*
10597  {
10598  return new Inst_SOP1__S_BREV_B64(&iFmt->iFmt_SOP1);
10599  } // decode_OP_SOP1__S_BREV_B64
10600 
10601  GPUStaticInst*
10603  {
10604  return new Inst_SOP1__S_BCNT0_I32_B32(&iFmt->iFmt_SOP1);
10605  } // decode_OP_SOP1__S_BCNT0_I32_B32
10606 
10607  GPUStaticInst*
10609  {
10610  return new Inst_SOP1__S_BCNT0_I32_B64(&iFmt->iFmt_SOP1);
10611  } // decode_OP_SOP1__S_BCNT0_I32_B64
10612 
10613  GPUStaticInst*
10615  {
10616  return new Inst_SOP1__S_BCNT1_I32_B32(&iFmt->iFmt_SOP1);
10617  } // decode_OP_SOP1__S_BCNT1_I32_B32
10618 
10619  GPUStaticInst*
10621  {
10622  return new Inst_SOP1__S_BCNT1_I32_B64(&iFmt->iFmt_SOP1);
10623  } // decode_OP_SOP1__S_BCNT1_I32_B64
10624 
10625  GPUStaticInst*
10627  {
10628  return new Inst_SOP1__S_FF0_I32_B32(&iFmt->iFmt_SOP1);
10629  } // decode_OP_SOP1__S_FF0_I32_B32
10630 
10631  GPUStaticInst*
10633  {
10634  return new Inst_SOP1__S_FF0_I32_B64(&iFmt->iFmt_SOP1);
10635  } // decode_OP_SOP1__S_FF0_I32_B64
10636 
10637  GPUStaticInst*
10639  {
10640  return new Inst_SOP1__S_FF1_I32_B32(&iFmt->iFmt_SOP1);
10641  } // decode_OP_SOP1__S_FF1_I32_B32
10642 
10643  GPUStaticInst*
10645  {
10646  return new Inst_SOP1__S_FF1_I32_B64(&iFmt->iFmt_SOP1);
10647  } // decode_OP_SOP1__S_FF1_I32_B64
10648 
10649  GPUStaticInst*
10651  {
10652  return new Inst_SOP1__S_FLBIT_I32_B32(&iFmt->iFmt_SOP1);
10653  } // decode_OP_SOP1__S_FLBIT_I32_B32
10654 
10655  GPUStaticInst*
10657  {
10658  return new Inst_SOP1__S_FLBIT_I32_B64(&iFmt->iFmt_SOP1);
10659  } // decode_OP_SOP1__S_FLBIT_I32_B64
10660 
10661  GPUStaticInst*
10663  {
10664  return new Inst_SOP1__S_FLBIT_I32(&iFmt->iFmt_SOP1);
10665  } // decode_OP_SOP1__S_FLBIT_I32
10666 
10667  GPUStaticInst*
10669  {
10670  return new Inst_SOP1__S_FLBIT_I32_I64(&iFmt->iFmt_SOP1);
10671  } // decode_OP_SOP1__S_FLBIT_I32_I64
10672 
10673  GPUStaticInst*
10675  {
10676  return new Inst_SOP1__S_SEXT_I32_I8(&iFmt->iFmt_SOP1);
10677  } // decode_OP_SOP1__S_SEXT_I32_I8
10678 
10679  GPUStaticInst*
10681  {
10682  return new Inst_SOP1__S_SEXT_I32_I16(&iFmt->iFmt_SOP1);
10683  } // decode_OP_SOP1__S_SEXT_I32_I16
10684 
10685  GPUStaticInst*
10687  {
10688  return new Inst_SOP1__S_BITSET0_B32(&iFmt->iFmt_SOP1);
10689  } // decode_OP_SOP1__S_BITSET0_B32
10690 
10691  GPUStaticInst*
10693  {
10694  return new Inst_SOP1__S_BITSET0_B64(&iFmt->iFmt_SOP1);
10695  } // decode_OP_SOP1__S_BITSET0_B64
10696 
10697  GPUStaticInst*
10699  {
10700  return new Inst_SOP1__S_BITSET1_B32(&iFmt->iFmt_SOP1);
10701  } // decode_OP_SOP1__S_BITSET1_B32
10702 
10703  GPUStaticInst*
10705  {
10706  return new Inst_SOP1__S_BITSET1_B64(&iFmt->iFmt_SOP1);
10707  } // decode_OP_SOP1__S_BITSET1_B64
10708 
10709  GPUStaticInst*
10711  {
10712  return new Inst_SOP1__S_GETPC_B64(&iFmt->iFmt_SOP1);
10713  } // decode_OP_SOP1__S_GETPC_B64
10714 
10715  GPUStaticInst*
10717  {
10718  return new Inst_SOP1__S_SETPC_B64(&iFmt->iFmt_SOP1);
10719  } // decode_OP_SOP1__S_SETPC_B64
10720 
10721  GPUStaticInst*
10723  {
10724  return new Inst_SOP1__S_SWAPPC_B64(&iFmt->iFmt_SOP1);
10725  } // decode_OP_SOP1__S_SWAPPC_B64
10726 
10727  GPUStaticInst*
10729  {
10730  return new Inst_SOP1__S_RFE_B64(&iFmt->iFmt_SOP1);
10731  } // decode_OP_SOP1__S_RFE_B64
10732 
10733  GPUStaticInst*
10735  {
10736  return new Inst_SOP1__S_AND_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10737  } // decode_OP_SOP1__S_AND_SAVEEXEC_B64
10738 
10739  GPUStaticInst*
10741  {
10742  return new Inst_SOP1__S_OR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10743  } // decode_OP_SOP1__S_OR_SAVEEXEC_B64
10744 
10745  GPUStaticInst*
10747  {
10748  return new Inst_SOP1__S_XOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10749  } // decode_OP_SOP1__S_XOR_SAVEEXEC_B64
10750 
10751  GPUStaticInst*
10753  {
10754  return new Inst_SOP1__S_ANDN2_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10755  } // decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64
10756 
10757  GPUStaticInst*
10759  {
10760  return new Inst_SOP1__S_ORN2_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10761  } // decode_OP_SOP1__S_ORN2_SAVEEXEC_B64
10762 
10763  GPUStaticInst*
10765  {
10766  return new Inst_SOP1__S_NAND_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10767  } // decode_OP_SOP1__S_NAND_SAVEEXEC_B64
10768 
10769  GPUStaticInst*
10771  {
10772  return new Inst_SOP1__S_NOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10773  } // decode_OP_SOP1__S_NOR_SAVEEXEC_B64
10774 
10775  GPUStaticInst*
10777  {
10778  return new Inst_SOP1__S_XNOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10779  } // decode_OP_SOP1__S_XNOR_SAVEEXEC_B64
10780 
10781  GPUStaticInst*
10783  {
10784  return new Inst_SOP1__S_QUADMASK_B32(&iFmt->iFmt_SOP1);
10785  } // decode_OP_SOP1__S_QUADMASK_B32
10786 
10787  GPUStaticInst*
10789  {
10790  return new Inst_SOP1__S_QUADMASK_B64(&iFmt->iFmt_SOP1);
10791  } // decode_OP_SOP1__S_QUADMASK_B64
10792 
10793  GPUStaticInst*
10795  {
10796  return new Inst_SOP1__S_MOVRELS_B32(&iFmt->iFmt_SOP1);
10797  } // decode_OP_SOP1__S_MOVRELS_B32
10798 
10799  GPUStaticInst*
10801  {
10802  return new Inst_SOP1__S_MOVRELS_B64(&iFmt->iFmt_SOP1);
10803  } // decode_OP_SOP1__S_MOVRELS_B64
10804 
10805  GPUStaticInst*
10807  {
10808  return new Inst_SOP1__S_MOVRELD_B32(&iFmt->iFmt_SOP1);
10809  } // decode_OP_SOP1__S_MOVRELD_B32
10810 
10811  GPUStaticInst*
10813  {
10814  return new Inst_SOP1__S_MOVRELD_B64(&iFmt->iFmt_SOP1);
10815  } // decode_OP_SOP1__S_MOVRELD_B64
10816 
10817  GPUStaticInst*
10819  {
10820  return new Inst_SOP1__S_CBRANCH_JOIN(&iFmt->iFmt_SOP1);
10821  } // decode_OP_SOP1__S_CBRANCH_JOIN
10822 
10823  GPUStaticInst*
10825  {
10826  return new Inst_SOP1__S_ABS_I32(&iFmt->iFmt_SOP1);
10827  } // decode_OP_SOP1__S_ABS_I32
10828 
10829  GPUStaticInst*
10831  {
10832  return new Inst_SOP1__S_SET_GPR_IDX_IDX(&iFmt->iFmt_SOP1);
10833  } // decode_OP_SOP1__S_SET_GPR_IDX_IDX
10834 
10835  GPUStaticInst*
10837  {
10838  fatal("Trying to decode instruction without a class\n");
10839  return nullptr;
10840  }
10841 
10842  GPUStaticInst*
10844  {
10845  fatal("Trying to decode instruction without a class\n");
10846  return nullptr;
10847  }
10848 
10849  GPUStaticInst*
10851  {
10852  fatal("Trying to decode instruction without a class\n");
10853  return nullptr;
10854  }
10855 
10856  GPUStaticInst*
10858  {
10859  fatal("Trying to decode instruction without a class\n");
10860  return nullptr;
10861  }
10862 
10863  GPUStaticInst*
10865  {
10866  fatal("Trying to decode instruction without a class\n");
10867  return nullptr;
10868  }
10869 
10870  GPUStaticInst*
10872  {
10873  return new Inst_SOPC__S_CMP_EQ_I32(&iFmt->iFmt_SOPC);
10874  } // decode_OP_SOPC__S_CMP_EQ_I32
10875 
10876  GPUStaticInst*
10878  {
10879  return new Inst_SOPC__S_CMP_LG_I32(&iFmt->iFmt_SOPC);
10880  } // decode_OP_SOPC__S_CMP_LG_I32
10881 
10882  GPUStaticInst*
10884  {
10885  return new Inst_SOPC__S_CMP_GT_I32(&iFmt->iFmt_SOPC);
10886  } // decode_OP_SOPC__S_CMP_GT_I32
10887 
10888  GPUStaticInst*
10890  {
10891  return new Inst_SOPC__S_CMP_GE_I32(&iFmt->iFmt_SOPC);
10892  } // decode_OP_SOPC__S_CMP_GE_I32
10893 
10894  GPUStaticInst*
10896  {
10897  return new Inst_SOPC__S_CMP_LT_I32(&iFmt->iFmt_SOPC);
10898  } // decode_OP_SOPC__S_CMP_LT_I32
10899 
10900  GPUStaticInst*
10902  {
10903  return new Inst_SOPC__S_CMP_LE_I32(&iFmt->iFmt_SOPC);
10904  } // decode_OP_SOPC__S_CMP_LE_I32
10905 
10906  GPUStaticInst*
10908  {
10909  return new Inst_SOPC__S_CMP_EQ_U32(&iFmt->iFmt_SOPC);
10910  } // decode_OP_SOPC__S_CMP_EQ_U32
10911 
10912  GPUStaticInst*
10914  {
10915  return new Inst_SOPC__S_CMP_LG_U32(&iFmt->iFmt_SOPC);
10916  } // decode_OP_SOPC__S_CMP_LG_U32
10917 
10918  GPUStaticInst*
10920  {
10921  return new Inst_SOPC__S_CMP_GT_U32(&iFmt->iFmt_SOPC);
10922  } // decode_OP_SOPC__S_CMP_GT_U32
10923 
10924  GPUStaticInst*
10926  {
10927  return new Inst_SOPC__S_CMP_GE_U32(&iFmt->iFmt_SOPC);
10928  } // decode_OP_SOPC__S_CMP_GE_U32
10929 
10930  GPUStaticInst*
10932  {
10933  return new Inst_SOPC__S_CMP_LT_U32(&iFmt->iFmt_SOPC);
10934  } // decode_OP_SOPC__S_CMP_LT_U32
10935 
10936  GPUStaticInst*
10938  {
10939  return new Inst_SOPC__S_CMP_LE_U32(&iFmt->iFmt_SOPC);
10940  } // decode_OP_SOPC__S_CMP_LE_U32
10941 
10942  GPUStaticInst*
10944  {
10945  return new Inst_SOPC__S_BITCMP0_B32(&iFmt->iFmt_SOPC);
10946  } // decode_OP_SOPC__S_BITCMP0_B32
10947 
10948  GPUStaticInst*
10950  {
10951  return new Inst_SOPC__S_BITCMP1_B32(&iFmt->iFmt_SOPC);
10952  } // decode_OP_SOPC__S_BITCMP1_B32
10953 
10954  GPUStaticInst*
10956  {
10957  return new Inst_SOPC__S_BITCMP0_B64(&iFmt->iFmt_SOPC);
10958  } // decode_OP_SOPC__S_BITCMP0_B64
10959 
10960  GPUStaticInst*
10962  {
10963  return new Inst_SOPC__S_BITCMP1_B64(&iFmt->iFmt_SOPC);
10964  } // decode_OP_SOPC__S_BITCMP1_B64
10965 
10966  GPUStaticInst*
10968  {
10969  return new Inst_SOPC__S_SETVSKIP(&iFmt->iFmt_SOPC);
10970  } // decode_OP_SOPC__S_SETVSKIP
10971 
10972  GPUStaticInst*
10974  {
10975  return new Inst_SOPC__S_SET_GPR_IDX_ON(&iFmt->iFmt_SOPC);
10976  } // decode_OP_SOPC__S_SET_GPR_IDX_ON
10977 
10978  GPUStaticInst*
10980  {
10981  return new Inst_SOPC__S_CMP_EQ_U64(&iFmt->iFmt_SOPC);
10982  } // decode_OP_SOPC__S_CMP_EQ_U64
10983 
10984  GPUStaticInst*
10986  {
10987  return new Inst_SOPC__S_CMP_LG_U64(&iFmt->iFmt_SOPC);
10988  } // decode_OP_SOPC__S_CMP_LG_U64
10989 
10990  GPUStaticInst*
10992  {
10993  return new Inst_SOPP__S_NOP(&iFmt->iFmt_SOPP);
10994  } // decode_OP_SOPP__S_NOP
10995 
10996  GPUStaticInst*
10998  {
10999  return new Inst_SOPP__S_ENDPGM(&iFmt->iFmt_SOPP);
11000  } // decode_OP_SOPP__S_ENDPGM
11001 
11002  GPUStaticInst*
11004  {
11005  return new Inst_SOPP__S_BRANCH(&iFmt->iFmt_SOPP);
11006  } // decode_OP_SOPP__S_BRANCH
11007 
11008  GPUStaticInst*
11010  {
11011  return new Inst_SOPP__S_WAKEUP(&iFmt->iFmt_SOPP);
11012  } // decode_OP_SOPP__S_WAKEUP
11013 
11014  GPUStaticInst*
11016  {
11017  return new Inst_SOPP__S_CBRANCH_SCC0(&iFmt->iFmt_SOPP);
11018  } // decode_OP_SOPP__S_CBRANCH_SCC0
11019 
11020  GPUStaticInst*
11022  {
11023  return new Inst_SOPP__S_CBRANCH_SCC1(&iFmt->iFmt_SOPP);
11024  } // decode_OP_SOPP__S_CBRANCH_SCC1
11025 
11026  GPUStaticInst*
11028  {
11029  return new Inst_SOPP__S_CBRANCH_VCCZ(&iFmt->iFmt_SOPP);
11030  } // decode_OP_SOPP__S_CBRANCH_VCCZ
11031 
11032  GPUStaticInst*
11034  {
11035  return new Inst_SOPP__S_CBRANCH_VCCNZ(&iFmt->iFmt_SOPP);
11036  } // decode_OP_SOPP__S_CBRANCH_VCCNZ
11037 
11038  GPUStaticInst*
11040  {
11041  return new Inst_SOPP__S_CBRANCH_EXECZ(&iFmt->iFmt_SOPP);
11042  } // decode_OP_SOPP__S_CBRANCH_EXECZ
11043 
11044  GPUStaticInst*
11046  {
11047  return new Inst_SOPP__S_CBRANCH_EXECNZ(&iFmt->iFmt_SOPP);
11048  } // decode_OP_SOPP__S_CBRANCH_EXECNZ
11049 
11050  GPUStaticInst*
11052  {
11053  return new Inst_SOPP__S_BARRIER(&iFmt->iFmt_SOPP);
11054  } // decode_OP_SOPP__S_BARRIER
11055 
11056  GPUStaticInst*
11058  {
11059  return new Inst_SOPP__S_SETKILL(&iFmt->iFmt_SOPP);
11060  } // decode_OP_SOPP__S_SETKILL
11061 
11062  GPUStaticInst*
11064  {
11065  return new Inst_SOPP__S_WAITCNT(&iFmt->iFmt_SOPP);
11066  } // decode_OP_SOPP__S_WAITCNT
11067 
11068  GPUStaticInst*
11070  {
11071  return new Inst_SOPP__S_SETHALT(&iFmt->iFmt_SOPP);
11072  } // decode_OP_SOPP__S_SETHALT
11073 
11074  GPUStaticInst*
11076  {
11077  return new Inst_SOPP__S_SLEEP(&iFmt->iFmt_SOPP);
11078  } // decode_OP_SOPP__S_SLEEP
11079 
11080  GPUStaticInst*
11082  {
11083  return new Inst_SOPP__S_SETPRIO(&iFmt->iFmt_SOPP);
11084  } // decode_OP_SOPP__S_SETPRIO
11085 
11086  GPUStaticInst*
11088  {
11089  return new Inst_SOPP__S_SENDMSG(&iFmt->iFmt_SOPP);
11090  } // decode_OP_SOPP__S_SENDMSG
11091 
11092  GPUStaticInst*
11094  {
11095  return new Inst_SOPP__S_SENDMSGHALT(&iFmt->iFmt_SOPP);
11096  } // decode_OP_SOPP__S_SENDMSGHALT
11097 
11098  GPUStaticInst*
11100  {
11101  return new Inst_SOPP__S_TRAP(&iFmt->iFmt_SOPP);
11102  } // decode_OP_SOPP__S_TRAP
11103 
11104  GPUStaticInst*
11106  {
11107  return new Inst_SOPP__S_ICACHE_INV(&iFmt->iFmt_SOPP);
11108  } // decode_OP_SOPP__S_ICACHE_INV
11109 
11110  GPUStaticInst*
11112  {
11113  return new Inst_SOPP__S_INCPERFLEVEL(&iFmt->iFmt_SOPP);
11114  } // decode_OP_SOPP__S_INCPERFLEVEL
11115 
11116  GPUStaticInst*
11118  {
11119  return new Inst_SOPP__S_DECPERFLEVEL(&iFmt->iFmt_SOPP);
11120  } // decode_OP_SOPP__S_DECPERFLEVEL
11121 
11122  GPUStaticInst*
11124  {
11125  return new Inst_SOPP__S_TTRACEDATA(&iFmt->iFmt_SOPP);
11126  } // decode_OP_SOPP__S_TTRACEDATA
11127 
11128  GPUStaticInst*
11130  {
11131  return new Inst_SOPP__S_CBRANCH_CDBGSYS(&iFmt->iFmt_SOPP);
11132  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS
11133 
11134  GPUStaticInst*
11136  {
11137  return new Inst_SOPP__S_CBRANCH_CDBGUSER(&iFmt->iFmt_SOPP);
11138  } // decode_OP_SOPP__S_CBRANCH_CDBGUSER
11139 
11140  GPUStaticInst*
11142  {
11144  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER
11145 
11146  GPUStaticInst*
11148  {
11150  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER
11151 
11152  GPUStaticInst*
11154  {
11155  return new Inst_SOPP__S_ENDPGM_SAVED(&iFmt->iFmt_SOPP);
11156  } // decode_OP_SOPP__S_ENDPGM_SAVED
11157 
11158  GPUStaticInst*
11160  {
11161  return new Inst_SOPP__S_SET_GPR_IDX_OFF(&iFmt->iFmt_SOPP);
11162  } // decode_OP_SOPP__S_SET_GPR_IDX_OFF
11163 
11164  GPUStaticInst*
11166  {
11167  return new Inst_SOPP__S_SET_GPR_IDX_MODE(&iFmt->iFmt_SOPP);
11168  } // decode_OP_SOPP__S_SET_GPR_IDX_MODE
11169 
11170  GPUStaticInst*
11172  {
11173  fatal("Trying to decode instruction without a class\n");
11174  return nullptr;
11175  }
11176 
11177  GPUStaticInst*
11179  {
11180  return new Inst_VINTRP__V_INTERP_P1_F32(&iFmt->iFmt_VINTRP);
11181  } // decode_OP_VINTRP__V_INTERP_P1_F32
11182 
11183  GPUStaticInst*
11185  {
11186  return new Inst_VINTRP__V_INTERP_P2_F32(&iFmt->iFmt_VINTRP);
11187  } // decode_OP_VINTRP__V_INTERP_P2_F32
11188 
11189  GPUStaticInst*
11191  {
11192  return new Inst_VINTRP__V_INTERP_MOV_F32(&iFmt->iFmt_VINTRP);
11193  } // decode_OP_VINTRP__V_INTERP_MOV_F32
11194 
11195  GPUStaticInst*
11197  {
11198  return new Inst_VOP1__V_NOP(&iFmt->iFmt_VOP1);
11199  } // decode_OP_VOP1__V_NOP
11200 
11201  GPUStaticInst*
11203  {
11204  return new Inst_VOP1__V_MOV_B32(&iFmt->iFmt_VOP1);
11205  } // decode_OP_VOP1__V_MOV_B32
11206 
11207  GPUStaticInst*
11209  {
11210  return new Inst_VOP1__V_READFIRSTLANE_B32(&iFmt->iFmt_VOP1);
11211  } // decode_OP_VOP1__V_READFIRSTLANE_B32
11212 
11213  GPUStaticInst*
11215  {
11216  return new Inst_VOP1__V_CVT_I32_F64(&iFmt->iFmt_VOP1);
11217  } // decode_OP_VOP1__V_CVT_I32_F64
11218 
11219  GPUStaticInst*
11221  {
11222  return new Inst_VOP1__V_CVT_F64_I32(&iFmt->iFmt_VOP1);
11223  } // decode_OP_VOP1__V_CVT_F64_I32
11224 
11225  GPUStaticInst*
11227  {
11228  return new Inst_VOP1__V_CVT_F32_I32(&iFmt->iFmt_VOP1);
11229  } // decode_OP_VOP1__V_CVT_F32_I32
11230 
11231  GPUStaticInst*
11233  {
11234  return new Inst_VOP1__V_CVT_F32_U32(&iFmt->iFmt_VOP1);
11235  } // decode_OP_VOP1__V_CVT_F32_U32
11236 
11237  GPUStaticInst*
11239  {
11240  return new Inst_VOP1__V_CVT_U32_F32(&iFmt->iFmt_VOP1);
11241  } // decode_OP_VOP1__V_CVT_U32_F32
11242 
11243  GPUStaticInst*
11245  {
11246  return new Inst_VOP1__V_CVT_I32_F32(&iFmt->iFmt_VOP1);
11247  } // decode_OP_VOP1__V_CVT_I32_F32
11248 
11249  GPUStaticInst*
11251  {
11252  return new Inst_VOP1__V_CVT_F16_F32(&iFmt->iFmt_VOP1);
11253  } // decode_OP_VOP1__V_CVT_F16_F32
11254 
11255  GPUStaticInst*
11257  {
11258  return new Inst_VOP1__V_CVT_F32_F16(&iFmt->iFmt_VOP1);
11259  } // decode_OP_VOP1__V_CVT_F32_F16
11260 
11261  GPUStaticInst*
11263  {
11264  return new Inst_VOP1__V_CVT_RPI_I32_F32(&iFmt->iFmt_VOP1);
11265  } // decode_OP_VOP1__V_CVT_RPI_I32_F32
11266 
11267  GPUStaticInst*
11269  {
11270  return new Inst_VOP1__V_CVT_FLR_I32_F32(&iFmt->iFmt_VOP1);
11271  } // decode_OP_VOP1__V_CVT_FLR_I32_F32
11272 
11273  GPUStaticInst*
11275  {
11276  return new Inst_VOP1__V_CVT_OFF_F32_I4(&iFmt->iFmt_VOP1);
11277  } // decode_OP_VOP1__V_CVT_OFF_F32_I4
11278 
11279  GPUStaticInst*
11281  {
11282  return new Inst_VOP1__V_CVT_F32_F64(&iFmt->iFmt_VOP1);
11283  } // decode_OP_VOP1__V_CVT_F32_F64
11284 
11285  GPUStaticInst*
11287  {
11288  return new Inst_VOP1__V_CVT_F64_F32(&iFmt->iFmt_VOP1);
11289  } // decode_OP_VOP1__V_CVT_F64_F32
11290 
11291  GPUStaticInst*
11293  {
11294  return new Inst_VOP1__V_CVT_F32_UBYTE0(&iFmt->iFmt_VOP1);
11295  } // decode_OP_VOP1__V_CVT_F32_UBYTE0
11296 
11297  GPUStaticInst*
11299  {
11300  return new Inst_VOP1__V_CVT_F32_UBYTE1(&iFmt->iFmt_VOP1);
11301  } // decode_OP_VOP1__V_CVT_F32_UBYTE1
11302 
11303  GPUStaticInst*
11305  {
11306  return new Inst_VOP1__V_CVT_F32_UBYTE2(&iFmt->iFmt_VOP1);
11307  } // decode_OP_VOP1__V_CVT_F32_UBYTE2
11308 
11309  GPUStaticInst*
11311  {
11312  return new Inst_VOP1__V_CVT_F32_UBYTE3(&iFmt->iFmt_VOP1);
11313  } // decode_OP_VOP1__V_CVT_F32_UBYTE3
11314 
11315  GPUStaticInst*
11317  {
11318  return new Inst_VOP1__V_CVT_U32_F64(&iFmt->iFmt_VOP1);
11319  } // decode_OP_VOP1__V_CVT_U32_F64
11320 
11321  GPUStaticInst*
11323  {
11324  return new Inst_VOP1__V_CVT_F64_U32(&iFmt->iFmt_VOP1);
11325  } // decode_OP_VOP1__V_CVT_F64_U32
11326 
11327  GPUStaticInst*
11329  {
11330  return new Inst_VOP1__V_TRUNC_F64(&iFmt->iFmt_VOP1);
11331  } // decode_OP_VOP1__V_TRUNC_F64
11332 
11333  GPUStaticInst*
11335  {
11336  return new Inst_VOP1__V_CEIL_F64(&iFmt->iFmt_VOP1);
11337  } // decode_OP_VOP1__V_CEIL_F64
11338 
11339  GPUStaticInst*
11341  {
11342  return new Inst_VOP1__V_RNDNE_F64(&iFmt->iFmt_VOP1);
11343  } // decode_OP_VOP1__V_RNDNE_F64
11344 
11345  GPUStaticInst*
11347  {
11348  return new Inst_VOP1__V_FLOOR_F64(&iFmt->iFmt_VOP1);
11349  } // decode_OP_VOP1__V_FLOOR_F64
11350 
11351  GPUStaticInst*
11353  {
11354  return new Inst_VOP1__V_FRACT_F32(&iFmt->iFmt_VOP1);
11355  } // decode_OP_VOP1__V_FRACT_F32
11356 
11357  GPUStaticInst*
11359  {
11360  return new Inst_VOP1__V_TRUNC_F32(&iFmt->iFmt_VOP1);
11361  } // decode_OP_VOP1__V_TRUNC_F32
11362 
11363  GPUStaticInst*
11365  {
11366  return new Inst_VOP1__V_CEIL_F32(&iFmt->iFmt_VOP1);
11367  } // decode_OP_VOP1__V_CEIL_F32
11368 
11369  GPUStaticInst*
11371  {
11372  return new Inst_VOP1__V_RNDNE_F32(&iFmt->iFmt_VOP1);
11373  } // decode_OP_VOP1__V_RNDNE_F32
11374 
11375  GPUStaticInst*
11377  {
11378  return new Inst_VOP1__V_FLOOR_F32(&iFmt->iFmt_VOP1);
11379  } // decode_OP_VOP1__V_FLOOR_F32
11380 
11381  GPUStaticInst*
11383  {
11384  return new Inst_VOP1__V_EXP_F32(&iFmt->iFmt_VOP1);
11385  } // decode_OP_VOP1__V_EXP_F32
11386 
11387  GPUStaticInst*
11389  {
11390  return new Inst_VOP1__V_LOG_F32(&iFmt->iFmt_VOP1);
11391  } // decode_OP_VOP1__V_LOG_F32
11392 
11393  GPUStaticInst*
11395  {
11396  return new Inst_VOP1__V_RCP_F32(&iFmt->iFmt_VOP1);
11397  } // decode_OP_VOP1__V_RCP_F32
11398 
11399  GPUStaticInst*
11401  {
11402  return new Inst_VOP1__V_RCP_IFLAG_F32(&iFmt->iFmt_VOP1);
11403  } // decode_OP_VOP1__V_RCP_IFLAG_F32
11404 
11405  GPUStaticInst*
11407  {
11408  return new Inst_VOP1__V_RSQ_F32(&iFmt->iFmt_VOP1);
11409  } // decode_OP_VOP1__V_RSQ_F32
11410 
11411  GPUStaticInst*
11413  {
11414  return new Inst_VOP1__V_RCP_F64(&iFmt->iFmt_VOP1);
11415  } // decode_OP_VOP1__V_RCP_F64
11416 
11417  GPUStaticInst*
11419  {
11420  return new Inst_VOP1__V_RSQ_F64(&iFmt->iFmt_VOP1);
11421  } // decode_OP_VOP1__V_RSQ_F64
11422 
11423  GPUStaticInst*
11425  {
11426  return new Inst_VOP1__V_SQRT_F32(&iFmt->iFmt_VOP1);
11427  } // decode_OP_VOP1__V_SQRT_F32
11428 
11429  GPUStaticInst*
11431  {
11432  return new Inst_VOP1__V_SQRT_F64(&iFmt->iFmt_VOP1);
11433  } // decode_OP_VOP1__V_SQRT_F64
11434 
11435  GPUStaticInst*
11437  {
11438  return new Inst_VOP1__V_SIN_F32(&iFmt->iFmt_VOP1);
11439  } // decode_OP_VOP1__V_SIN_F32
11440 
11441  GPUStaticInst*
11443  {
11444  return new Inst_VOP1__V_COS_F32(&iFmt->iFmt_VOP1);
11445  } // decode_OP_VOP1__V_COS_F32
11446 
11447  GPUStaticInst*
11449  {
11450  return new Inst_VOP1__V_NOT_B32(&iFmt->iFmt_VOP1);
11451  } // decode_OP_VOP1__V_NOT_B32
11452 
11453  GPUStaticInst*
11455  {
11456  return new Inst_VOP1__V_BFREV_B32(&iFmt->iFmt_VOP1);
11457  } // decode_OP_VOP1__V_BFREV_B32
11458 
11459  GPUStaticInst*
11461  {
11462  return new Inst_VOP1__V_FFBH_U32(&iFmt->iFmt_VOP1);
11463  } // decode_OP_VOP1__V_FFBH_U32
11464 
11465  GPUStaticInst*
11467  {
11468  return new Inst_VOP1__V_FFBL_B32(&iFmt->iFmt_VOP1);
11469  } // decode_OP_VOP1__V_FFBL_B32
11470 
11471  GPUStaticInst*
11473  {
11474  return new Inst_VOP1__V_FFBH_I32(&iFmt->iFmt_VOP1);
11475  } // decode_OP_VOP1__V_FFBH_I32
11476 
11477  GPUStaticInst*
11479  {
11480  return new Inst_VOP1__V_FREXP_EXP_I32_F64(&iFmt->iFmt_VOP1);
11481  } // decode_OP_VOP1__V_FREXP_EXP_I32_F64
11482 
11483  GPUStaticInst*
11485  {
11486  return new Inst_VOP1__V_FREXP_MANT_F64(&iFmt->iFmt_VOP1);
11487  } // decode_OP_VOP1__V_FREXP_MANT_F64
11488 
11489  GPUStaticInst*
11491  {
11492  return new Inst_VOP1__V_FRACT_F64(&iFmt->iFmt_VOP1);
11493  } // decode_OP_VOP1__V_FRACT_F64
11494 
11495  GPUStaticInst*
11497  {
11498  return new Inst_VOP1__V_FREXP_EXP_I32_F32(&iFmt->iFmt_VOP1);
11499  } // decode_OP_VOP1__V_FREXP_EXP_I32_F32
11500 
11501  GPUStaticInst*
11503  {
11504  return new Inst_VOP1__V_FREXP_MANT_F32(&iFmt->iFmt_VOP1);
11505  } // decode_OP_VOP1__V_FREXP_MANT_F32
11506 
11507  GPUStaticInst*
11509  {
11510  return new Inst_VOP1__V_CLREXCP(&iFmt->iFmt_VOP1);
11511  } // decode_OP_VOP1__V_CLREXCP
11512 
11513  GPUStaticInst*
11515  {
11516  fatal("Trying to decode instruction without a class\n");
11517  return nullptr;
11518  }
11519 
11520  GPUStaticInst*
11522  {
11523  return new Inst_VOP1__V_CVT_F16_U16(&iFmt->iFmt_VOP1);
11524  } // decode_OP_VOP1__V_CVT_F16_U16
11525 
11526  GPUStaticInst*
11528  {
11529  return new Inst_VOP1__V_CVT_F16_I16(&iFmt->iFmt_VOP1);
11530  } // decode_OP_VOP1__V_CVT_F16_I16
11531 
11532  GPUStaticInst*
11534  {
11535  return new Inst_VOP1__V_CVT_U16_F16(&iFmt->iFmt_VOP1);
11536  } // decode_OP_VOP1__V_CVT_U16_F16
11537 
11538  GPUStaticInst*
11540  {
11541  return new Inst_VOP1__V_CVT_I16_F16(&iFmt->iFmt_VOP1);
11542  } // decode_OP_VOP1__V_CVT_I16_F16
11543 
11544  GPUStaticInst*
11546  {
11547  return new Inst_VOP1__V_RCP_F16(&iFmt->iFmt_VOP1);
11548  } // decode_OP_VOP1__V_RCP_F16
11549 
11550  GPUStaticInst*
11552  {
11553  return new Inst_VOP1__V_SQRT_F16(&iFmt->iFmt_VOP1);
11554  } // decode_OP_VOP1__V_SQRT_F16
11555 
11556  GPUStaticInst*
11558  {
11559  return new Inst_VOP1__V_RSQ_F16(&iFmt->iFmt_VOP1);
11560  } // decode_OP_VOP1__V_RSQ_F16
11561 
11562  GPUStaticInst*
11564  {
11565  return new Inst_VOP1__V_LOG_F16(&iFmt->iFmt_VOP1);
11566  } // decode_OP_VOP1__V_LOG_F16
11567 
11568  GPUStaticInst*
11570  {
11571  return new Inst_VOP1__V_EXP_F16(&iFmt->iFmt_VOP1);
11572  } // decode_OP_VOP1__V_EXP_F16
11573 
11574  GPUStaticInst*
11576  {
11577  return new Inst_VOP1__V_FREXP_MANT_F16(&iFmt->iFmt_VOP1);
11578  } // decode_OP_VOP1__V_FREXP_MANT_F16
11579 
11580  GPUStaticInst*
11582  {
11583  return new Inst_VOP1__V_FREXP_EXP_I16_F16(&iFmt->iFmt_VOP1);
11584  } // decode_OP_VOP1__V_FREXP_EXP_I16_F16
11585 
11586  GPUStaticInst*
11588  {
11589  return new Inst_VOP1__V_FLOOR_F16(&iFmt->iFmt_VOP1);
11590  } // decode_OP_VOP1__V_FLOOR_F16
11591 
11592  GPUStaticInst*
11594  {
11595  return new Inst_VOP1__V_CEIL_F16(&iFmt->iFmt_VOP1);
11596  } // decode_OP_VOP1__V_CEIL_F16
11597 
11598  GPUStaticInst*
11600  {
11601  return new Inst_VOP1__V_TRUNC_F16(&iFmt->iFmt_VOP1);
11602  } // decode_OP_VOP1__V_TRUNC_F16
11603 
11604  GPUStaticInst*
11606  {
11607  return new Inst_VOP1__V_RNDNE_F16(&iFmt->iFmt_VOP1);
11608  } // decode_OP_VOP1__V_RNDNE_F16
11609 
11610  GPUStaticInst*
11612  {
11613  return new Inst_VOP1__V_FRACT_F16(&iFmt->iFmt_VOP1);
11614  } // decode_OP_VOP1__V_FRACT_F16
11615 
11616  GPUStaticInst*
11618  {
11619  return new Inst_VOP1__V_SIN_F16(&iFmt->iFmt_VOP1);
11620  } // decode_OP_VOP1__V_SIN_F16
11621 
11622  GPUStaticInst*
11624  {
11625  return new Inst_VOP1__V_COS_F16(&iFmt->iFmt_VOP1);
11626  } // decode_OP_VOP1__V_COS_F16
11627 
11628  GPUStaticInst*
11630  {
11631  return new Inst_VOP1__V_EXP_LEGACY_F32(&iFmt->iFmt_VOP1);
11632  } // decode_OP_VOP1__V_EXP_LEGACY_F32
11633 
11634  GPUStaticInst*
11636  {
11637  return new Inst_VOP1__V_LOG_LEGACY_F32(&iFmt->iFmt_VOP1);
11638  } // decode_OP_VOP1__V_LOG_LEGACY_F32
11639 
11640  GPUStaticInst*
11642  {
11643  fatal("Trying to decode instruction without a class\n");
11644  return nullptr;
11645  }
11646 
11647  GPUStaticInst*
11649  {
11650  fatal("Trying to decode instruction without a class\n");
11651  return nullptr;
11652  }
11653 
11654  GPUStaticInst*
11656  {
11657  fatal("Trying to decode instruction without a class\n");
11658  return nullptr;
11659  }
11660 
11661  GPUStaticInst*
11663  {
11664  fatal("Trying to decode instruction without a class\n");
11665  return nullptr;
11666  }
11667 
11668  GPUStaticInst*
11670  {
11671  return new Inst_VOPC__V_CMP_CLASS_F32(&iFmt->iFmt_VOPC);
11672  } // decode_OP_VOPC__V_CMP_CLASS_F32
11673 
11674  GPUStaticInst*
11676  {
11677  return new Inst_VOPC__V_CMPX_CLASS_F32(&iFmt->iFmt_VOPC);
11678  } // decode_OP_VOPC__V_CMPX_CLASS_F32
11679 
11680  GPUStaticInst*
11682  {
11683  return new Inst_VOPC__V_CMP_CLASS_F64(&iFmt->iFmt_VOPC);
11684  } // decode_OP_VOPC__V_CMP_CLASS_F64
11685 
11686  GPUStaticInst*
11688  {
11689  return new Inst_VOPC__V_CMPX_CLASS_F64(&iFmt->iFmt_VOPC);
11690  } // decode_OP_VOPC__V_CMPX_CLASS_F64
11691 
11692  GPUStaticInst*
11694  {
11695  return new Inst_VOPC__V_CMP_CLASS_F16(&iFmt->iFmt_VOPC);
11696  } // decode_OP_VOPC__V_CMP_CLASS_F16
11697 
11698  GPUStaticInst*
11700  {
11701  return new Inst_VOPC__V_CMPX_CLASS_F16(&iFmt->iFmt_VOPC);
11702  } // decode_OP_VOPC__V_CMPX_CLASS_F16
11703 
11704  GPUStaticInst*
11706  {
11707  return new Inst_VOPC__V_CMP_F_F16(&iFmt->iFmt_VOPC);
11708  } // decode_OP_VOPC__V_CMP_F_F16
11709 
11710  GPUStaticInst*
11712  {
11713  return new Inst_VOPC__V_CMP_LT_F16(&iFmt->iFmt_VOPC);
11714  } // decode_OP_VOPC__V_CMP_LT_F16
11715 
11716  GPUStaticInst*
11718  {
11719  return new Inst_VOPC__V_CMP_EQ_F16(&iFmt->iFmt_VOPC);
11720  } // decode_OP_VOPC__V_CMP_EQ_F16
11721 
11722  GPUStaticInst*
11724  {
11725  return new Inst_VOPC__V_CMP_LE_F16(&iFmt->iFmt_VOPC);
11726  } // decode_OP_VOPC__V_CMP_LE_F16
11727 
11728  GPUStaticInst*
11730  {
11731  return new Inst_VOPC__V_CMP_GT_F16(&iFmt->iFmt_VOPC);
11732  } // decode_OP_VOPC__V_CMP_GT_F16
11733 
11734  GPUStaticInst*
11736  {
11737  return new Inst_VOPC__V_CMP_LG_F16(&iFmt->iFmt_VOPC);
11738  } // decode_OP_VOPC__V_CMP_LG_F16
11739 
11740  GPUStaticInst*
11742  {
11743  return new Inst_VOPC__V_CMP_GE_F16(&iFmt->iFmt_VOPC);
11744  } // decode_OP_VOPC__V_CMP_GE_F16
11745 
11746  GPUStaticInst*
11748  {
11749  return new Inst_VOPC__V_CMP_O_F16(&iFmt->iFmt_VOPC);
11750  } // decode_OP_VOPC__V_CMP_O_F16
11751 
11752  GPUStaticInst*
11754  {
11755  return new Inst_VOPC__V_CMP_U_F16(&iFmt->iFmt_VOPC);
11756  } // decode_OP_VOPC__V_CMP_U_F16
11757 
11758  GPUStaticInst*
11760  {
11761  return new Inst_VOPC__V_CMP_NGE_F16(&iFmt->iFmt_VOPC);
11762  } // decode_OP_VOPC__V_CMP_NGE_F16
11763 
11764  GPUStaticInst*
11766  {
11767  return new Inst_VOPC__V_CMP_NLG_F16(&iFmt->iFmt_VOPC);
11768  } // decode_OP_VOPC__V_CMP_NLG_F16
11769 
11770  GPUStaticInst*
11772  {
11773  return new Inst_VOPC__V_CMP_NGT_F16(&iFmt->iFmt_VOPC);
11774  } // decode_OP_VOPC__V_CMP_NGT_F16
11775 
11776  GPUStaticInst*
11778  {
11779  return new Inst_VOPC__V_CMP_NLE_F16(&iFmt->iFmt_VOPC);
11780  } // decode_OP_VOPC__V_CMP_NLE_F16
11781 
11782  GPUStaticInst*
11784  {
11785  return new Inst_VOPC__V_CMP_NEQ_F16(&iFmt->iFmt_VOPC);
11786  } // decode_OP_VOPC__V_CMP_NEQ_F16
11787 
11788  GPUStaticInst*
11790  {
11791  return new Inst_VOPC__V_CMP_NLT_F16(&iFmt->iFmt_VOPC);
11792  } // decode_OP_VOPC__V_CMP_NLT_F16
11793 
11794  GPUStaticInst*
11796  {
11797  return new Inst_VOPC__V_CMP_TRU_F16(&iFmt->iFmt_VOPC);
11798  } // decode_OP_VOPC__V_CMP_TRU_F16
11799 
11800  GPUStaticInst*
11802  {
11803  return new Inst_VOPC__V_CMPX_F_F16(&iFmt->iFmt_VOPC);
11804  } // decode_OP_VOPC__V_CMPX_F_F16
11805 
11806  GPUStaticInst*
11808  {
11809  return new Inst_VOPC__V_CMPX_LT_F16(&iFmt->iFmt_VOPC);
11810  } // decode_OP_VOPC__V_CMPX_LT_F16
11811 
11812  GPUStaticInst*
11814  {
11815  return new Inst_VOPC__V_CMPX_EQ_F16(&iFmt->iFmt_VOPC);
11816  } // decode_OP_VOPC__V_CMPX_EQ_F16
11817 
11818  GPUStaticInst*
11820  {
11821  return new Inst_VOPC__V_CMPX_LE_F16(&iFmt->iFmt_VOPC);
11822  } // decode_OP_VOPC__V_CMPX_LE_F16
11823 
11824  GPUStaticInst*
11826  {
11827  return new Inst_VOPC__V_CMPX_GT_F16(&iFmt->iFmt_VOPC);
11828  } // decode_OP_VOPC__V_CMPX_GT_F16
11829 
11830  GPUStaticInst*
11832  {
11833  return new Inst_VOPC__V_CMPX_LG_F16(&iFmt->iFmt_VOPC);
11834  } // decode_OP_VOPC__V_CMPX_LG_F16
11835 
11836  GPUStaticInst*
11838  {
11839  return new Inst_VOPC__V_CMPX_GE_F16(&iFmt->iFmt_VOPC);
11840  } // decode_OP_VOPC__V_CMPX_GE_F16
11841 
11842  GPUStaticInst*
11844  {
11845  return new Inst_VOPC__V_CMPX_O_F16(&iFmt->iFmt_VOPC);
11846  } // decode_OP_VOPC__V_CMPX_O_F16
11847 
11848  GPUStaticInst*
11850  {
11851  return new Inst_VOPC__V_CMPX_U_F16(&iFmt->iFmt_VOPC);
11852  } // decode_OP_VOPC__V_CMPX_U_F16
11853 
11854  GPUStaticInst*
11856  {
11857  return new Inst_VOPC__V_CMPX_NGE_F16(&iFmt->iFmt_VOPC);
11858  } // decode_OP_VOPC__V_CMPX_NGE_F16
11859 
11860  GPUStaticInst*
11862  {
11863  return new Inst_VOPC__V_CMPX_NLG_F16(&iFmt->iFmt_VOPC);
11864  } // decode_OP_VOPC__V_CMPX_NLG_F16
11865 
11866  GPUStaticInst*
11868  {
11869  return new Inst_VOPC__V_CMPX_NGT_F16(&iFmt->iFmt_VOPC);
11870  } // decode_OP_VOPC__V_CMPX_NGT_F16
11871 
11872  GPUStaticInst*
11874  {
11875  return new Inst_VOPC__V_CMPX_NLE_F16(&iFmt->iFmt_VOPC);
11876  } // decode_OP_VOPC__V_CMPX_NLE_F16
11877 
11878  GPUStaticInst*
11880  {
11881  return new Inst_VOPC__V_CMPX_NEQ_F16(&iFmt->iFmt_VOPC);
11882  } // decode_OP_VOPC__V_CMPX_NEQ_F16
11883 
11884  GPUStaticInst*
11886  {
11887  return new Inst_VOPC__V_CMPX_NLT_F16(&iFmt->iFmt_VOPC);
11888  } // decode_OP_VOPC__V_CMPX_NLT_F16
11889 
11890  GPUStaticInst*
11892  {
11893  return new Inst_VOPC__V_CMPX_TRU_F16(&iFmt->iFmt_VOPC);
11894  } // decode_OP_VOPC__V_CMPX_TRU_F16
11895 
11896  GPUStaticInst*
11898  {
11899  return new Inst_VOPC__V_CMP_F_F32(&iFmt->iFmt_VOPC);
11900  } // decode_OP_VOPC__V_CMP_F_F32
11901 
11902  GPUStaticInst*
11904  {
11905  return new Inst_VOPC__V_CMP_LT_F32(&iFmt->iFmt_VOPC);
11906  } // decode_OP_VOPC__V_CMP_LT_F32
11907 
11908  GPUStaticInst*
11910  {
11911  return new Inst_VOPC__V_CMP_EQ_F32(&iFmt->iFmt_VOPC);
11912  } // decode_OP_VOPC__V_CMP_EQ_F32
11913 
11914  GPUStaticInst*
11916  {
11917  return new Inst_VOPC__V_CMP_LE_F32(&iFmt->iFmt_VOPC);
11918  } // decode_OP_VOPC__V_CMP_LE_F32
11919 
11920  GPUStaticInst*
11922  {
11923  return new Inst_VOPC__V_CMP_GT_F32(&iFmt->iFmt_VOPC);
11924  } // decode_OP_VOPC__V_CMP_GT_F32
11925 
11926  GPUStaticInst*
11928  {
11929  return new Inst_VOPC__V_CMP_LG_F32(&iFmt->iFmt_VOPC);
11930  } // decode_OP_VOPC__V_CMP_LG_F32
11931 
11932  GPUStaticInst*
11934  {
11935  return new Inst_VOPC__V_CMP_GE_F32(&iFmt->iFmt_VOPC);
11936  } // decode_OP_VOPC__V_CMP_GE_F32
11937 
11938  GPUStaticInst*
11940  {
11941  return new Inst_VOPC__V_CMP_O_F32(&iFmt->iFmt_VOPC);
11942  } // decode_OP_VOPC__V_CMP_O_F32
11943 
11944  GPUStaticInst*
11946  {
11947  return new Inst_VOPC__V_CMP_U_F32(&iFmt->iFmt_VOPC);
11948  } // decode_OP_VOPC__V_CMP_U_F32
11949 
11950  GPUStaticInst*
11952  {
11953  return new Inst_VOPC__V_CMP_NGE_F32(&iFmt->iFmt_VOPC);
11954  } // decode_OP_VOPC__V_CMP_NGE_F32
11955 
11956  GPUStaticInst*
11958  {
11959  return new Inst_VOPC__V_CMP_NLG_F32(&iFmt->iFmt_VOPC);
11960  } // decode_OP_VOPC__V_CMP_NLG_F32
11961 
11962  GPUStaticInst*
11964  {
11965  return new Inst_VOPC__V_CMP_NGT_F32(&iFmt->iFmt_VOPC);
11966  } // decode_OP_VOPC__V_CMP_NGT_F32
11967 
11968  GPUStaticInst*
11970  {
11971  return new Inst_VOPC__V_CMP_NLE_F32(&iFmt->iFmt_VOPC);
11972  } // decode_OP_VOPC__V_CMP_NLE_F32
11973 
11974  GPUStaticInst*
11976  {
11977  return new Inst_VOPC__V_CMP_NEQ_F32(&iFmt->iFmt_VOPC);
11978  } // decode_OP_VOPC__V_CMP_NEQ_F32
11979 
11980  GPUStaticInst*
11982  {
11983  return new Inst_VOPC__V_CMP_NLT_F32(&iFmt->iFmt_VOPC);
11984  } // decode_OP_VOPC__V_CMP_NLT_F32
11985 
11986  GPUStaticInst*
11988  {
11989  return new Inst_VOPC__V_CMP_TRU_F32(&iFmt->iFmt_VOPC);
11990  } // decode_OP_VOPC__V_CMP_TRU_F32
11991 
11992  GPUStaticInst*
11994  {
11995  return new Inst_VOPC__V_CMPX_F_F32(&iFmt->iFmt_VOPC);
11996  } // decode_OP_VOPC__V_CMPX_F_F32
11997 
11998  GPUStaticInst*
12000  {
12001  return new Inst_VOPC__V_CMPX_LT_F32(&iFmt->iFmt_VOPC);
12002  } // decode_OP_VOPC__V_CMPX_LT_F32
12003 
12004  GPUStaticInst*
12006  {
12007  return new Inst_VOPC__V_CMPX_EQ_F32(&iFmt->iFmt_VOPC);
12008  } // decode_OP_VOPC__V_CMPX_EQ_F32
12009 
12010  GPUStaticInst*
12012  {
12013  return new Inst_VOPC__V_CMPX_LE_F32(&iFmt->iFmt_VOPC);
12014  } // decode_OP_VOPC__V_CMPX_LE_F32
12015 
12016  GPUStaticInst*
12018  {
12019  return new Inst_VOPC__V_CMPX_GT_F32(&iFmt->iFmt_VOPC);
12020  } // decode_OP_VOPC__V_CMPX_GT_F32
12021 
12022  GPUStaticInst*
12024  {
12025  return new Inst_VOPC__V_CMPX_LG_F32(&iFmt->iFmt_VOPC);
12026  } // decode_OP_VOPC__V_CMPX_LG_F32
12027 
12028  GPUStaticInst*
12030  {
12031  return new Inst_VOPC__V_CMPX_GE_F32(&iFmt->iFmt_VOPC);
12032  } // decode_OP_VOPC__V_CMPX_GE_F32
12033 
12034  GPUStaticInst*
12036  {
12037  return new Inst_VOPC__V_CMPX_O_F32(&iFmt->iFmt_VOPC);
12038  } // decode_OP_VOPC__V_CMPX_O_F32
12039 
12040  GPUStaticInst*
12042  {
12043  return new Inst_VOPC__V_CMPX_U_F32(&iFmt->iFmt_VOPC);
12044  } // decode_OP_VOPC__V_CMPX_U_F32
12045 
12046  GPUStaticInst*
12048  {
12049  return new Inst_VOPC__V_CMPX_NGE_F32(&iFmt->iFmt_VOPC);
12050  } // decode_OP_VOPC__V_CMPX_NGE_F32
12051 
12052  GPUStaticInst*
12054  {
12055  return new Inst_VOPC__V_CMPX_NLG_F32(&iFmt->iFmt_VOPC);
12056  } // decode_OP_VOPC__V_CMPX_NLG_F32
12057 
12058  GPUStaticInst*
12060  {
12061  return new Inst_VOPC__V_CMPX_NGT_F32(&iFmt->iFmt_VOPC);
12062  } // decode_OP_VOPC__V_CMPX_NGT_F32
12063 
12064  GPUStaticInst*
12066  {
12067  return new Inst_VOPC__V_CMPX_NLE_F32(&iFmt->iFmt_VOPC);
12068  } // decode_OP_VOPC__V_CMPX_NLE_F32
12069 
12070  GPUStaticInst*
12072  {
12073  return new Inst_VOPC__V_CMPX_NEQ_F32(&iFmt->iFmt_VOPC);
12074  } // decode_OP_VOPC__V_CMPX_NEQ_F32
12075 
12076  GPUStaticInst*
12078  {
12079  return new Inst_VOPC__V_CMPX_NLT_F32(&iFmt->iFmt_VOPC);
12080  } // decode_OP_VOPC__V_CMPX_NLT_F32
12081 
12082  GPUStaticInst*
12084  {
12085  return new Inst_VOPC__V_CMPX_TRU_F32(&iFmt->iFmt_VOPC);
12086  } // decode_OP_VOPC__V_CMPX_TRU_F32
12087 
12088  GPUStaticInst*
12090  {
12091  return new Inst_VOPC__V_CMP_F_F64(&iFmt->iFmt_VOPC);
12092  } // decode_OP_VOPC__V_CMP_F_F64
12093 
12094  GPUStaticInst*
12096  {
12097  return new Inst_VOPC__V_CMP_LT_F64(&iFmt->iFmt_VOPC);
12098  } // decode_OP_VOPC__V_CMP_LT_F64
12099 
12100  GPUStaticInst*
12102  {
12103  return new Inst_VOPC__V_CMP_EQ_F64(&iFmt->iFmt_VOPC);
12104  } // decode_OP_VOPC__V_CMP_EQ_F64
12105 
12106  GPUStaticInst*
12108  {
12109  return new Inst_VOPC__V_CMP_LE_F64(&iFmt->iFmt_VOPC);
12110  } // decode_OP_VOPC__V_CMP_LE_F64
12111 
12112  GPUStaticInst*
12114  {
12115  return new Inst_VOPC__V_CMP_GT_F64(&iFmt->iFmt_VOPC);
12116  } // decode_OP_VOPC__V_CMP_GT_F64
12117 
12118  GPUStaticInst*
12120  {
12121  return new Inst_VOPC__V_CMP_LG_F64(&iFmt->iFmt_VOPC);
12122  } // decode_OP_VOPC__V_CMP_LG_F64
12123 
12124  GPUStaticInst*
12126  {
12127  return new Inst_VOPC__V_CMP_GE_F64(&iFmt->iFmt_VOPC);
12128  } // decode_OP_VOPC__V_CMP_GE_F64
12129 
12130  GPUStaticInst*
12132  {
12133  return new Inst_VOPC__V_CMP_O_F64(&iFmt->iFmt_VOPC);
12134  } // decode_OP_VOPC__V_CMP_O_F64
12135 
12136  GPUStaticInst*
12138  {
12139  return new Inst_VOPC__V_CMP_U_F64(&iFmt->iFmt_VOPC);
12140  } // decode_OP_VOPC__V_CMP_U_F64
12141 
12142  GPUStaticInst*
12144  {
12145  return new Inst_VOPC__V_CMP_NGE_F64(&iFmt->iFmt_VOPC);
12146  } // decode_OP_VOPC__V_CMP_NGE_F64
12147 
12148  GPUStaticInst*
12150  {
12151  return new Inst_VOPC__V_CMP_NLG_F64(&iFmt->iFmt_VOPC);
12152  } // decode_OP_VOPC__V_CMP_NLG_F64
12153 
12154  GPUStaticInst*
12156  {
12157  return new Inst_VOPC__V_CMP_NGT_F64(&iFmt->iFmt_VOPC);
12158  } // decode_OP_VOPC__V_CMP_NGT_F64
12159 
12160  GPUStaticInst*
12162  {
12163  return new Inst_VOPC__V_CMP_NLE_F64(&iFmt->iFmt_VOPC);
12164  } // decode_OP_VOPC__V_CMP_NLE_F64
12165 
12166  GPUStaticInst*
12168  {
12169  return new Inst_VOPC__V_CMP_NEQ_F64(&iFmt->iFmt_VOPC);
12170  } // decode_OP_VOPC__V_CMP_NEQ_F64
12171 
12172  GPUStaticInst*
12174  {
12175  return new Inst_VOPC__V_CMP_NLT_F64(&iFmt->iFmt_VOPC);
12176  } // decode_OP_VOPC__V_CMP_NLT_F64
12177 
12178  GPUStaticInst*
12180  {
12181  return new Inst_VOPC__V_CMP_TRU_F64(&iFmt->iFmt_VOPC);
12182  } // decode_OP_VOPC__V_CMP_TRU_F64
12183 
12184  GPUStaticInst*
12186  {
12187  return new Inst_VOPC__V_CMPX_F_F64(&iFmt->iFmt_VOPC);
12188  } // decode_OP_VOPC__V_CMPX_F_F64
12189 
12190  GPUStaticInst*
12192  {
12193  return new Inst_VOPC__V_CMPX_LT_F64(&iFmt->iFmt_VOPC);
12194  } // decode_OP_VOPC__V_CMPX_LT_F64
12195 
12196  GPUStaticInst*
12198  {
12199  return new Inst_VOPC__V_CMPX_EQ_F64(&iFmt->iFmt_VOPC);
12200  } // decode_OP_VOPC__V_CMPX_EQ_F64
12201 
12202  GPUStaticInst*
12204  {
12205  return new Inst_VOPC__V_CMPX_LE_F64(&iFmt->iFmt_VOPC);
12206  } // decode_OP_VOPC__V_CMPX_LE_F64
12207 
12208  GPUStaticInst*
12210  {
12211  return new Inst_VOPC__V_CMPX_GT_F64(&iFmt->iFmt_VOPC);
12212  } // decode_OP_VOPC__V_CMPX_GT_F64
12213 
12214  GPUStaticInst*
12216  {
12217  return new Inst_VOPC__V_CMPX_LG_F64(&iFmt->iFmt_VOPC);
12218  } // decode_OP_VOPC__V_CMPX_LG_F64
12219 
12220  GPUStaticInst*
12222  {
12223  return new Inst_VOPC__V_CMPX_GE_F64(&iFmt->iFmt_VOPC);
12224  } // decode_OP_VOPC__V_CMPX_GE_F64
12225 
12226  GPUStaticInst*
12228  {
12229  return new Inst_VOPC__V_CMPX_O_F64(&iFmt->iFmt_VOPC);
12230  } // decode_OP_VOPC__V_CMPX_O_F64
12231 
12232  GPUStaticInst*
12234  {
12235  return new Inst_VOPC__V_CMPX_U_F64(&iFmt->iFmt_VOPC);
12236  } // decode_OP_VOPC__V_CMPX_U_F64
12237 
12238  GPUStaticInst*
12240  {
12241  return new Inst_VOPC__V_CMPX_NGE_F64(&iFmt->iFmt_VOPC);
12242  } // decode_OP_VOPC__V_CMPX_NGE_F64
12243 
12244  GPUStaticInst*
12246  {
12247  return new Inst_VOPC__V_CMPX_NLG_F64(&iFmt->iFmt_VOPC);
12248  } // decode_OP_VOPC__V_CMPX_NLG_F64
12249 
12250  GPUStaticInst*
12252  {
12253  return new Inst_VOPC__V_CMPX_NGT_F64(&iFmt->iFmt_VOPC);
12254  } // decode_OP_VOPC__V_CMPX_NGT_F64
12255 
12256  GPUStaticInst*
12258  {
12259  return new Inst_VOPC__V_CMPX_NLE_F64(&iFmt->iFmt_VOPC);
12260  } // decode_OP_VOPC__V_CMPX_NLE_F64
12261 
12262  GPUStaticInst*
12264  {
12265  return new Inst_VOPC__V_CMPX_NEQ_F64(&iFmt->iFmt_VOPC);
12266  } // decode_OP_VOPC__V_CMPX_NEQ_F64
12267 
12268  GPUStaticInst*
12270  {
12271  return new Inst_VOPC__V_CMPX_NLT_F64(&iFmt->iFmt_VOPC);
12272  } // decode_OP_VOPC__V_CMPX_NLT_F64
12273 
12274  GPUStaticInst*
12276  {
12277  return new Inst_VOPC__V_CMPX_TRU_F64(&iFmt->iFmt_VOPC);
12278  } // decode_OP_VOPC__V_CMPX_TRU_F64
12279 
12280  GPUStaticInst*
12282  {
12283  return new Inst_VOPC__V_CMP_F_I16(&iFmt->iFmt_VOPC);
12284  } // decode_OP_VOPC__V_CMP_F_I16
12285 
12286  GPUStaticInst*
12288  {
12289  return new Inst_VOPC__V_CMP_LT_I16(&iFmt->iFmt_VOPC);
12290  } // decode_OP_VOPC__V_CMP_LT_I16
12291 
12292  GPUStaticInst*
12294  {
12295  return new Inst_VOPC__V_CMP_EQ_I16(&iFmt->iFmt_VOPC);
12296  } // decode_OP_VOPC__V_CMP_EQ_I16
12297 
12298  GPUStaticInst*
12300  {
12301  return new Inst_VOPC__V_CMP_LE_I16(&iFmt->iFmt_VOPC);
12302  } // decode_OP_VOPC__V_CMP_LE_I16
12303 
12304  GPUStaticInst*
12306  {
12307  return new Inst_VOPC__V_CMP_GT_I16(&iFmt->iFmt_VOPC);
12308  } // decode_OP_VOPC__V_CMP_GT_I16
12309 
12310  GPUStaticInst*
12312  {
12313  return new Inst_VOPC__V_CMP_NE_I16(&iFmt->iFmt_VOPC);
12314  } // decode_OP_VOPC__V_CMP_NE_I16
12315 
12316  GPUStaticInst*
12318  {
12319  return new Inst_VOPC__V_CMP_GE_I16(&iFmt->iFmt_VOPC);
12320  } // decode_OP_VOPC__V_CMP_GE_I16
12321 
12322  GPUStaticInst*
12324  {
12325  return new Inst_VOPC__V_CMP_T_I16(&iFmt->iFmt_VOPC);
12326  } // decode_OP_VOPC__V_CMP_T_I16
12327 
12328  GPUStaticInst*
12330  {
12331  return new Inst_VOPC__V_CMP_F_U16(&iFmt->iFmt_VOPC);
12332  } // decode_OP_VOPC__V_CMP_F_U16
12333 
12334  GPUStaticInst*
12336  {
12337  return new Inst_VOPC__V_CMP_LT_U16(&iFmt->iFmt_VOPC);
12338  } // decode_OP_VOPC__V_CMP_LT_U16
12339 
12340  GPUStaticInst*
12342  {
12343  return new Inst_VOPC__V_CMP_EQ_U16(&iFmt->iFmt_VOPC);
12344  } // decode_OP_VOPC__V_CMP_EQ_U16
12345 
12346  GPUStaticInst*
12348  {
12349  return new Inst_VOPC__V_CMP_LE_U16(&iFmt->iFmt_VOPC);
12350  } // decode_OP_VOPC__V_CMP_LE_U16
12351 
12352  GPUStaticInst*
12354  {
12355  return new Inst_VOPC__V_CMP_GT_U16(&iFmt->iFmt_VOPC);
12356  } // decode_OP_VOPC__V_CMP_GT_U16
12357 
12358  GPUStaticInst*
12360  {
12361  return new Inst_VOPC__V_CMP_NE_U16(&iFmt->iFmt_VOPC);
12362  } // decode_OP_VOPC__V_CMP_NE_U16
12363 
12364  GPUStaticInst*
12366  {
12367  return new Inst_VOPC__V_CMP_GE_U16(&iFmt->iFmt_VOPC);
12368  } // decode_OP_VOPC__V_CMP_GE_U16
12369 
12370  GPUStaticInst*
12372  {
12373  return new Inst_VOPC__V_CMP_T_U16(&iFmt->iFmt_VOPC);
12374  } // decode_OP_VOPC__V_CMP_T_U16
12375 
12376  GPUStaticInst*
12378  {
12379  return new Inst_VOPC__V_CMPX_F_I16(&iFmt->iFmt_VOPC);
12380  } // decode_OP_VOPC__V_CMPX_F_I16
12381 
12382  GPUStaticInst*
12384  {
12385  return new Inst_VOPC__V_CMPX_LT_I16(&iFmt->iFmt_VOPC);
12386  } // decode_OP_VOPC__V_CMPX_LT_I16
12387 
12388  GPUStaticInst*
12390  {
12391  return new Inst_VOPC__V_CMPX_EQ_I16(&iFmt->iFmt_VOPC);
12392  } // decode_OP_VOPC__V_CMPX_EQ_I16
12393 
12394  GPUStaticInst*
12396  {
12397  return new Inst_VOPC__V_CMPX_LE_I16(&iFmt->iFmt_VOPC);
12398  } // decode_OP_VOPC__V_CMPX_LE_I16
12399 
12400  GPUStaticInst*
12402  {
12403  return new Inst_VOPC__V_CMPX_GT_I16(&iFmt->iFmt_VOPC);
12404  } // decode_OP_VOPC__V_CMPX_GT_I16
12405 
12406  GPUStaticInst*
12408  {
12409  return new Inst_VOPC__V_CMPX_NE_I16(&iFmt->iFmt_VOPC);
12410  } // decode_OP_VOPC__V_CMPX_NE_I16
12411 
12412  GPUStaticInst*
12414  {
12415  return new Inst_VOPC__V_CMPX_GE_I16(&iFmt->iFmt_VOPC);
12416  } // decode_OP_VOPC__V_CMPX_GE_I16
12417 
12418  GPUStaticInst*
12420  {
12421  return new Inst_VOPC__V_CMPX_T_I16(&iFmt->iFmt_VOPC);
12422  } // decode_OP_VOPC__V_CMPX_T_I16
12423 
12424  GPUStaticInst*
12426  {
12427  return new Inst_VOPC__V_CMPX_F_U16(&iFmt->iFmt_VOPC);
12428  } // decode_OP_VOPC__V_CMPX_F_U16
12429 
12430  GPUStaticInst*
12432  {
12433  return new Inst_VOPC__V_CMPX_LT_U16(&iFmt->iFmt_VOPC);
12434  } // decode_OP_VOPC__V_CMPX_LT_U16
12435 
12436  GPUStaticInst*
12438  {
12439  return new Inst_VOPC__V_CMPX_EQ_U16(&iFmt->iFmt_VOPC);
12440  } // decode_OP_VOPC__V_CMPX_EQ_U16
12441 
12442  GPUStaticInst*
12444  {
12445  return new Inst_VOPC__V_CMPX_LE_U16(&iFmt->iFmt_VOPC);
12446  } // decode_OP_VOPC__V_CMPX_LE_U16
12447 
12448  GPUStaticInst*
12450  {
12451  return new Inst_VOPC__V_CMPX_GT_U16(&iFmt->iFmt_VOPC);
12452  } // decode_OP_VOPC__V_CMPX_GT_U16
12453 
12454  GPUStaticInst*
12456  {
12457  return new Inst_VOPC__V_CMPX_NE_U16(&iFmt->iFmt_VOPC);
12458  } // decode_OP_VOPC__V_CMPX_NE_U16
12459 
12460  GPUStaticInst*
12462  {
12463  return new Inst_VOPC__V_CMPX_GE_U16(&iFmt->iFmt_VOPC);
12464  } // decode_OP_VOPC__V_CMPX_GE_U16
12465 
12466  GPUStaticInst*
12468  {
12469  return new Inst_VOPC__V_CMPX_T_U16(&iFmt->iFmt_VOPC);
12470  } // decode_OP_VOPC__V_CMPX_T_U16
12471 
12472  GPUStaticInst*
12474  {
12475  return new Inst_VOPC__V_CMP_F_I32(&iFmt->iFmt_VOPC);
12476  } // decode_OP_VOPC__V_CMP_F_I32
12477 
12478  GPUStaticInst*
12480  {
12481  return new Inst_VOPC__V_CMP_LT_I32(&iFmt->iFmt_VOPC);
12482  } // decode_OP_VOPC__V_CMP_LT_I32
12483 
12484  GPUStaticInst*
12486  {
12487  return new Inst_VOPC__V_CMP_EQ_I32(&iFmt->iFmt_VOPC);
12488  } // decode_OP_VOPC__V_CMP_EQ_I32
12489 
12490  GPUStaticInst*
12492  {
12493  return new Inst_VOPC__V_CMP_LE_I32(&iFmt->iFmt_VOPC);
12494  } // decode_OP_VOPC__V_CMP_LE_I32
12495 
12496  GPUStaticInst*
12498  {
12499  return new Inst_VOPC__V_CMP_GT_I32(&iFmt->iFmt_VOPC);
12500  } // decode_OP_VOPC__V_CMP_GT_I32
12501 
12502  GPUStaticInst*
12504  {
12505  return new Inst_VOPC__V_CMP_NE_I32(&iFmt->iFmt_VOPC);
12506  } // decode_OP_VOPC__V_CMP_NE_I32
12507 
12508  GPUStaticInst*
12510  {
12511  return new Inst_VOPC__V_CMP_GE_I32(&iFmt->iFmt_VOPC);
12512  } // decode_OP_VOPC__V_CMP_GE_I32
12513 
12514  GPUStaticInst*
12516  {
12517  return new Inst_VOPC__V_CMP_T_I32(&iFmt->iFmt_VOPC);
12518  } // decode_OP_VOPC__V_CMP_T_I32
12519 
12520  GPUStaticInst*
12522  {
12523  return new Inst_VOPC__V_CMP_F_U32(&iFmt->iFmt_VOPC);
12524  } // decode_OP_VOPC__V_CMP_F_U32
12525 
12526  GPUStaticInst*
12528  {
12529  return new Inst_VOPC__V_CMP_LT_U32(&iFmt->iFmt_VOPC);
12530  } // decode_OP_VOPC__V_CMP_LT_U32
12531 
12532  GPUStaticInst*
12534  {
12535  return new Inst_VOPC__V_CMP_EQ_U32(&iFmt->iFmt_VOPC);
12536  } // decode_OP_VOPC__V_CMP_EQ_U32
12537 
12538  GPUStaticInst*
12540  {
12541  return new Inst_VOPC__V_CMP_LE_U32(&iFmt->iFmt_VOPC);
12542  } // decode_OP_VOPC__V_CMP_LE_U32
12543 
12544  GPUStaticInst*
12546  {
12547  return new Inst_VOPC__V_CMP_GT_U32(&iFmt->iFmt_VOPC);
12548  } // decode_OP_VOPC__V_CMP_GT_U32
12549 
12550  GPUStaticInst*
12552  {
12553  return new Inst_VOPC__V_CMP_NE_U32(&iFmt->iFmt_VOPC);
12554  } // decode_OP_VOPC__V_CMP_NE_U32
12555 
12556  GPUStaticInst*
12558  {
12559  return new Inst_VOPC__V_CMP_GE_U32(&iFmt->iFmt_VOPC);
12560  } // decode_OP_VOPC__V_CMP_GE_U32
12561 
12562  GPUStaticInst*
12564  {
12565  return new Inst_VOPC__V_CMP_T_U32(&iFmt->iFmt_VOPC);
12566  } // decode_OP_VOPC__V_CMP_T_U32
12567 
12568  GPUStaticInst*
12570  {
12571  return new Inst_VOPC__V_CMPX_F_I32(&iFmt->iFmt_VOPC);
12572  } // decode_OP_VOPC__V_CMPX_F_I32
12573 
12574  GPUStaticInst*
12576  {
12577  return new Inst_VOPC__V_CMPX_LT_I32(&iFmt->iFmt_VOPC);
12578  } // decode_OP_VOPC__V_CMPX_LT_I32
12579 
12580  GPUStaticInst*
12582  {
12583  return new Inst_VOPC__V_CMPX_EQ_I32(&iFmt->iFmt_VOPC);
12584  } // decode_OP_VOPC__V_CMPX_EQ_I32
12585 
12586  GPUStaticInst*
12588  {
12589  return new Inst_VOPC__V_CMPX_LE_I32(&iFmt->iFmt_VOPC);
12590  } // decode_OP_VOPC__V_CMPX_LE_I32
12591 
12592  GPUStaticInst*
12594  {
12595  return new Inst_VOPC__V_CMPX_GT_I32(&iFmt->iFmt_VOPC);
12596  } // decode_OP_VOPC__V_CMPX_GT_I32
12597 
12598  GPUStaticInst*
12600  {
12601  return new Inst_VOPC__V_CMPX_NE_I32(&iFmt->iFmt_VOPC);
12602  } // decode_OP_VOPC__V_CMPX_NE_I32
12603 
12604  GPUStaticInst*
12606  {
12607  return new Inst_VOPC__V_CMPX_GE_I32(&iFmt->iFmt_VOPC);
12608  } // decode_OP_VOPC__V_CMPX_GE_I32
12609 
12610  GPUStaticInst*
12612  {
12613  return new Inst_VOPC__V_CMPX_T_I32(&iFmt->iFmt_VOPC);
12614  } // decode_OP_VOPC__V_CMPX_T_I32
12615 
12616  GPUStaticInst*
12618  {
12619  return new Inst_VOPC__V_CMPX_F_U32(&iFmt->iFmt_VOPC);
12620  } // decode_OP_VOPC__V_CMPX_F_U32
12621 
12622  GPUStaticInst*
12624  {
12625  return new Inst_VOPC__V_CMPX_LT_U32(&iFmt->iFmt_VOPC);
12626  } // decode_OP_VOPC__V_CMPX_LT_U32
12627 
12628  GPUStaticInst*
12630  {
12631  return new Inst_VOPC__V_CMPX_EQ_U32(&iFmt->iFmt_VOPC);
12632  } // decode_OP_VOPC__V_CMPX_EQ_U32
12633 
12634  GPUStaticInst*
12636  {
12637  return new Inst_VOPC__V_CMPX_LE_U32(&iFmt->iFmt_VOPC);
12638  } // decode_OP_VOPC__V_CMPX_LE_U32
12639 
12640  GPUStaticInst*
12642  {
12643  return new Inst_VOPC__V_CMPX_GT_U32(&iFmt->iFmt_VOPC);
12644  } // decode_OP_VOPC__V_CMPX_GT_U32
12645 
12646  GPUStaticInst*
12648  {
12649  return new Inst_VOPC__V_CMPX_NE_U32(&iFmt->iFmt_VOPC);
12650  } // decode_OP_VOPC__V_CMPX_NE_U32
12651 
12652  GPUStaticInst*
12654  {
12655  return new Inst_VOPC__V_CMPX_GE_U32(&iFmt->iFmt_VOPC);
12656  } // decode_OP_VOPC__V_CMPX_GE_U32
12657 
12658  GPUStaticInst*
12660  {
12661  return new Inst_VOPC__V_CMPX_T_U32(&iFmt->iFmt_VOPC);
12662  } // decode_OP_VOPC__V_CMPX_T_U32
12663 
12664  GPUStaticInst*
12666  {
12667  return new Inst_VOPC__V_CMP_F_I64(&iFmt->iFmt_VOPC);
12668  } // decode_OP_VOPC__V_CMP_F_I64
12669 
12670  GPUStaticInst*
12672  {
12673  return new Inst_VOPC__V_CMP_LT_I64(&iFmt->iFmt_VOPC);
12674  } // decode_OP_VOPC__V_CMP_LT_I64
12675 
12676  GPUStaticInst*
12678  {
12679  return new Inst_VOPC__V_CMP_EQ_I64(&iFmt->iFmt_VOPC);
12680  } // decode_OP_VOPC__V_CMP_EQ_I64
12681 
12682  GPUStaticInst*
12684  {
12685  return new Inst_VOPC__V_CMP_LE_I64(&iFmt->iFmt_VOPC);
12686  } // decode_OP_VOPC__V_CMP_LE_I64
12687 
12688  GPUStaticInst*
12690  {
12691  return new Inst_VOPC__V_CMP_GT_I64(&iFmt->iFmt_VOPC);
12692  } // decode_OP_VOPC__V_CMP_GT_I64
12693 
12694  GPUStaticInst*
12696  {
12697  return new Inst_VOPC__V_CMP_NE_I64(&iFmt->iFmt_VOPC);
12698  } // decode_OP_VOPC__V_CMP_NE_I64
12699 
12700  GPUStaticInst*
12702  {
12703  return new Inst_VOPC__V_CMP_GE_I64(&iFmt->iFmt_VOPC);
12704  } // decode_OP_VOPC__V_CMP_GE_I64
12705 
12706  GPUStaticInst*
12708  {
12709  return new Inst_VOPC__V_CMP_T_I64(&iFmt->iFmt_VOPC);
12710  } // decode_OP_VOPC__V_CMP_T_I64
12711 
12712  GPUStaticInst*
12714  {
12715  return new Inst_VOPC__V_CMP_F_U64(&iFmt->iFmt_VOPC);
12716  } // decode_OP_VOPC__V_CMP_F_U64
12717 
12718  GPUStaticInst*
12720  {
12721  return new Inst_VOPC__V_CMP_LT_U64(&iFmt->iFmt_VOPC);
12722  } // decode_OP_VOPC__V_CMP_LT_U64
12723 
12724  GPUStaticInst*
12726  {
12727  return new Inst_VOPC__V_CMP_EQ_U64(&iFmt->iFmt_VOPC);
12728  } // decode_OP_VOPC__V_CMP_EQ_U64
12729 
12730  GPUStaticInst*
12732  {
12733  return new Inst_VOPC__V_CMP_LE_U64(&iFmt->iFmt_VOPC);
12734  } // decode_OP_VOPC__V_CMP_LE_U64
12735 
12736  GPUStaticInst*
12738  {
12739  return new Inst_VOPC__V_CMP_GT_U64(&iFmt->iFmt_VOPC);
12740  } // decode_OP_VOPC__V_CMP_GT_U64
12741 
12742  GPUStaticInst*
12744  {
12745  return new Inst_VOPC__V_CMP_NE_U64(&iFmt->iFmt_VOPC);
12746  } // decode_OP_VOPC__V_CMP_NE_U64
12747 
12748  GPUStaticInst*
12750  {
12751  return new Inst_VOPC__V_CMP_GE_U64(&iFmt->iFmt_VOPC);
12752  } // decode_OP_VOPC__V_CMP_GE_U64
12753 
12754  GPUStaticInst*
12756  {
12757  return new Inst_VOPC__V_CMP_T_U64(&iFmt->iFmt_VOPC);
12758  } // decode_OP_VOPC__V_CMP_T_U64
12759 
12760  GPUStaticInst*
12762  {
12763  return new Inst_VOPC__V_CMPX_F_I64(&iFmt->iFmt_VOPC);
12764  } // decode_OP_VOPC__V_CMPX_F_I64
12765 
12766  GPUStaticInst*
12768  {
12769  return new Inst_VOPC__V_CMPX_LT_I64(&iFmt->iFmt_VOPC);
12770  } // decode_OP_VOPC__V_CMPX_LT_I64
12771 
12772  GPUStaticInst*
12774  {
12775  return new Inst_VOPC__V_CMPX_EQ_I64(&iFmt->iFmt_VOPC);
12776  } // decode_OP_VOPC__V_CMPX_EQ_I64
12777 
12778  GPUStaticInst*
12780  {
12781  return new Inst_VOPC__V_CMPX_LE_I64(&iFmt->iFmt_VOPC);
12782  } // decode_OP_VOPC__V_CMPX_LE_I64
12783 
12784  GPUStaticInst*
12786  {
12787  return new Inst_VOPC__V_CMPX_GT_I64(&iFmt->iFmt_VOPC);
12788  } // decode_OP_VOPC__V_CMPX_GT_I64
12789 
12790  GPUStaticInst*
12792  {
12793  return new Inst_VOPC__V_CMPX_NE_I64(&iFmt->iFmt_VOPC);
12794  } // decode_OP_VOPC__V_CMPX_NE_I64
12795 
12796  GPUStaticInst*
12798  {
12799  return new Inst_VOPC__V_CMPX_GE_I64(&iFmt->iFmt_VOPC);
12800  } // decode_OP_VOPC__V_CMPX_GE_I64
12801 
12802  GPUStaticInst*
12804  {
12805  return new Inst_VOPC__V_CMPX_T_I64(&iFmt->iFmt_VOPC);
12806  } // decode_OP_VOPC__V_CMPX_T_I64
12807 
12808  GPUStaticInst*
12810  {
12811  return new Inst_VOPC__V_CMPX_F_U64(&iFmt->iFmt_VOPC);
12812  } // decode_OP_VOPC__V_CMPX_F_U64
12813 
12814  GPUStaticInst*
12816  {
12817  return new Inst_VOPC__V_CMPX_LT_U64(&iFmt->iFmt_VOPC);
12818  } // decode_OP_VOPC__V_CMPX_LT_U64
12819 
12820  GPUStaticInst*
12822  {
12823  return new Inst_VOPC__V_CMPX_EQ_U64(&iFmt->iFmt_VOPC);
12824  } // decode_OP_VOPC__V_CMPX_EQ_U64
12825 
12826  GPUStaticInst*
12828  {
12829  return new Inst_VOPC__V_CMPX_LE_U64(&iFmt->iFmt_VOPC);
12830  } // decode_OP_VOPC__V_CMPX_LE_U64
12831 
12832  GPUStaticInst*
12834  {
12835  return new Inst_VOPC__V_CMPX_GT_U64(&iFmt->iFmt_VOPC);
12836  } // decode_OP_VOPC__V_CMPX_GT_U64
12837 
12838  GPUStaticInst*
12840  {
12841  return new Inst_VOPC__V_CMPX_NE_U64(&iFmt->iFmt_VOPC);
12842  } // decode_OP_VOPC__V_CMPX_NE_U64
12843 
12844  GPUStaticInst*
12846  {
12847  return new Inst_VOPC__V_CMPX_GE_U64(&iFmt->iFmt_VOPC);
12848  } // decode_OP_VOPC__V_CMPX_GE_U64
12849 
12850  GPUStaticInst*
12852  {
12853  return new Inst_VOPC__V_CMPX_T_U64(&iFmt->iFmt_VOPC);
12854  } // decode_OP_VOPC__V_CMPX_T_U64
12855 
12856  GPUStaticInst*
12858  {
12859  fatal("Trying to decode instruction without a class\n");
12860  return nullptr;
12861  }
12862 
12863  GPUStaticInst*
12865  {
12866  fatal("Trying to decode instruction without a class\n");
12867  return nullptr;
12868  }
12869 
12870  GPUStaticInst*
12872  {
12873  fatal("Trying to decode instruction without a class\n");
12874  return nullptr;
12875  }
12876 
12877  GPUStaticInst*
12879  {
12880  fatal("Trying to decode instruction without a class\n");
12881  return nullptr;
12882  }
12883 
12884  GPUStaticInst*
12886  {
12887  fatal("Trying to decode instruction without a class\n");
12888  return nullptr;
12889  }
12890 
12891  GPUStaticInst*
12893  {
12894  fatal("Trying to decode instruction without a class\n");
12895  return nullptr;
12896  }
12897 
12898  GPUStaticInst*
12900  {
12901  fatal("Trying to decode instruction without a class\n");
12902  return nullptr;
12903  }
12904 
12905  GPUStaticInst*
12907  {
12908  fatal("Trying to decode instruction without a class\n");
12909  return nullptr;
12910  }
12911 
12912  GPUStaticInst*
12914  {
12915  fatal("Trying to decode instruction without a class\n");
12916  return nullptr;
12917  }
12918 
12919  GPUStaticInst*
12921  {
12922  fatal("Trying to decode instruction without a class\n");
12923  return nullptr;
12924  }
12925 
12926  GPUStaticInst*
12928  {
12929  fatal("Trying to decode instruction without a class\n");
12930  return nullptr;
12931  }
12932 
12933  GPUStaticInst*
12935  {
12936  fatal("Trying to decode instruction without a class\n");
12937  return nullptr;
12938  }
12939 
12940  GPUStaticInst*
12942  {
12943  fatal("Trying to decode instruction without a class\n");
12944  return nullptr;
12945  }
12946 
12947  GPUStaticInst*
12949  {
12950  fatal("Trying to decode instruction without a class\n");
12951  return nullptr;
12952  }
12953 
12954  GPUStaticInst*
12956  {
12957  fatal("Trying to decode instruction without a class\n");
12958  return nullptr;
12959  }
12960 
12961  GPUStaticInst*
12963  {
12964  fatal("Trying to decode instruction without a class\n");
12965  return nullptr;
12966  }
12967 
12968  GPUStaticInst*
12970  {
12971  fatal("Trying to decode instruction without a class\n");
12972  return nullptr;
12973  }
12974 
12975  GPUStaticInst*
12977  {
12978  fatal("Trying to decode instruction without a class\n");
12979  return nullptr;
12980  }
12981 
12982  GPUStaticInst*
12984  {
12985  fatal("Trying to decode instruction without a class\n");
12986  return nullptr;
12987  }
12988 
12989  GPUStaticInst*
12991  {
12992  fatal("Trying to decode instruction without a class\n");
12993  return nullptr;
12994  }
12995 
12996  GPUStaticInst*
12998  {
12999  fatal("Trying to decode instruction without a class\n");
13000  return nullptr;
13001  }
13002 
13003  GPUStaticInst*
13005  {
13006  fatal("Trying to decode instruction without a class\n");
13007  return nullptr;
13008  }
13009 
13010  GPUStaticInst*
13012  {
13013  fatal("Invalid opcode encountered: %#x\n", iFmt->imm_u32);
13014 
13015  return nullptr;
13016  }
13017 } // namespace VegaISA
13018 } // namespace gem5
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX3
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX3(MachInst)
Definition: decoder.cc:8248
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F16(MachInst)
Definition: decoder.cc:11759
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_F16
GPUStaticInst * decode_OPU_VOP3__V_MUL_F16(MachInst)
Definition: decoder.cc:6014
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2
Definition: instructions.hh:42691
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U8_D16
GPUStaticInst * decode_OP_DS__DS_READ_U8_D16(MachInst)
Definition: decoder.cc:7705
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG2_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG2_RTN_B64(MachInst)
Definition: decoder.cc:7831
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I64
Definition: instructions.hh:16717
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:8392
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:8380
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SENDMSGHALT
GPUStaticInst * decode_OP_SOPP__S_SENDMSGHALT(MachInst)
Definition: decoder.cc:11093
gem5::VegaISA::Inst_SOP2__S_ADD_U32
Definition: instructions.hh:45
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LE_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LE_I32(MachInst)
Definition: decoder.cc:10901
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F64(MachInst)
Definition: decoder.cc:5186
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LOG_F16
GPUStaticInst * decode_OPU_VOP3__V_LOG_F16(MachInst)
Definition: decoder.cc:6470
gem5::VegaISA::Inst_SOPP__S_CBRANCH_SCC1
Definition: instructions.hh:4569
gem5::VegaISA::Inst_VOP3__V_ADD_F64
Definition: instructions.hh:30163
gem5::VegaISA::Decoder::tableSubDecode_OP_MIMG
static IsaDecodeMethod tableSubDecode_OP_MIMG[128]
Definition: gpu_decoder.hh:66
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GET_LOD
GPUStaticInst * decode_OP_MIMG__IMAGE_GET_LOD(MachInst)
Definition: decoder.cc:9256
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I16(MachInst)
Definition: decoder.cc:5372
gem5::VegaISA::Inst_VOP1__V_RNDNE_F64
Definition: instructions.hh:8829
gem5::VegaISA::Inst_VOP1__V_CLREXCP
Definition: instructions.hh:9725
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I32(MachInst)
Definition: decoder.cc:5468
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFM_B64
GPUStaticInst * decode_OP_SOP2__S_BFM_B64(MachInst)
Definition: decoder.cc:4385
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F64(MachInst)
Definition: decoder.cc:12197
gem5::VegaISA::Decoder::decode_OP_SOPK__S_SETREG_B32
GPUStaticInst * decode_OP_SOPK__S_SETREG_B32(MachInst)
Definition: decoder.cc:4609
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F32
Definition: instructions.hh:18689
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I64(MachInst)
Definition: decoder.cc:5732
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I32(MachInst)
Definition: decoder.cc:12509
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_O_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F32(MachInst)
Definition: decoder.cc:12035
gem5::VegaISA::Inst_VOP3__V_MED3_I32
Definition: instructions.hh:28803
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U64
Definition: instructions.hh:16445
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_SEMA_P
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_P(MachInst)
Definition: decoder.cc:8011
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F16
Definition: instructions.hh:11209
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F32
Definition: instructions.hh:12399
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_D
Definition: instructions.hh:39631
gem5::VegaISA::Decoder::decode_OP_SOP1__S_WQM_B32
GPUStaticInst * decode_OP_SOP1__S_WQM_B32(MachInst)
Definition: decoder.cc:10578
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F16
Definition: instructions.hh:11107
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I64(MachInst)
Definition: decoder.cc:12695
gem5::VegaISA::Inst_SOP2__S_OR_B64
Definition: instructions.hh:555
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LG_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_U32(MachInst)
Definition: decoder.cc:10913
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_SRC2_U64(MachInst)
Definition: decoder.cc:8060
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F32(MachInst)
Definition: decoder.cc:4958
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I64
Definition: instructions.hh:16139
gem5::VegaISA::InFmt_VINTRP::OP
unsigned int OP
Definition: gpu_decoder.hh:1780
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_O(MachInst)
Definition: decoder.cc:9025
gem5::VegaISA::Inst_VOP3__V_BFM_B32
Definition: instructions.hh:30775
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F16_U16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_U16(MachInst)
Definition: decoder.cc:6428
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SUB_X2
Definition: instructions.hh:37467
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I16
Definition: instructions.hh:14473
gem5::VegaISA::Decoder::decode_OP_SOP1__S_WQM_B64
GPUStaticInst * decode_OP_SOP1__S_WQM_B64(MachInst)
Definition: decoder.cc:10584
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_SBYTE
Definition: instructions.hh:36297
gem5::VegaISA::Decoder::decode_OP_DS__DS_MSKOR_B64
GPUStaticInst * decode_OP_DS__DS_MSKOR_B64(MachInst)
Definition: decoder.cc:7643
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F64(MachInst)
Definition: decoder.cc:12167
gem5::VegaISA::Inst_VOP3__V_MED3_F32
Definition: instructions.hh:28767
gem5::VegaISA::Decoder::decode_OP_SOP1__S_OR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_OR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10740
gem5::VegaISA::Inst_VOP3__V_SQRT_F16
Definition: instructions.hh:27495
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F16
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F16(MachInst)
Definition: decoder.cc:6482
gem5::VegaISA::Inst_DS__DS_OR_RTN_B64
Definition: instructions.hh:33827
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_AND_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:8428
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2
Definition: instructions.hh:37539
gem5::VegaISA::Inst_VOP2__V_SUB_U32
Definition: instructions.hh:7965
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:9973
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_CL_O
Definition: instructions.hh:40891
gem5::VegaISA::Decoder::decode_OP_SOP1__S_XOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_XOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10746
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SQRT_F32
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F32(MachInst)
Definition: decoder.cc:6338
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F32(MachInst)
Definition: decoder.cc:4640
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SWAP
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:8821
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F64
Definition: instructions.hh:12875
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F32(MachInst)
Definition: decoder.cc:11999
gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B64
Definition: instructions.hh:2789
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ
Definition: instructions.hh:38055
gem5::VegaISA::Inst_DS__DS_INC_SRC2_U64
Definition: instructions.hh:35155
gem5::VegaISA::Inst_VOP3__V_CLREXCP
Definition: instructions.hh:27307
gem5::VegaISA::Inst_VOP3__V_CEIL_F64
Definition: instructions.hh:26379
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F16
Definition: instructions.hh:18111
gem5::VegaISA::Inst_VOP3__V_MUL_LEGACY_F32
Definition: instructions.hh:24097
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_U32(MachInst)
Definition: decoder.cc:7240
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CEIL_F64
GPUStaticInst * decode_OP_VOP1__V_CEIL_F64(MachInst)
Definition: decoder.cc:11334
gem5::VegaISA::Inst_VINTRP__V_INTERP_P1_F32
Definition: instructions.hh:17125
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFE_U64
GPUStaticInst * decode_OP_SOP2__S_BFE_U64(MachInst)
Definition: decoder.cc:4409
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U64(MachInst)
Definition: decoder.cc:5708
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:8488
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX
Definition: instructions.hh:42395
gem5::VegaISA::Inst_SOP2__S_MAX_U32
Definition: instructions.hh:351
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F64
Definition: instructions.hh:19947
gem5::VegaISA::Inst_DS__DS_GWS_BARRIER
Definition: instructions.hh:34937
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I16(MachInst)
Definition: decoder.cc:12401
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F16(MachInst)
Definition: decoder.cc:11885
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I16
Definition: instructions.hh:21375
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I32(MachInst)
Definition: decoder.cc:5570
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B64
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B64(MachInst)
Definition: decoder.cc:7125
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U32
Definition: instructions.hh:15323
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2
Definition: instructions.hh:37575
gem5::VegaISA::InFmt_SMEM
Definition: gpu_decoder.hh:1723
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_L_O
Definition: instructions.hh:39991
gem5::VegaISA::Inst_SOP2__S_LSHR_B64
Definition: instructions.hh:1099
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U64
Definition: instructions.hh:16853
gem5::VegaISA::Inst_VOP3__V_LERP_U8
Definition: instructions.hh:28443
gem5::VegaISA::Inst_DS__DS_CONSUME
Definition: instructions.hh:34969
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SUB
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SUB(MachInst)
Definition: decoder.cc:9637
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MBCNT_HI_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_MBCNT_HI_U32_B32(MachInst)
Definition: decoder.cc:7113
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX2
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9533
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FF0_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FF0_I32_B32(MachInst)
Definition: decoder.cc:10626
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX3
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:9539
gem5::VegaISA::Inst_VOP3__V_MAD_U16
Definition: instructions.hh:29713
gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_I64
Definition: instructions.hh:2853
gem5::VegaISA::Inst_VOP1__V_CVT_U32_F32
Definition: instructions.hh:8253
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BCNT1_I32_B32
GPUStaticInst * decode_OP_SOP1__S_BCNT1_I32_B32(MachInst)
Definition: decoder.cc:10614
gem5::VegaISA::Decoder::decode_OP_SOP2__S_CBRANCH_G_FORK
GPUStaticInst * decode_OP_SOP2__S_CBRANCH_G_FORK(MachInst)
Definition: decoder.cc:4421
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SETPC_B64
GPUStaticInst * decode_OP_SOP1__S_SETPC_B64(MachInst)
Definition: decoder.cc:10716
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_SHORT
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_SHORT(MachInst)
Definition: decoder.cc:8519
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:9491
gem5::VegaISA::Inst_DS__DS_CMPST_B32
Definition: instructions.hh:31501
gem5::VegaISA::Decoder::decode_OP_VINTRP__V_INTERP_MOV_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_MOV_F32(MachInst)
Definition: decoder.cc:11190
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_CL
Definition: instructions.hh:41431
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:9739
gem5::VegaISA::Decoder::tableSubDecode_OP_SOP1
static IsaDecodeMethod tableSubDecode_OP_SOP1[256]
Definition: gpu_decoder.hh:71
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F64
Definition: instructions.hh:17329
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORD
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORD(MachInst)
Definition: decoder.cc:8236
gem5::VegaISA::Inst_VOP1__V_SIN_F16
Definition: instructions.hh:10265
gem5::VegaISA::Inst_VOP1__V_CVT_I32_F64
Definition: instructions.hh:8125
gem5::VegaISA::Inst_DS__DS_READ_B96
Definition: instructions.hh:35579
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I16
Definition: instructions.hh:14031
gem5::VegaISA::Inst_DS__DS_MAX_RTN_I32
Definition: instructions.hh:31963
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_U_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F32(MachInst)
Definition: decoder.cc:4910
gem5::VegaISA::Inst_DS__DS_BPERMUTE_B32
Definition: instructions.hh:32807
gem5::VegaISA::Inst_VOP3__V_ASHRREV_I64
Definition: instructions.hh:30707
gem5::VegaISA::Inst_DS__DS_ADD_SRC2_U32
Definition: instructions.hh:34303
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F16(MachInst)
Definition: decoder.cc:4826
gem5::VegaISA::Inst_DS__DS_CMPST_F32
Definition: instructions.hh:31533
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F16
Definition: instructions.hh:18145
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:9709
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_F64(MachInst)
Definition: decoder.cc:11280
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I32(MachInst)
Definition: decoder.cc:12503
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RCP_F64
GPUStaticInst * decode_OPU_VOP3__V_RCP_F64(MachInst)
Definition: decoder.cc:6326
gem5::VegaISA::Inst_VOP3__V_FLOOR_F64
Definition: instructions.hh:26443
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16(MachInst)
Definition: decoder.cc:9887
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOVRELD_B32
GPUStaticInst * decode_OP_SOP1__S_MOVRELD_B32(MachInst)
Definition: decoder.cc:10806
gem5::VegaISA::Inst_VOP3__V_MAD_I32_I24
Definition: instructions.hh:28047
gem5::VegaISA::Inst_DS__DS_MAX_RTN_F32
Definition: instructions.hh:32405
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CL
Definition: instructions.hh:39595
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ2ST64_B64
GPUStaticInst * decode_OP_DS__DS_READ2ST64_B64(MachInst)
Definition: decoder.cc:7879
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_B32
GPUStaticInst * decode_OP_DS__DS_AND_B32(MachInst)
Definition: decoder.cc:7282
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F64(MachInst)
Definition: decoder.cc:5156
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_DWORDX4
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_DWORDX4(MachInst)
Definition: decoder.cc:8551
gem5::VegaISA::Decoder::decode_OP_SOPK__S_MOVK_I32
GPUStaticInst * decode_OP_SOPK__S_MOVK_I32(MachInst)
Definition: decoder.cc:4501
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_F32
GPUStaticInst * decode_OPU_VOP3__V_SUB_F32(MachInst)
Definition: decoder.cc:5834
gem5::VegaISA::Inst_DS__DS_READ2ST64_B64
Definition: instructions.hh:34235
gem5::VegaISA::Inst_VOP3__V_CVT_I32_F64
Definition: instructions.hh:25707
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_INC
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_INC(MachInst)
Definition: decoder.cc:10255
gem5::VegaISA::Inst_DS__DS_WRITE_B8
Definition: instructions.hh:31691
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F32
Definition: instructions.hh:12297
gem5::VegaISA::Decoder::subDecode_OP_SOP1
GPUStaticInst * subDecode_OP_SOP1(MachInst)
Definition: decoder.cc:3744
gem5::VegaISA::Inst_VOP3__V_CVT_U32_F32
Definition: instructions.hh:25835
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_PKNORM_I16_F16
GPUStaticInst * decode_OPU_VOP3__V_PKNORM_I16_F16(MachInst)
Definition: decoder.cc:7179
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_U32_U24
GPUStaticInst * decode_OP_VOP2__V_MUL_U32_U24(MachInst)
Definition: decoder.cc:3893
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X(MachInst)
Definition: decoder.cc:9407
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F32(MachInst)
Definition: decoder.cc:11951
gem5::VegaISA::Inst_VOP2__V_LSHRREV_B16
Definition: instructions.hh:7625
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR_X2
Definition: instructions.hh:42991
gem5::VegaISA::Inst_DS__DS_GWS_SEMA_P
Definition: instructions.hh:34907
gem5::VegaISA::Inst_VOP3__V_BFI_B32
Definition: instructions.hh:28335
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_UBYTE_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_UBYTE_D16_HI(MachInst)
Definition: decoder.cc:8267
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_F16(MachInst)
Definition: decoder.cc:6170
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SBYTE
Definition: instructions.hh:41686
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SET_GPR_IDX_MODE
GPUStaticInst * decode_OP_SOPP__S_SET_GPR_IDX_MODE(MachInst)
Definition: decoder.cc:11165
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FLOOR_F64
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F64(MachInst)
Definition: decoder.cc:11346
gem5::VegaISA::Inst_SOPP__S_CBRANCH_VCCZ
Definition: instructions.hh:4599
gem5::VegaISA::Decoder::decode_OP_VOP1__V_TRUNC_F64
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F64(MachInst)
Definition: decoder.cc:11328
gem5::VegaISA::Inst_VOP3__V_RSQ_F16
Definition: instructions.hh:27527
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:8398
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F64(MachInst)
Definition: decoder.cc:5222
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I32
Definition: instructions.hh:15561
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CEIL_F16
GPUStaticInst * decode_OP_VOP1__V_CEIL_F16(MachInst)
Definition: decoder.cc:11593
gem5::VegaISA::Inst_VOP3__V_RCP_F16
Definition: instructions.hh:27463
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:10297
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_U32
Definition: instructions.hh:34513
gem5::VegaISA::Decoder::decode_OP_SOPP__S_BARRIER
GPUStaticInst * decode_OP_SOPP__S_BARRIER(MachInst)
Definition: decoder.cc:11051
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_I32
GPUStaticInst * decode_OP_VOP2__V_MAX_I32(MachInst)
Definition: decoder.cc:3923
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_TRUNC_F32
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F32(MachInst)
Definition: decoder.cc:6272
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MUL_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_MUL_F16(MachInst)
Definition: decoder.cc:12969
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOVRELS_B64
GPUStaticInst * decode_OP_SOP1__S_MOVRELS_B64(MachInst)
Definition: decoder.cc:10800
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SWAP
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:8302
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F64(MachInst)
Definition: decoder.cc:5054
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B8_D16_HI
GPUStaticInst * decode_OP_DS__DS_WRITE_B8_D16_HI(MachInst)
Definition: decoder.cc:7691
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U16(MachInst)
Definition: decoder.cc:12365
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_U16
GPUStaticInst * decode_OPU_VOP3__V_MAD_U16(MachInst)
Definition: decoder.cc:6968
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_U32(MachInst)
Definition: decoder.cc:7939
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MOV_FED_B32
GPUStaticInst * decode_OPU_VOP3__V_MOV_FED_B32(MachInst)
Definition: decoder.cc:6158
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I64(MachInst)
Definition: decoder.cc:12665
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHL_ADD_U32
GPUStaticInst * decode_OPU_VOP3__V_LSHL_ADD_U32(MachInst)
Definition: decoder.cc:6926
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_U_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F32(MachInst)
Definition: decoder.cc:12041
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X(MachInst)
Definition: decoder.cc:9334
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_UMAX
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:10409
gem5::VegaISA::Inst_VOP2__V_LSHLREV_B16
Definition: instructions.hh:7591
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ2_B32
GPUStaticInst * decode_OP_DS__DS_READ2_B32(MachInst)
Definition: decoder.cc:7517
gem5::VegaISA::Inst_DS__DS_AND_SRC2_B64
Definition: instructions.hh:35335
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F16(MachInst)
Definition: decoder.cc:11891
gem5::VegaISA::Inst_VOP1__V_FREXP_MANT_F32
Definition: instructions.hh:9693
gem5::VegaISA::Inst_SOP2__S_CSELECT_B32
Definition: instructions.hh:385
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_U32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_U32_F64(MachInst)
Definition: decoder.cc:11316
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U32(MachInst)
Definition: decoder.cc:12551
gem5::VegaISA::Inst_VOP2__V_MADAK_F32
Definition: instructions.hh:6957
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_O_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F16(MachInst)
Definition: decoder.cc:11843
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_STORE_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_STORE_DWORDX2(MachInst)
Definition: decoder.cc:10035
gem5::VegaISA::Inst_VOP3__V_ALIGNBYTE_B32
Definition: instructions.hh:28515
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F64
Definition: instructions.hh:20117
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U64
Definition: instructions.hh:23687
gem5::VegaISA::InstFormat::iFmt_VOP3P
InFmt_VOP3P iFmt_VOP3P
Definition: gpu_decoder.hh:1932
gem5::VegaISA::InFmt_SOP1::OP
unsigned int OP
Definition: gpu_decoder.hh:1743
gem5::VegaISA::Inst_VOP1__V_FREXP_MANT_F64
Definition: instructions.hh:9597
gem5::VegaISA::Inst_SOP2__S_ASHR_I64
Definition: instructions.hh:1167
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_OR
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_OR(MachInst)
Definition: decoder.cc:10423
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_F32
GPUStaticInst * decode_OP_DS__DS_MIN_F32(MachInst)
Definition: decoder.cc:7336
gem5::VegaISA::Decoder::decode_OP_DS__DS_PERMUTE_B32
GPUStaticInst * decode_OP_DS__DS_PERMUTE_B32(MachInst)
Definition: decoder.cc:7559
gem5::VegaISA::Inst_VOP1__V_RCP_F64
Definition: instructions.hh:9213
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:10353
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_INC
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_INC(MachInst)
Definition: decoder.cc:8887
gem5::VegaISA::Inst_VOP1__V_LOG_F16
Definition: instructions.hh:9977
gem5::VegaISA::Inst_SOPC__S_SETVSKIP
Definition: instructions.hh:4291
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX
Definition: instructions.hh:42432
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I64
Definition: instructions.hh:22973
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RSQ_F64
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F64(MachInst)
Definition: decoder.cc:6332
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_F64
GPUStaticInst * decode_OP_DS__DS_MAX_F64(MachInst)
Definition: decoder.cc:7685
gem5::VegaISA::Inst_VOP3__V_NOP
Definition: instructions.hh:25647
gem5::VegaISA::Inst_SOP2__S_BFM_B32
Definition: instructions.hh:1201
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SEXT_I32_I16
GPUStaticInst * decode_OP_SOP1__S_SEXT_I32_I16(MachInst)
Definition: decoder.cc:10680
gem5::VegaISA::Inst_VOP1__V_CVT_F64_I32
Definition: instructions.hh:8157
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFE_I64
GPUStaticInst * decode_OP_SOP2__S_BFE_I64(MachInst)
Definition: decoder.cc:4415
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SHORT_D16
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SHORT_D16(MachInst)
Definition: decoder.cc:8288
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F64(MachInst)
Definition: decoder.cc:12275
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_I32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_I32(MachInst)
Definition: decoder.cc:7415
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PKNORM_U16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKNORM_U16_F32(MachInst)
Definition: decoder.cc:7155
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX4
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:8204
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_F16(MachInst)
Definition: decoder.cc:11256
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F32(MachInst)
Definition: decoder.cc:11909
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F64
Definition: instructions.hh:19709
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F64(MachInst)
Definition: decoder.cc:5198
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_F32
GPUStaticInst * decode_OPU_VOP3__V_MAD_F32(MachInst)
Definition: decoder.cc:6554
gem5::VegaISA::Inst_SOPP__S_CBRANCH_CDBGUSER
Definition: instructions.hh:5143
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FRACT_F32
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F32(MachInst)
Definition: decoder.cc:6266
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_OR_X2
Definition: instructions.hh:37683
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_OR
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_OR(MachInst)
Definition: decoder.cc:8356
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F32(MachInst)
Definition: decoder.cc:4922
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I32_F32(MachInst)
Definition: decoder.cc:6410
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_INC
Definition: instructions.hh:39203
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_ADD
Definition: instructions.hh:36963
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U64
Definition: instructions.hh:16887
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBB_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBB_CO_U32(MachInst)
Definition: decoder.cc:5984
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_F64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_F64(MachInst)
Definition: decoder.cc:8132
gem5::VegaISA::Inst_VOP1__V_LOG_LEGACY_F32
Definition: instructions.hh:10361
gem5::VegaISA::InFmt_SOPP::OP
unsigned int OP
Definition: gpu_decoder.hh:1772
gem5::VegaISA::Inst_VOP1__V_CVT_F64_F32
Definition: instructions.hh:8541
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORD
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORD(MachInst)
Definition: decoder.cc:9929
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CL(MachInst)
Definition: decoder.cc:8905
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFM_B32
GPUStaticInst * decode_OP_SOP2__S_BFM_B32(MachInst)
Definition: decoder.cc:4379
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SSHORT
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SSHORT(MachInst)
Definition: decoder.cc:8476
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHL_OR_B32
GPUStaticInst * decode_OPU_VOP3__V_LSHL_OR_B32(MachInst)
Definition: decoder.cc:6944
gem5::VegaISA::Inst_VOP3__V_CVT_F64_I32
Definition: instructions.hh:25739
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U16(MachInst)
Definition: decoder.cc:5294
gem5::VegaISA::Inst_VOP1__V_CVT_F32_F16
Definition: instructions.hh:8381
gem5::VegaISA::Inst_VOP3__V_CMP_T_U32
Definition: instructions.hh:22293
gem5::VegaISA::Inst_VOP3__V_CMP_F_U32
Definition: instructions.hh:22055
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F16
Definition: instructions.hh:11175
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
Definition: instructions.hh:38131
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F64
Definition: instructions.hh:13215
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I64(MachInst)
Definition: decoder.cc:12803
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XY
Definition: instructions.hh:35833
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_O_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F64(MachInst)
Definition: decoder.cc:12227
gem5::VegaISA::Decoder::tableSubDecode_OPU_VOP3
static IsaDecodeMethod tableSubDecode_OPU_VOP3[768]
Definition: gpu_decoder.hh:62
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_AND_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:10507
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I32
Definition: instructions.hh:15153
gem5::VegaISA::Decoder::decode_OP_SMEM__S_MEMREALTIME
GPUStaticInst * decode_OP_SMEM__S_MEMREALTIME(MachInst)
Definition: decoder.cc:10146
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9966
gem5::VegaISA::Inst_SOP2__S_AND_B64
Definition: instructions.hh:487
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAX_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAX_U16(MachInst)
Definition: decoder.cc:12941
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX3
Definition: instructions.hh:36723
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F64(MachInst)
Definition: decoder.cc:12245
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ(MachInst)
Definition: decoder.cc:9346
gem5::VegaISA::Inst_DS__DS_DEC_RTN_U64
Definition: instructions.hh:33623
gem5::VegaISA::Inst_VOP3__V_MQSAD_PK_U16_U8
Definition: instructions.hh:29349
gem5::VegaISA::Inst_VOP3__V_CVT_F64_F32
Definition: instructions.hh:26123
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_U_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F64(MachInst)
Definition: decoder.cc:5102
gpu_static_inst.hh
gem5::VegaISA::Inst_VOP3__V_CVT_PKNORM_I16_F32
Definition: instructions.hh:30809
gem5::VegaISA::Inst_VOP3__V_CVT_F32_F16
Definition: instructions.hh:25963
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:9697
gem5::VegaISA::Decoder::decode_OP_VOP1__V_NOP
GPUStaticInst * decode_OP_VOP1__V_NOP(MachInst)
Definition: decoder.cc:11196
gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32
Definition: instructions.hh:6991
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_LSHRREV_B16
GPUStaticInst * decode_OP_VOP3P__V_PK_LSHRREV_B16(MachInst)
Definition: decoder.cc:12892
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F16
Definition: instructions.hh:17907
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I16
Definition: instructions.hh:14439
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_F64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_F64(MachInst)
Definition: decoder.cc:7861
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_EQ_U64
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_U64(MachInst)
Definition: decoder.cc:10979
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I32(MachInst)
Definition: decoder.cc:12473
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I32(MachInst)
Definition: decoder.cc:5540
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SETHALT
GPUStaticInst * decode_OP_SOPP__S_SETHALT(MachInst)
Definition: decoder.cc:11069
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F64(MachInst)
Definition: decoder.cc:12263
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_RPI_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_RPI_I32_F32(MachInst)
Definition: decoder.cc:6176
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F32
Definition: instructions.hh:11889
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I16_F16
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I16_F16(MachInst)
Definition: decoder.cc:6488
gem5::VegaISA::Decoder::decode_OP_DS__DS_ORDERED_COUNT
GPUStaticInst * decode_OP_DS__DS_ORDERED_COUNT(MachInst)
Definition: decoder.cc:8042
gem5::VegaISA::Inst_VOP3__V_MAD_I16
Definition: instructions.hh:29749
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_UBYTE
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_UBYTE(MachInst)
Definition: decoder.cc:8162
gem5::VegaISA::InstFormat::iFmt_VINTRP
InFmt_VINTRP iFmt_VINTRP
Definition: gpu_decoder.hh:1922
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I16
Definition: instructions.hh:20865
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL_B64
GPUStaticInst * decode_OP_SOP2__S_LSHL_B64(MachInst)
Definition: decoder.cc:4349
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SSHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SSHORT(MachInst)
Definition: decoder.cc:9521
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_O(MachInst)
Definition: decoder.cc:9007
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RSQ_F32
GPUStaticInst * decode_OP_VOP1__V_RSQ_F32(MachInst)
Definition: decoder.cc:11406
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F64_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_F32(MachInst)
Definition: decoder.cc:11286
gem5::VegaISA::Inst_VOP3__V_FLOOR_F32
Definition: instructions.hh:26603
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F32(MachInst)
Definition: decoder.cc:12071
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16(MachInst)
Definition: decoder.cc:10079
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U64
Definition: instructions.hh:23245
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SHORT_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SHORT_D16_HI(MachInst)
Definition: decoder.cc:8295
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_STORE_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_STORE_DWORDX4(MachInst)
Definition: decoder.cc:10042
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F32
Definition: instructions.hh:12331
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I32_F64
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I32_F64(MachInst)
Definition: decoder.cc:6392
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER(MachInst)
Definition: decoder.cc:11141
gem5::VegaISA::Inst_VOP3__V_CMP_T_U64
Definition: instructions.hh:23381
gem5::VegaISA::Inst_DS__DS_INC_SRC2_U32
Definition: instructions.hh:34393
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BCNT_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_BCNT_U32_B32(MachInst)
Definition: decoder.cc:7101
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F16(MachInst)
Definition: decoder.cc:11819
gem5::VegaISA::Decoder::decode_OP_SOPP__S_TRAP
GPUStaticInst * decode_OP_SOPP__S_TRAP(MachInst)
Definition: decoder.cc:11099
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16_HI(MachInst)
Definition: decoder.cc:9908
gem5::VegaISA::Inst_VOP3__V_MAD_F16
Definition: instructions.hh:29677
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_I32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_I32(MachInst)
Definition: decoder.cc:7921
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_UMIN
Definition: instructions.hh:37071
gem5::VegaISA::Inst_VOP3__V_DIV_FIXUP_F64
Definition: instructions.hh:29091
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U16(MachInst)
Definition: decoder.cc:5330
gem5::VegaISA::Inst_SOP1__S_BITSET1_B64
Definition: instructions.hh:3045
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F64(MachInst)
Definition: decoder.cc:12161
gem5::VegaISA::Inst_VOP3__V_CMP_O_F16
Definition: instructions.hh:17669
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I32
Definition: instructions.hh:15595
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_U32
Definition: instructions.hh:34543
gem5::VegaISA::Inst_SOP1__S_XNOR_SAVEEXEC_B64
Definition: instructions.hh:3427
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U16
Definition: instructions.hh:21613
gem5::VegaISA::Inst_VOP2__V_SUBBREV_CO_U32
Definition: instructions.hh:7175
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I64(MachInst)
Definition: decoder.cc:12779
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U64(MachInst)
Definition: decoder.cc:5720
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F64
Definition: instructions.hh:12943
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_U32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_U32(MachInst)
Definition: decoder.cc:6674
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F16(MachInst)
Definition: decoder.cc:4700
gem5::VegaISA::Decoder::decode_OP_SOP2__S_XOR_B64
GPUStaticInst * decode_OP_SOP2__S_XOR_B64(MachInst)
Definition: decoder.cc:4277
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F32(MachInst)
Definition: decoder.cc:4994
gem5::VegaISA::Decoder::decode_OP_SOP2__S_XOR_B32
GPUStaticInst * decode_OP_SOP2__S_XOR_B32(MachInst)
Definition: decoder.cc:4271
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
Definition: instructions.hh:38321
gem5::VegaISA::Inst_DS__DS_AND_B64
Definition: instructions.hh:33129
gem5::VegaISA::Decoder::decode_OP_SOPP__S_DECPERFLEVEL
GPUStaticInst * decode_OP_SOPP__S_DECPERFLEVEL(MachInst)
Definition: decoder.cc:11117
gem5::VegaISA::Inst_SOP2__S_NOR_B64
Definition: instructions.hh:895
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CL
Definition: instructions.hh:39307
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F64
Definition: instructions.hh:13657
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE2_B32
GPUStaticInst * decode_OP_DS__DS_WRITE2_B32(MachInst)
Definition: decoder.cc:7312
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B16
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B16(MachInst)
Definition: decoder.cc:6050
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F64
Definition: instructions.hh:20015
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_I16
GPUStaticInst * decode_OPU_VOP3__V_MIN3_I16(MachInst)
Definition: decoder.cc:6870
gem5::VegaISA::Inst_VOP3__V_FREXP_EXP_I32_F32
Definition: instructions.hh:27243
gem5::VegaISA::Inst_SOP2__S_ADD_I32
Definition: instructions.hh:113
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U16
Definition: instructions.hh:14813
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:10479
gem5::VegaISA::Inst_DS__DS_MAX_RTN_U32
Definition: instructions.hh:32031
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:9625
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CUBEMA_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBEMA_F32(MachInst)
Definition: decoder.cc:6590
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_DWORDX2
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_DWORDX2(MachInst)
Definition: decoder.cc:9866
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SWAP
Definition: instructions.hh:36891
gem5::VegaISA::Inst_SOP2__S_CSELECT_B64
Definition: instructions.hh:419
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U32(MachInst)
Definition: decoder.cc:5498
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F32
Definition: instructions.hh:12161
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_UBYTE_D16
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_UBYTE_D16(MachInst)
Definition: decoder.cc:8260
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I32(MachInst)
Definition: decoder.cc:12497
gem5::VegaISA::Inst_SOP2__S_LSHL_B64
Definition: instructions.hh:1031
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_STORE_MIP_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_MIP_PCK(MachInst)
Definition: decoder.cc:8809
gem5::VegaISA::Inst_VOP3__V_COS_F16
Definition: instructions.hh:27879
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U64(MachInst)
Definition: decoder.cc:5714
gem5::VegaISA::Inst_DS__DS_WRITE_B64
Definition: instructions.hh:33257
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I32
Definition: instructions.hh:15085
gem5::VegaISA::Inst_VOP3__V_RSQ_F64
Definition: instructions.hh:26827
gem5::VegaISA::InstFormat::imm_u32
uint32_t imm_u32
Definition: gpu_decoder.hh:1934
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CNDMASK_B32
GPUStaticInst * decode_OPU_VOP3__V_CNDMASK_B32(MachInst)
Definition: decoder.cc:5822
gem5::VegaISA::Inst_SOP2__S_ADDC_U32
Definition: instructions.hh:181
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16(MachInst)
Definition: decoder.cc:10091
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_F32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_F32(MachInst)
Definition: decoder.cc:7493
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL3_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_LSHL3_ADD_U32(MachInst)
Definition: decoder.cc:4466
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_F64
Definition: instructions.hh:35455
gem5::VegaISA::Inst_SOP1__S_NOT_B32
Definition: instructions.hh:2309
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I64(MachInst)
Definition: decoder.cc:12761
gem5::VegaISA::Inst_VOP1__V_FFBL_B32
Definition: instructions.hh:9501
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U16
Definition: instructions.hh:21137
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U16(MachInst)
Definition: decoder.cc:5414
gem5::VegaISA::Decoder::decode_OP_VINTRP__V_INTERP_P1_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_P1_F32(MachInst)
Definition: decoder.cc:11178
gem5::VegaISA::Decoder::decode_OP_SOPP__S_WAITCNT
GPUStaticInst * decode_OP_SOPP__S_WAITCNT(MachInst)
Definition: decoder.cc:11063
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FRACT_F64
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F64(MachInst)
Definition: decoder.cc:6404
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U32(MachInst)
Definition: decoder.cc:5510
gem5::VegaISA::Inst_SOPK__S_SETREG_IMM32_B32
Definition: instructions.hh:2149
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_U16
GPUStaticInst * decode_OPU_VOP3__V_MIN_U16(MachInst)
Definition: decoder.cc:6092
gem5::VegaISA::InstFormat::iFmt_SOPP
InFmt_SOPP iFmt_SOPP
Definition: gpu_decoder.hh:1921
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_CL_O
Definition: instructions.hh:41107
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX3
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX3(MachInst)
Definition: decoder.cc:9589
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P2_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P2_F16(MachInst)
Definition: decoder.cc:7029
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F32
Definition: instructions.hh:11821
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SUB
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SUB(MachInst)
Definition: decoder.cc:8320
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_I64
Definition: instructions.hh:35215
gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE3
Definition: instructions.hh:26251
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_ADD_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_ADD_U16(MachInst)
Definition: decoder.cc:12927
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_F32
GPUStaticInst * decode_OP_DS__DS_ADD_F32(MachInst)
Definition: decoder.cc:7354
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F16(MachInst)
Definition: decoder.cc:11831
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_U32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_U32_F32(MachInst)
Definition: decoder.cc:11238
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_COS_F16
GPUStaticInst * decode_OPU_VOP3__V_COS_F16(MachInst)
Definition: decoder.cc:6530
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:10458
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F16
Definition: instructions.hh:18077
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX4
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:9545
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_DISCARD
GPUStaticInst * decode_OP_SMEM__S_DCACHE_DISCARD(MachInst)
Definition: decoder.cc:10164
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:8308
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CUBEID_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBEID_F32(MachInst)
Definition: decoder.cc:6572
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I64(MachInst)
Definition: decoder.cc:5726
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I32(MachInst)
Definition: decoder.cc:5450
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_U64
GPUStaticInst * decode_OP_DS__DS_DEC_U64(MachInst)
Definition: decoder.cc:7595
gem5::VegaISA::Inst_SOP2__S_MAX_I32
Definition: instructions.hh:317
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I16(MachInst)
Definition: decoder.cc:12311
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I32(MachInst)
Definition: decoder.cc:5438
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SIN_F16
GPUStaticInst * decode_OP_VOP1__V_SIN_F16(MachInst)
Definition: decoder.cc:11617
gem5::VegaISA::Decoder::decode_OP_SOPK__S_SETREG_IMM32_B32
GPUStaticInst * decode_OP_SOPK__S_SETREG_IMM32_B32(MachInst)
Definition: decoder.cc:4615
gem5::VegaISA::Inst_SOP1__S_ORN2_SAVEEXEC_B64
Definition: instructions.hh:3331
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX2
Definition: instructions.hh:5539
gem5::VegaISA::Inst_VOP2__V_SUB_F32
Definition: instructions.hh:6209
gem5::VegaISA::Inst_SOPC__S_CMP_EQ_I32
Definition: instructions.hh:3779
gem5::VegaISA::Inst_SOPK__S_ADDK_I32
Definition: instructions.hh:1989
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F32(MachInst)
Definition: decoder.cc:4976
gem5::VegaISA::Inst_DS__DS_DEC_U32
Definition: instructions.hh:31107
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I16
Definition: instructions.hh:21341
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F16(MachInst)
Definition: decoder.cc:11867
gem5::VegaISA::Inst_DS__DS_WRITE2_B64
Definition: instructions.hh:33291
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F32
Definition: instructions.hh:19335
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_WBINVL1_VOL
GPUStaticInst * decode_OP_MUBUF__BUFFER_WBINVL1_VOL(MachInst)
Definition: decoder.cc:9613
gem5::VegaISA::Inst_VOP2__V_MAX_U32
Definition: instructions.hh:6651
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F16
Definition: instructions.hh:11617
gem5::VegaISA::Inst_VOP3__V_MUL_HI_I32
Definition: instructions.hh:30401
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_U_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F16(MachInst)
Definition: decoder.cc:11753
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RSQ_F16
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F16(MachInst)
Definition: decoder.cc:6464
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I32
Definition: instructions.hh:21987
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:10227
gem5::VegaISA::InFmt_SMEM::OP
unsigned int OP
Definition: gpu_decoder.hh:1731
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:9461
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_B_CL_O
Definition: instructions.hh:40063
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_F16
GPUStaticInst * decode_OPU_VOP3__V_MED3_F16(MachInst)
Definition: decoder.cc:6905
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U64
Definition: instructions.hh:23891
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:9467
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BCNT0_I32_B32
GPUStaticInst * decode_OP_SOP1__S_BCNT0_I32_B32(MachInst)
Definition: decoder.cc:10602
gem5::VegaISA::Decoder::subDecode_OP_SMEM
GPUStaticInst * subDecode_OP_SMEM(MachInst)
Definition: decoder.cc:3768
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHR_B64
GPUStaticInst * decode_OP_SOP2__S_LSHR_B64(MachInst)
Definition: decoder.cc:4361
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F32(MachInst)
Definition: decoder.cc:11915
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_CMPSWAP
Definition: instructions.hh:38863
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F32
Definition: instructions.hh:18723
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE_D16
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE_D16(MachInst)
Definition: decoder.cc:8557
gem5::VegaISA::Decoder::tableSubDecode_OP_SOPC
static IsaDecodeMethod tableSubDecode_OP_SOPC[128]
Definition: gpu_decoder.hh:72
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:8737
gem5::VegaISA::Inst_SOPK__S_CMPK_EQ_U32
Definition: instructions.hh:1797
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F32
Definition: instructions.hh:12501
gem5::VegaISA::Inst_DS__DS_INC_U64
Definition: instructions.hh:32937
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:9400
gem5::VegaISA::Inst_VOP3__V_MIN3_U32
Definition: instructions.hh:28623
gem5::VegaISA::InFmt_VOP1::OP
unsigned int OP
Definition: gpu_decoder.hh:1787
gem5::VegaISA::Inst_SOPK__S_CMPK_LG_U32
Definition: instructions.hh:1829
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_XAD_U32
GPUStaticInst * decode_OPU_VOP3__V_XAD_U32(MachInst)
Definition: decoder.cc:6856
gem5::VegaISA::Inst_DS__DS_XOR_RTN_B32
Definition: instructions.hh:32133
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_SUB_SRC2_U32(MachInst)
Definition: decoder.cc:7897
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CLREXCP
GPUStaticInst * decode_OPU_VOP3__V_CLREXCP(MachInst)
Definition: decoder.cc:6422
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I64(MachInst)
Definition: decoder.cc:12683
gem5::VegaISA::Inst_VOP3__V_MUL_LO_U32
Definition: instructions.hh:30333
gem5::VegaISA::Decoder::decode_OP_SMEM__S_STORE_DWORD
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORD(MachInst)
Definition: decoder.cc:10010
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_U64
GPUStaticInst * decode_OP_DS__DS_MIN_U64(MachInst)
Definition: decoder.cc:7613
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_TRIG_PREOP_F64
GPUStaticInst * decode_OPU_VOP3__V_TRIG_PREOP_F64(MachInst)
Definition: decoder.cc:7137
gem5::VegaISA::Inst_SOPP__S_DECPERFLEVEL
Definition: instructions.hh:5053
gem5::VegaISA::Inst_VOP3__V_ADD_CO_U32
Definition: instructions.hh:24779
gem5::VegaISA::Inst_VOP3__V_SUBREV_CO_U32
Definition: instructions.hh:24851
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I32(MachInst)
Definition: decoder.cc:5576
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F16
Definition: instructions.hh:11039
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
Definition: instructions.hh:38207
gem5::VegaISA::Inst_SOPC__S_CMP_EQ_U32
Definition: instructions.hh:3971
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_B
Definition: instructions.hh:39739
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I32(MachInst)
Definition: decoder.cc:5456
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORD
Definition: instructions.hh:5503
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_CL(MachInst)
Definition: decoder.cc:9172
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX2
Definition: instructions.hh:42056
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I32(MachInst)
Definition: decoder.cc:12593
gem5::VegaISA::Inst_VOP3__V_MUL_F32
Definition: instructions.hh:24131
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:8719
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_F32
GPUStaticInst * decode_OP_DS__DS_MAX_F32(MachInst)
Definition: decoder.cc:7342
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F16(MachInst)
Definition: decoder.cc:4832
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I64
Definition: instructions.hh:16751
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9935
gem5::VegaISA::Inst_SOPC__S_BITCMP0_B32
Definition: instructions.hh:4163
gem5::VegaISA::Decoder::decode_OP_VOP1__V_EXP_F32
GPUStaticInst * decode_OP_VOP1__V_EXP_F32(MachInst)
Definition: decoder.cc:11382
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP_PCK(MachInst)
Definition: decoder.cc:8779
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F16
Definition: instructions.hh:18485
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F16
Definition: instructions.hh:18213
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U16(MachInst)
Definition: decoder.cc:5300
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_OR_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:10332
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_HI_U32
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_U32(MachInst)
Definition: decoder.cc:7071
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_INC_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:10346
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B16_D16_HI
GPUStaticInst * decode_OP_DS__DS_WRITE_B16_D16_HI(MachInst)
Definition: decoder.cc:7698
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O(MachInst)
Definition: decoder.cc:9061
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:10276
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_RTN_U64
GPUStaticInst * decode_OP_DS__DS_INC_RTN_U64(MachInst)
Definition: decoder.cc:7765
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_U64
GPUStaticInst * decode_OP_DS__DS_MAX_U64(MachInst)
Definition: decoder.cc:7619
gem5::VegaISA::Inst_SOPK__S_CMOVK_I32
Definition: instructions.hh:1573
gem5::VegaISA::Inst_VOP2__V_MUL_I32_I24
Definition: instructions.hh:6345
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MQSAD_U32_U8
GPUStaticInst * decode_OPU_VOP3__V_MQSAD_U32_U8(MachInst)
Definition: decoder.cc:6782
gem5::VegaISA::Inst_DS__DS_MAX_F64
Definition: instructions.hh:33455
gem5::VegaISA::Inst_VOP3__V_SUBBREV_CO_U32
Definition: instructions.hh:24963
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LOG_F32
GPUStaticInst * decode_OPU_VOP3__V_LOG_F32(MachInst)
Definition: decoder.cc:6302
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_F32(MachInst)
Definition: decoder.cc:6164
gem5::VegaISA::Decoder::decode_OP_DS__DS_CONDXCHG32_RTN_B64
GPUStaticInst * decode_OP_DS__DS_CONDXCHG32_RTN_B64(MachInst)
Definition: decoder.cc:7885
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F64
Definition: instructions.hh:19777
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X
Definition: instructions.hh:38283
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:9394
gem5::VegaISA::Inst_VOP3__V_MIN3_I32
Definition: instructions.hh:28587
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F16(MachInst)
Definition: decoder.cc:4850
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F16
Definition: instructions.hh:11379
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F64
Definition: instructions.hh:19913
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL(MachInst)
Definition: decoder.cc:8983
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U32(MachInst)
Definition: decoder.cc:12533
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I16(MachInst)
Definition: decoder.cc:12293
gem5::VegaISA::Inst_DS__DS_MAX_I64
Definition: instructions.hh:33033
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C
Definition: instructions.hh:39559
gem5::VegaISA::Inst_VOP3__V_LSHL_OR_B32
Definition: instructions.hh:29605
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:10535
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY
Definition: instructions.hh:37865
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SWAP_B32
GPUStaticInst * decode_OP_VOP1__V_SWAP_B32(MachInst)
Definition: decoder.cc:11662
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B(MachInst)
Definition: decoder.cc:9116
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_UBYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_UBYTE(MachInst)
Definition: decoder.cc:9503
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_O(MachInst)
Definition: decoder.cc:9055
gem5::VegaISA::Inst_VOP3__V_MUL_I32_I24
Definition: instructions.hh:24165
gem5::VegaISA::InstFormat::iFmt_MIMG
InFmt_MIMG iFmt_MIMG
Definition: gpu_decoder.hh:1909
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F64
Definition: instructions.hh:20355
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SMAX
Definition: instructions.hh:37107
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_L
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_L(MachInst)
Definition: decoder.cc:9160
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I16
Definition: instructions.hh:21477
gem5::VegaISA::Inst_VOP3__V_CNDMASK_B32
Definition: instructions.hh:23959
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_XOR_B32
GPUStaticInst * decode_OPU_VOP3__V_XOR_B32(MachInst)
Definition: decoder.cc:5948
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U32
Definition: instructions.hh:22259
gem5::VegaISA::Inst_VOP3__V_TRUNC_F16
Definition: instructions.hh:27751
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I16
Definition: instructions.hh:13929
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F64
Definition: instructions.hh:17295
gem5::VegaISA::Inst_VOPC__V_CMP_O_F16
Definition: instructions.hh:10835
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F16(MachInst)
Definition: decoder.cc:4670
gem5::VegaISA::Inst_VOP3__V_MIN3_F32
Definition: instructions.hh:28551
gem5::VegaISA::Inst_VOP3__V_DIV_FIXUP_F16
Definition: instructions.hh:29885
gem5::VegaISA::Inst_SMEM__S_BUFFER_STORE_DWORD
Definition: instructions.hh:5791
gem5::VegaISA::Inst_SMEM__S_ATC_PROBE_BUFFER
Definition: instructions.hh:6105
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I64
Definition: instructions.hh:23619
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE(MachInst)
Definition: decoder.cc:9782
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LSHLREV_B32
GPUStaticInst * decode_OP_VOP2__V_LSHLREV_B32(MachInst)
Definition: decoder.cc:3953
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F16
Definition: instructions.hh:18451
gem5::VegaISA::Inst_DS__DS_SUB_U32
Definition: instructions.hh:31011
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FRACT_F64
GPUStaticInst * decode_OP_VOP1__V_FRACT_F64(MachInst)
Definition: decoder.cc:11490
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U64(MachInst)
Definition: decoder.cc:5786
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX4
Definition: instructions.hh:42130
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_I32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_I32(MachInst)
Definition: decoder.cc:6668
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_B64
GPUStaticInst * decode_OP_DS__DS_XOR_B64(MachInst)
Definition: decoder.cc:7637
gem5::VegaISA::Inst_VOP3__V_SIN_F16
Definition: instructions.hh:27847
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F64(MachInst)
Definition: decoder.cc:5114
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I32
Definition: instructions.hh:21919
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F16(MachInst)
Definition: decoder.cc:11705
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMIN
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:9643
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F32
Definition: instructions.hh:12705
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ABSDIFF_I32
GPUStaticInst * decode_OP_SOP2__S_ABSDIFF_I32(MachInst)
Definition: decoder.cc:4427
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFE_I32
GPUStaticInst * decode_OPU_VOP3__V_BFE_I32(MachInst)
Definition: decoder.cc:6602
gem5::VegaISA::Inst_VOP1__V_CEIL_F32
Definition: instructions.hh:8957
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F16
Definition: instructions.hh:10665
gem5::VegaISA::Inst_DS__DS_READ_U8
Definition: instructions.hh:32641
gem5::VegaISA::Inst_SOP1__S_FF1_I32_B32
Definition: instructions.hh:2693
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I64
Definition: instructions.hh:16241
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U32(MachInst)
Definition: decoder.cc:5588
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F64(MachInst)
Definition: decoder.cc:12143
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I16
Definition: instructions.hh:14643
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_STORE
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE(MachInst)
Definition: decoder.cc:8791
gem5::VegaISA::Inst_MIMG__IMAGE_STORE
Definition: instructions.hh:38651
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F32
Definition: instructions.hh:18655
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_I32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_I32(MachInst)
Definition: decoder.cc:7409
gem5::VegaISA::Inst_DS__DS_WRITE2ST64_B64
Definition: instructions.hh:33327
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U64
Definition: instructions.hh:16411
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U16(MachInst)
Definition: decoder.cc:12437
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F32(MachInst)
Definition: decoder.cc:11669
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ALIGNBYTE_B32
GPUStaticInst * decode_OPU_VOP3__V_ALIGNBYTE_B32(MachInst)
Definition: decoder.cc:6638
gem5::VegaISA::Inst_DS__DS_MAX_U64
Definition: instructions.hh:33097
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_X
Definition: instructions.hh:37979
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_XOR
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_XOR(MachInst)
Definition: decoder.cc:10248
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_INC_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:10528
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F64
Definition: instructions.hh:12977
gem5::VegaISA::Inst_DS__DS_WRITE2ST64_B32
Definition: instructions.hh:31465
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F64(MachInst)
Definition: decoder.cc:12107
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_BYTE_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_BYTE_D16_HI(MachInst)
Definition: decoder.cc:9557
gem5::VegaISA::Inst_SOP2__S_MUL_I32
Definition: instructions.hh:1269
gem5::VegaISA::InFmt_VOP3A
Definition: gpu_decoder.hh:1800
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_BYTE
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_BYTE(MachInst)
Definition: decoder.cc:8210
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_F16
GPUStaticInst * decode_OP_VOP2__V_MUL_F16(MachInst)
Definition: decoder.cc:4049
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F32
Definition: instructions.hh:12127
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FLOOR_F32
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F32(MachInst)
Definition: decoder.cc:6290
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I16(MachInst)
Definition: decoder.cc:5348
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_OR
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_OR(MachInst)
Definition: decoder.cc:9673
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_VCCNZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_VCCNZ(MachInst)
Definition: decoder.cc:11033
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ANDN2_B64
GPUStaticInst * decode_OP_SOP2__S_ANDN2_B64(MachInst)
Definition: decoder.cc:4289
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_UMIN
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:10395
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_SHORT
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_SHORT(MachInst)
Definition: decoder.cc:9845
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_I32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_I32(MachInst)
Definition: decoder.cc:6650
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I64(MachInst)
Definition: decoder.cc:12689
gem5::VegaISA::Decoder::decode_OP_SOP1__S_NOT_B32
GPUStaticInst * decode_OP_SOP1__S_NOT_B32(MachInst)
Definition: decoder.cc:10566
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F64
Definition: instructions.hh:10495
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX2
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:8192
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U64(MachInst)
Definition: decoder.cc:5810
gem5::VegaISA::Inst_VOP2__V_CNDMASK_B32
Definition: instructions.hh:6139
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I64
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I64(MachInst)
Definition: decoder.cc:7131
gem5::VegaISA::Inst_VOP3__V_CMP_F_F32
Definition: instructions.hh:18519
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I32(MachInst)
Definition: decoder.cc:5474
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FLOOR_F16
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F16(MachInst)
Definition: decoder.cc:11587
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F64
Definition: instructions.hh:20321
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F16(MachInst)
Definition: decoder.cc:4730
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I32(MachInst)
Definition: decoder.cc:5462
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F16(MachInst)
Definition: decoder.cc:4706
gem5::VegaISA::Inst_VOP3__V_LSHRREV_B16
Definition: instructions.hh:25341
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:10451
gem5::VegaISA::Inst_VOP2__V_SUBREV_U32
Definition: instructions.hh:7999
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_XOR_SRC2_B64(MachInst)
Definition: decoder.cc:8114
gem5::VegaISA::Inst_SOPP__S_CBRANCH_SCC0
Definition: instructions.hh:4539
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_L
Definition: instructions.hh:39415
gem5::VegaISA::Inst_VOP3__V_MAD_I64_I32
Definition: instructions.hh:29459
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_AND_SRC2_B64(MachInst)
Definition: decoder.cc:8102
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_EXP_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_EXP_LEGACY_F32(MachInst)
Definition: decoder.cc:6536
gem5::VegaISA::Decoder::decode_OP_SOPP__S_ENDPGM
GPUStaticInst * decode_OP_SOPP__S_ENDPGM(MachInst)
Definition: decoder.cc:10997
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_INC
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_INC(MachInst)
Definition: decoder.cc:8665
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F32(MachInst)
Definition: decoder.cc:5006
gem5::VegaISA::Inst_SOP2__S_XOR_B64
Definition: instructions.hh:623
gem5::VegaISA::Inst_VOP1__V_CVT_U32_F64
Definition: instructions.hh:8701
gem5::VegaISA::Inst_DS__DS_ADD_SRC2_F32
Definition: instructions.hh:34753
gem5::VegaISA::Inst_VOP3__V_BFREV_B32
Definition: instructions.hh:27019
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SAD_U8
GPUStaticInst * decode_OPU_VOP3__V_SAD_U8(MachInst)
Definition: decoder.cc:6698
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ANDN2_B32
GPUStaticInst * decode_OP_SOP2__S_ANDN2_B32(MachInst)
Definition: decoder.cc:4283
gem5::VegaISA::Inst_VOP3__V_CMP_T_I32
Definition: instructions.hh:22021
gem5::VegaISA::Inst_VOP3__V_CMP_F_I32
Definition: instructions.hh:21783
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X(MachInst)
Definition: decoder.cc:9455
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U32(MachInst)
Definition: decoder.cc:12521
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O(MachInst)
Definition: decoder.cc:9298
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER(MachInst)
Definition: decoder.cc:11147
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_AND_SRC2_B32(MachInst)
Definition: decoder.cc:7945
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_PKNORM_U16_F16
GPUStaticInst * decode_OPU_VOP3__V_PKNORM_U16_F16(MachInst)
Definition: decoder.cc:7186
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U32
Definition: instructions.hh:22191
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAC_F32
GPUStaticInst * decode_OP_VOP2__V_MAC_F32(MachInst)
Definition: decoder.cc:3977
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F32(MachInst)
Definition: decoder.cc:12053
gem5::VegaISA::Inst_VOP3__V_LSHLREV_B16
Definition: instructions.hh:25307
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F32(MachInst)
Definition: decoder.cc:4874
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U16
Definition: instructions.hh:14303
gem5::VegaISA::Decoder::decode_OP_DS__DS_CONSUME
GPUStaticInst * decode_OP_DS__DS_CONSUME(MachInst)
Definition: decoder.cc:8030
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_SSHORT
Definition: instructions.hh:36373
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I32(MachInst)
Definition: decoder.cc:5480
gem5::VegaISA::Inst_VOP3__V_ASHRREV_I32
Definition: instructions.hh:24539
gem5::VegaISA::Inst_VOP3__V_RCP_F64
Definition: instructions.hh:26795
gem5::VegaISA::Inst_VOP3__V_FFBL_B32
Definition: instructions.hh:27083
gem5::VegaISA::Inst_VOP3__V_LOG_F16
Definition: instructions.hh:27559
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_U32(MachInst)
Definition: decoder.cc:7933
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_HI_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_U32_U24(MachInst)
Definition: decoder.cc:5876
gem5::VegaISA::Inst_VOP3__V_RNDNE_F32
Definition: instructions.hh:26571
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_U32
GPUStaticInst * decode_OP_DS__DS_INC_U32(MachInst)
Definition: decoder.cc:7246
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LG_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F64(MachInst)
Definition: decoder.cc:12119
gem5::VegaISA::Inst_VOP3__V_MBCNT_LO_U32_B32
Definition: instructions.hh:30571
gem5::VegaISA::Inst_DS__DS_GWS_SEMA_BR
Definition: instructions.hh:34875
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F32
Definition: instructions.hh:19539
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U32(MachInst)
Definition: decoder.cc:12641
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U16(MachInst)
Definition: decoder.cc:12371
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_GE_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GE_U32(MachInst)
Definition: decoder.cc:4567
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F32(MachInst)
Definition: decoder.cc:11993
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_I32
GPUStaticInst * decode_OPU_VOP3__V_MIN_I32(MachInst)
Definition: decoder.cc:5894
gem5::VegaISA::InFmt_DS::OP
unsigned int OP
Definition: gpu_decoder.hh:1604
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I32(MachInst)
Definition: decoder.cc:12587
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_O
Definition: instructions.hh:41071
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SET_GPR_IDX_IDX
GPUStaticInst * decode_OP_SOP1__S_SET_GPR_IDX_IDX(MachInst)
Definition: decoder.cc:10830
gem5::VegaISA::Inst_VOP3__V_MUL_F64
Definition: instructions.hh:30197
gem5::VegaISA::Inst_SOP2__S_BFE_U64
Definition: instructions.hh:1371
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F16
Definition: instructions.hh:11651
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U32
Definition: instructions.hh:22769
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SMIN
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:10388
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_SUB_SRC2_U64(MachInst)
Definition: decoder.cc:8054
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_U16
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_U16(MachInst)
Definition: decoder.cc:6806
gem5::VegaISA::Inst_VOP1__V_CEIL_F16
Definition: instructions.hh:10137
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_B64
GPUStaticInst * decode_OP_DS__DS_READ_B64(MachInst)
Definition: decoder.cc:7867
gem5::VegaISA::Inst_VOP3__V_CVT_U32_F64
Definition: instructions.hh:26283
gem5::VegaISA::Inst_DS__DS_SWIZZLE_B32
Definition: instructions.hh:32741
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U16(MachInst)
Definition: decoder.cc:5324
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBREV_U16
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_U16(MachInst)
Definition: decoder.cc:6038
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_F32
Definition: instructions.hh:34693
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F32
Definition: instructions.hh:18893
gem5::VegaISA::InFmt_MIMG
Definition: gpu_decoder.hh:1656
gem5::VegaISA::Inst_VOP1__V_CVT_I32_F32
Definition: instructions.hh:8285
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE_D16
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE_D16(MachInst)
Definition: decoder.cc:8571
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U32(MachInst)
Definition: decoder.cc:5504
gem5::VegaISA::Decoder::tableSubDecode_OP_SMEM
static IsaDecodeMethod tableSubDecode_OP_SMEM[256]
Definition: gpu_decoder.hh:70
gem5::VegaISA::Inst_VOP1__V_SQRT_F32
Definition: instructions.hh:9277
gem5::VegaISA::Inst_SOP2__S_SUB_U32
Definition: instructions.hh:79
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_EQ_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_EQ_U32(MachInst)
Definition: decoder.cc:4549
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG2ST64_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG2ST64_RTN_B64(MachInst)
Definition: decoder.cc:7837
gem5::VegaISA::Inst_SMEM__S_STORE_DWORDX2
Definition: instructions.hh:5719
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_I32
Definition: instructions.hh:34453
gem5::VegaISA::Inst_VOP3__V_CMP_T_I64
Definition: instructions.hh:23109
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC
Definition: instructions.hh:42580
gem5::VegaISA::Inst_VOP2__V_MADMK_F16
Definition: instructions.hh:7383
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U8_D16_HI
GPUStaticInst * decode_OP_DS__DS_READ_U8_D16_HI(MachInst)
Definition: decoder.cc:7712
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_F32
GPUStaticInst * decode_OPU_VOP3__V_ADD_F32(MachInst)
Definition: decoder.cc:5828
gem5::VegaISA::Decoder::decode_OP_SOP2__S_RFE_RESTORE_B64
GPUStaticInst * decode_OP_SOP2__S_RFE_RESTORE_B64(MachInst)
Definition: decoder.cc:4433
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F32(MachInst)
Definition: decoder.cc:11981
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_WRITE_SRC2_B64(MachInst)
Definition: decoder.cc:8120
gem5::VegaISA::Decoder::decode_OP_SOP2__S_XNOR_B32
GPUStaticInst * decode_OP_SOP2__S_XNOR_B32(MachInst)
Definition: decoder.cc:4331
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LSHLREV_B16
GPUStaticInst * decode_OP_VOP2__V_LSHLREV_B16(MachInst)
Definition: decoder.cc:4097
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U16
Definition: instructions.hh:14779
gem5::VegaISA::InFmt_SOP1::ENCODING
unsigned int ENCODING
Definition: gpu_decoder.hh:1745
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:10465
gem5::VegaISA::Decoder::decode_OP_SMEM__S_MEMTIME
GPUStaticInst * decode_OP_SMEM__S_MEMTIME(MachInst)
Definition: decoder.cc:10140
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F64
Definition: instructions.hh:13147
gem5::VegaISA::Inst_VOP3__V_CVT_I32_F32
Definition: instructions.hh:25867
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F32(MachInst)
Definition: decoder.cc:12047
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_SCC0
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_SCC0(MachInst)
Definition: decoder.cc:11015
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_RTN_U32
GPUStaticInst * decode_OP_DS__DS_SUB_RTN_U32(MachInst)
Definition: decoder.cc:7385
gem5::VegaISA::Inst_VOP1__V_FFBH_U32
Definition: instructions.hh:9469
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I16
Definition: instructions.hh:20763
gem5::VegaISA::Inst_SOP1__S_FF0_I32_B64
Definition: instructions.hh:2661
gem5::VegaISA::InstFormat::iFmt_MTBUF
InFmt_MTBUF iFmt_MTBUF
Definition: gpu_decoder.hh:1911
gem5::VegaISA::InFmt_FLAT::OP
unsigned int OP
Definition: gpu_decoder.hh:1639
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC(MachInst)
Definition: decoder.cc:8671
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_B_CL
Definition: instructions.hh:40567
gem5::VegaISA::Inst_DS__DS_READ2_B64
Definition: instructions.hh:34201
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:9745
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_F32
GPUStaticInst * decode_OPU_VOP3__V_MUL_F32(MachInst)
Definition: decoder.cc:5852
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_U_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F64(MachInst)
Definition: decoder.cc:12137
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_F16
GPUStaticInst * decode_OP_VOP2__V_MAX_F16(MachInst)
Definition: decoder.cc:4115
gem5::VegaISA::Inst_DS__DS_WRXCHG2_RTN_B64
Definition: instructions.hh:33963
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F16
Definition: instructions.hh:17499
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_BYTE_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_BYTE_D16_HI(MachInst)
Definition: decoder.cc:8216
gem5::VegaISA::InFmt_DS
Definition: gpu_decoder.hh:1600
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_EXECZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_EXECZ(MachInst)
Definition: decoder.cc:11039
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_USHORT
Definition: instructions.hh:41723
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U16(MachInst)
Definition: decoder.cc:12329
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I64(MachInst)
Definition: decoder.cc:5654
gem5::VegaISA::Inst_SOP1__S_MOVRELS_B32
Definition: instructions.hh:3523
gem5::VegaISA::Inst_VOP2__V_ASHRREV_I32
Definition: instructions.hh:6719
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F16
Definition: instructions.hh:17737
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SAD_U32
GPUStaticInst * decode_OPU_VOP3__V_SAD_U32(MachInst)
Definition: decoder.cc:6716
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CL(MachInst)
Definition: decoder.cc:8953
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_RTN_B64
GPUStaticInst * decode_OP_DS__DS_AND_RTN_B64(MachInst)
Definition: decoder.cc:7801
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_LZ(MachInst)
Definition: decoder.cc:8941
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I64
Definition: instructions.hh:23075
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CBRANCH_I_FORK
GPUStaticInst * decode_OP_SOPK__S_CBRANCH_I_FORK(MachInst)
Definition: decoder.cc:4597
gem5::VegaISA::Inst_VOP1__V_READFIRSTLANE_B32
Definition: instructions.hh:8093
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_F32
GPUStaticInst * decode_OP_VOP2__V_MAX_F32(MachInst)
Definition: decoder.cc:3911
gem5::VegaISA::Inst_SOPK__S_CMPK_LE_U32
Definition: instructions.hh:1957
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_RTN_B32
GPUStaticInst * decode_OP_DS__DS_AND_RTN_B32(MachInst)
Definition: decoder.cc:7433
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F32(MachInst)
Definition: decoder.cc:4988
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAD_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAD_U16(MachInst)
Definition: decoder.cc:12920
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I64
Definition: instructions.hh:23653
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F64
Definition: instructions.hh:13351
gem5::VegaISA::Inst_VOPC__V_CMP_F_U64
Definition: instructions.hh:16309
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I32(MachInst)
Definition: decoder.cc:12479
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RCP_F16
GPUStaticInst * decode_OP_VOP1__V_RCP_F16(MachInst)
Definition: decoder.cc:11545
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F16(MachInst)
Definition: decoder.cc:11693
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F64
Definition: instructions.hh:19811
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_ADDTID_B32
GPUStaticInst * decode_OP_DS__DS_WRITE_ADDTID_B32(MachInst)
Definition: decoder.cc:7360
gem5::VegaISA::Inst_DS__DS_WRITE_SRC2_B32
Definition: instructions.hh:34663
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U64(MachInst)
Definition: decoder.cc:12833
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I32
Definition: instructions.hh:22497
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITSET1_B32
GPUStaticInst * decode_OP_SOP1__S_BITSET1_B32(MachInst)
Definition: decoder.cc:10698
gem5::VegaISA::Inst_VOP3__V_DIV_SCALE_F32
Definition: instructions.hh:29127
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U16(MachInst)
Definition: decoder.cc:5312
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I64
Definition: instructions.hh:16615
gem5::VegaISA::Inst_DS__DS_WRXCHG2ST64_RTN_B64
Definition: instructions.hh:33997
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F64(MachInst)
Definition: decoder.cc:5072
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_USHORT
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_USHORT(MachInst)
Definition: decoder.cc:8174
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SETPRIO
GPUStaticInst * decode_OP_SOPP__S_SETPRIO(MachInst)
Definition: decoder.cc:11081
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D(MachInst)
Definition: decoder.cc:8911
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_U16
GPUStaticInst * decode_OP_VOP2__V_SUB_U16(MachInst)
Definition: decoder.cc:4079
gem5::VegaISA::Inst_SOPC__S_CMP_EQ_U64
Definition: instructions.hh:4355
gem5::VegaISA::Inst_DS__DS_XOR_SRC2_B32
Definition: instructions.hh:34633
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I64
Definition: instructions.hh:16819
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL2_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_LSHL2_ADD_U32(MachInst)
Definition: decoder.cc:4459
gem5::VegaISA::Inst_VOP2__V_MAX_I32
Definition: instructions.hh:6583
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:10178
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I32
Definition: instructions.hh:15119
gem5::VegaISA::Inst_SMEM__S_DCACHE_INV_VOL
Definition: instructions.hh:5955
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SQRT_F16
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F16(MachInst)
Definition: decoder.cc:6458
gem5::VegaISA::Decoder::decode_OP_VOP1__V_TRUNC_F16
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F16(MachInst)
Definition: decoder.cc:11599
gem5::VegaISA::Inst_DS__DS_READ_U16
Definition: instructions.hh:32707
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FMAS_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_FMAS_F32(MachInst)
Definition: decoder.cc:6752
gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE2
Definition: instructions.hh:8637
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_U16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_U16_F16(MachInst)
Definition: decoder.cc:11533
gem5::VegaISA::Inst_SOPP__S_SLEEP
Definition: instructions.hh:4843
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FRACT_F16
GPUStaticInst * decode_OP_VOP1__V_FRACT_F16(MachInst)
Definition: decoder.cc:11611
gem5::VegaISA::Inst_VOP1__V_CVT_OFF_F32_I4
Definition: instructions.hh:8477
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U32
Definition: instructions.hh:15425
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX2
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX2(MachInst)
Definition: decoder.cc:9583
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U32(MachInst)
Definition: decoder.cc:5594
gem5::VegaISA::Inst_SOP2__S_OR_B32
Definition: instructions.hh:521
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP_X2
Definition: instructions.hh:42654
gem5::GPUStaticInst
Definition: gpu_static_inst.hh:61
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:9703
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_ADD
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_ADD(MachInst)
Definition: decoder.cc:10192
gem5::VegaISA::Inst_SMEM__S_MEMTIME
Definition: instructions.hh:6011
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U16
Definition: instructions.hh:21035
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O
Definition: instructions.hh:40243
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:9473
gem5::VegaISA::Decoder::decode_OP_SOP2__S_CSELECT_B64
GPUStaticInst * decode_OP_SOP2__S_CSELECT_B64(MachInst)
Definition: decoder.cc:4241
gem5::VegaISA::Inst_VOP2__V_MAX_F32
Definition: instructions.hh:6515
gem5::VegaISA::Decoder::decode_OP_SOP1__S_NOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_NOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10770
gem5::VegaISA::InstFormat::iFmt_VOP1
InFmt_VOP1 iFmt_VOP1
Definition: gpu_decoder.hh:1923
gem5::VegaISA::Decoder::decode_OP_SOP1__S_CBRANCH_JOIN
GPUStaticInst * decode_OP_SOP1__S_CBRANCH_JOIN(MachInst)
Definition: decoder.cc:10818
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F64(MachInst)
Definition: decoder.cc:5168
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN
Definition: instructions.hh:38615
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LE_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LE_I32(MachInst)
Definition: decoder.cc:4543
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD
Definition: instructions.hh:38435
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CEIL_F64
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F64(MachInst)
Definition: decoder.cc:6248
gem5::VegaISA::Decoder::decode_OP_EXP
GPUStaticInst * decode_OP_EXP(MachInst)
Definition: decoder.cc:4628
gem5::VegaISA::Decoder::decode_OP_SOPP__S_WAKEUP
GPUStaticInst * decode_OP_SOPP__S_WAKEUP(MachInst)
Definition: decoder.cc:11009
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PKNORM_I16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKNORM_I16_F32(MachInst)
Definition: decoder.cc:7149
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FLOOR_F32
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F32(MachInst)
Definition: decoder.cc:11376
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
Definition: instructions.hh:36175
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_L
Definition: instructions.hh:39703
gem5::VegaISA::Inst_VOP2__V_MAC_F16
Definition: instructions.hh:7349
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U64
Definition: instructions.hh:17057
gem5::VegaISA::Inst_VOP1__V_TRUNC_F16
Definition: instructions.hh:10169
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_OR
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_OR(MachInst)
Definition: decoder.cc:8653
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:10367
gem5::VegaISA::Inst_SMEM__S_BUFFER_STORE_DWORDX2
Definition: instructions.hh:5827
gem5::VegaISA::Inst_VOP2__V_MUL_LO_U16
Definition: instructions.hh:7557
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U32(MachInst)
Definition: decoder.cc:5624
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_PCK
Definition: instructions.hh:38507
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I64(MachInst)
Definition: decoder.cc:12671
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F32(MachInst)
Definition: decoder.cc:11921
gem5::VegaISA::Inst_VOP3__V_CEIL_F32
Definition: instructions.hh:26539
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F16
Definition: instructions.hh:10563
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_WRITELANE_B32
GPUStaticInst * decode_OPU_VOP3__V_WRITELANE_B32(MachInst)
Definition: decoder.cc:7095
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U64
Definition: instructions.hh:23789
gem5::VegaISA::Inst_VOP1__V_CVT_RPI_I32_F32
Definition: instructions.hh:8413
gem5::VegaISA::Inst_SOPK__S_MULK_I32
Definition: instructions.hh:2021
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U64
Definition: instructions.hh:23347
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SSHORT
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SSHORT(MachInst)
Definition: decoder.cc:9796
gem5::VegaISA::Decoder::decode_OP_SOP2__S_NOR_B64
GPUStaticInst * decode_OP_SOP2__S_NOR_B64(MachInst)
Definition: decoder.cc:4325
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U16(MachInst)
Definition: decoder.cc:5396
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I16(MachInst)
Definition: decoder.cc:5384
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_NORM_I16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_NORM_I16_F16(MachInst)
Definition: decoder.cc:11641
gem5::VegaISA::InstFormat::iFmt_VOPC
InFmt_VOPC iFmt_VOPC
Definition: gpu_decoder.hh:1928
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_F32
GPUStaticInst * decode_OP_DS__DS_CMPST_F32(MachInst)
Definition: decoder.cc:7330
gem5::VegaISA::Inst_VOP1__V_CVT_U16_F16
Definition: instructions.hh:9817
gem5::VegaISA::Decoder::decode_OP_SOP2__S_OR_B32
GPUStaticInst * decode_OP_SOP2__S_OR_B32(MachInst)
Definition: decoder.cc:4259
gem5::VegaISA::Inst_SOPK__S_CMPK_EQ_I32
Definition: instructions.hh:1605
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
Definition: instructions.hh:37903
gem5::VegaISA::Inst_SOPK__S_CMPK_LG_I32
Definition: instructions.hh:1637
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U16(MachInst)
Definition: decoder.cc:5336
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_DWORD
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_DWORD(MachInst)
Definition: decoder.cc:8532
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND_X2
Definition: instructions.hh:42954
gem5::VegaISA::Inst_VOP2__V_SUBREV_F32
Definition: instructions.hh:6243
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_B32
GPUStaticInst * decode_OP_DS__DS_OR_B32(MachInst)
Definition: decoder.cc:7288
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_F32
Definition: instructions.hh:34723
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F32
Definition: instructions.hh:18825
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_DEC
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_DEC(MachInst)
Definition: decoder.cc:8374
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_XOR
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_XOR(MachInst)
Definition: decoder.cc:8362
gem5::VegaISA::Inst_SOP2__S_ABSDIFF_I32
Definition: instructions.hh:1473
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY(MachInst)
Definition: decoder.cc:9437
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_GT_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_GT_U32(MachInst)
Definition: decoder.cc:10919
gem5::VegaISA::Decoder::decode_OP_VOP1__V_TRUNC_F32
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F32(MachInst)
Definition: decoder.cc:11358
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_LSHL_U32
GPUStaticInst * decode_OPU_VOP3__V_ADD_LSHL_U32(MachInst)
Definition: decoder.cc:6932
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:8641
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_RTN_F64
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_F64(MachInst)
Definition: decoder.cc:7849
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I16(MachInst)
Definition: decoder.cc:12407
gem5::VegaISA::Decoder::subDecode_OP_VOP3P
GPUStaticInst * subDecode_OP_VOP3P(MachInst)
Definition: decoder.cc:3728
gem5::VegaISA::Inst_DS__DS_WRITE_B96
Definition: instructions.hh:35515
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_I32
Definition: instructions.hh:34483
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F16_U16
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_U16(MachInst)
Definition: decoder.cc:11521
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_I8_D16_HI
GPUStaticInst * decode_OP_DS__DS_READ_I8_D16_HI(MachInst)
Definition: decoder.cc:7726
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_INC_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:8446
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F64(MachInst)
Definition: decoder.cc:5132
gem5::VegaISA::Inst_SOPP__S_TRAP
Definition: instructions.hh:4963
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F16
Definition: instructions.hh:11277
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC
Definition: instructions.hh:42617
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX8
Definition: instructions.hh:5611
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F32(MachInst)
Definition: decoder.cc:5024
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FF1_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FF1_I32_B64(MachInst)
Definition: decoder.cc:10644
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_F64
GPUStaticInst * decode_OPU_VOP3__V_MAX_F64(MachInst)
Definition: decoder.cc:7053
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHR_B32
GPUStaticInst * decode_OP_SOP2__S_LSHR_B32(MachInst)
Definition: decoder.cc:4355
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX2
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9810
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SUB
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SUB(MachInst)
Definition: decoder.cc:10199
gem5::VegaISA::Inst_VOP2__V_ADD_U32
Definition: instructions.hh:7931
gem5::VegaISA::Inst_VOP1__V_LOG_F32
Definition: instructions.hh:9085
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F16(MachInst)
Definition: decoder.cc:4790
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_LDS_DWORD
Definition: instructions.hh:36799
gem5::VegaISA::Inst_VOP3__V_CVT_U16_F16
Definition: instructions.hh:27399
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I16
Definition: instructions.hh:14541
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_U32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_U32_F32(MachInst)
Definition: decoder.cc:6146
gem5::VegaISA::Inst_SOPP__S_SET_GPR_IDX_MODE
Definition: instructions.hh:5293
gem5::VegaISA::Inst_SOP2__S_XOR_B32
Definition: instructions.hh:589
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F16
Definition: instructions.hh:11583
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SIN_F32
GPUStaticInst * decode_OPU_VOP3__V_SIN_F32(MachInst)
Definition: decoder.cc:6350
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U32
Definition: instructions.hh:22735
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FRACT_F32
GPUStaticInst * decode_OP_VOP1__V_FRACT_F32(MachInst)
Definition: decoder.cc:11352
gem5::VegaISA::Inst_VOP3__V_SAD_U16
Definition: instructions.hh:28947
gem5::VegaISA::Inst_DS__DS_MIN_RTN_I64
Definition: instructions.hh:33657
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_I32
GPUStaticInst * decode_OPU_VOP3__V_SUB_I32(MachInst)
Definition: decoder.cc:7200
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_UMIN
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:8851
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_L
Definition: instructions.hh:40711
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_AND
Definition: instructions.hh:39101
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F64
Definition: instructions.hh:20253
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_LZ_O(MachInst)
Definition: decoder.cc:9214
gem5::VegaISA::Inst_SOP2__S_XNOR_B64
Definition: instructions.hh:963
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I32(MachInst)
Definition: decoder.cc:5564
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U32(MachInst)
Definition: decoder.cc:12623
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SEXT_I32_I8
GPUStaticInst * decode_OP_SOP1__S_SEXT_I32_I8(MachInst)
Definition: decoder.cc:10674
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:10486
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE2ST64_B32
GPUStaticInst * decode_OP_DS__DS_WRITE2ST64_B32(MachInst)
Definition: decoder.cc:7318
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX16
Definition: instructions.hh:5647
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_U64
GPUStaticInst * decode_OP_DS__DS_ADD_U64(MachInst)
Definition: decoder.cc:7571
gem5::VegaISA::Inst_DS__DS_RSUB_SRC2_U64
Definition: instructions.hh:35125
gem5::VegaISA::Inst_DS__DS_MIN_RTN_F64
Definition: instructions.hh:34099
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U32
Definition: instructions.hh:15357
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_RTN_U32
GPUStaticInst * decode_OP_DS__DS_DEC_RTN_U32(MachInst)
Definition: decoder.cc:7403
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2
Definition: instructions.hh:37611
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LDEXP_F32
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F32(MachInst)
Definition: decoder.cc:7083
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_F64
GPUStaticInst * decode_OPU_VOP3__V_MIN_F64(MachInst)
Definition: decoder.cc:7047
gem5::VegaISA::Inst_VOP1__V_FFBH_I32
Definition: instructions.hh:9533
gem5::VegaISA::Decoder::decode_OP_SOP2__S_SUBB_U32
GPUStaticInst * decode_OP_SOP2__S_SUBB_U32(MachInst)
Definition: decoder.cc:4205
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F16(MachInst)
Definition: decoder.cc:4802
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F64(MachInst)
Definition: decoder.cc:11681
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I64
Definition: instructions.hh:23517
gem5::VegaISA::Inst_VOP3__V_CMP_T_U16
Definition: instructions.hh:21205
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I16(MachInst)
Definition: decoder.cc:5264
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:8422
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_LZ(MachInst)
Definition: decoder.cc:9128
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LG_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LG_U32(MachInst)
Definition: decoder.cc:4555
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:10500
gem5::VegaISA::Decoder::decode_OP_VOP1__V_LOG_LEGACY_F32
GPUStaticInst * decode_OP_VOP1__V_LOG_LEGACY_F32(MachInst)
Definition: decoder.cc:11635
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4(MachInst)
Definition: decoder.cc:9091
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_USHORT
Definition: instructions.hh:36335
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F16
Definition: instructions.hh:11311
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_NORM_U16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_NORM_U16_F16(MachInst)
Definition: decoder.cc:11648
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_SHORT
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_SHORT(MachInst)
Definition: decoder.cc:8223
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F64
Definition: instructions.hh:13249
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_SWAP
Definition: instructions.hh:38829
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_ADD_U32(MachInst)
Definition: decoder.cc:4175
gem5::VegaISA::Inst_VOP3__V_SUB_F32
Definition: instructions.hh:24029
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U16(MachInst)
Definition: decoder.cc:12353
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U32(MachInst)
Definition: decoder.cc:5606
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U16
Definition: instructions.hh:21715
gem5::VegaISA::Inst_VOP3__V_CEIL_F16
Definition: instructions.hh:27719
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX8
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX8(MachInst)
Definition: decoder.cc:9947
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
Definition: instructions.hh:35985
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F64(MachInst)
Definition: decoder.cc:5240
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F32(MachInst)
Definition: decoder.cc:4862
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL(MachInst)
Definition: decoder.cc:9280
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F32
Definition: instructions.hh:19369
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32(MachInst)
Definition: decoder.cc:7161
gem5::VegaISA::Decoder::decode_OP_DS__DS_MSKOR_B32
GPUStaticInst * decode_OP_DS__DS_MSKOR_B32(MachInst)
Definition: decoder.cc:7300
gem5::VegaISA::Inst_SOPP__S_WAITCNT
Definition: instructions.hh:4783
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U16
Definition: instructions.hh:14915
gem5::VegaISA::Inst_VOP3__V_SQRT_F32
Definition: instructions.hh:26859
gem5::VegaISA::Inst_DS__DS_XOR_RTN_B64
Definition: instructions.hh:33861
gem5::VegaISA::Inst_VOP3__V_CVT_PKACCUM_U8_F32
Definition: instructions.hh:29921
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F16
Definition: instructions.hh:17771
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_I32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_I32(MachInst)
Definition: decoder.cc:7927
gem5::VegaISA::Decoder::decode_OP_DS__DS_NOP
GPUStaticInst * decode_OP_DS__DS_NOP(MachInst)
Definition: decoder.cc:7348
gem5::VegaISA::Inst_VOP2__V_SUB_U16
Definition: instructions.hh:7489
gem5::VegaISA::Decoder::subDecode_OP_VOP1
GPUStaticInst * subDecode_OP_VOP1(MachInst)
Definition: decoder.cc:3736
gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE0
Definition: instructions.hh:26155
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_SMAX
Definition: instructions.hh:39033
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_F16
GPUStaticInst * decode_OPU_VOP3__V_ADD_F16(MachInst)
Definition: decoder.cc:5996
gem5::VegaISA::Inst_SOP2__S_BFE_U32
Definition: instructions.hh:1303
gem5::VegaISA::Inst_VOP3__V_INTERP_P2_F32
Definition: instructions.hh:29989
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RCP_F16
GPUStaticInst * decode_OPU_VOP3__V_RCP_F16(MachInst)
Definition: decoder.cc:6452
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I32
Definition: instructions.hh:21953
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_AND_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:10325
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RNDNE_F32
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F32(MachInst)
Definition: decoder.cc:6284
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F32
Definition: instructions.hh:19199
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U16(MachInst)
Definition: decoder.cc:5318
gem5::VegaISA::Inst_SOP2__S_LSHR_B32
Definition: instructions.hh:1065
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:8410
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_UMAX
Definition: instructions.hh:37143
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F16(MachInst)
Definition: decoder.cc:4838
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F64_U32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_U32(MachInst)
Definition: decoder.cc:11322
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE(MachInst)
Definition: decoder.cc:8458
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_STORE_DWORD
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_STORE_DWORD(MachInst)
Definition: decoder.cc:10028
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_I32
GPUStaticInst * decode_OP_DS__DS_MIN_I32(MachInst)
Definition: decoder.cc:7258
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_ADD_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_ADD_F16(MachInst)
Definition: decoder.cc:12962
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_I32
GPUStaticInst * decode_OPU_VOP3__V_ADD_I32(MachInst)
Definition: decoder.cc:7193
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U16_D16
GPUStaticInst * decode_OP_DS__DS_READ_U16_D16(MachInst)
Definition: decoder.cc:7733
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_SMIN
Definition: instructions.hh:38965
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_CO_U32
GPUStaticInst * decode_OP_VOP2__V_ADD_CO_U32(MachInst)
Definition: decoder.cc:3995
gem5::VegaISA::Decoder::subDecode_OP_SOPP
GPUStaticInst * subDecode_OP_SOPP(MachInst)
Definition: decoder.cc:3760
gem5::VegaISA::Inst_VOP2__V_SUBB_CO_U32
Definition: instructions.hh:7137
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ(MachInst)
Definition: decoder.cc:9443
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I32
Definition: instructions.hh:22463
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY
Definition: instructions.hh:36137
gem5::VegaISA::Inst_VOP3__V_FFBH_U32
Definition: instructions.hh:27051
gem5::VegaISA::Decoder::decode_OP_SOPP__S_ENDPGM_ORDERED_PS_DONE
GPUStaticInst * decode_OP_SOPP__S_ENDPGM_ORDERED_PS_DONE(MachInst)
Definition: decoder.cc:11171
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_O(MachInst)
Definition: decoder.cc:8995
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I64(MachInst)
Definition: decoder.cc:5660
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_U64(MachInst)
Definition: decoder.cc:8090
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F64
Definition: instructions.hh:20389
gem5::VegaISA::Inst_SOP1__S_OR_SAVEEXEC_B64
Definition: instructions.hh:3235
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F32(MachInst)
Definition: decoder.cc:5042
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FMAS_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_FMAS_F64(MachInst)
Definition: decoder.cc:6758
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_SRC2_U32(MachInst)
Definition: decoder.cc:7903
gem5::VegaISA::Inst_SMEM__S_DCACHE_INV
Definition: instructions.hh:5899
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMIN
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:9649
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F64(MachInst)
Definition: decoder.cc:12203
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_GT_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GT_U32(MachInst)
Definition: decoder.cc:4561
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_XOR
Definition: instructions.hh:37251
gem5::VegaISA::Inst_VOP3__V_SUBB_CO_U32
Definition: instructions.hh:24925
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F16
Definition: instructions.hh:17397
gem5::VegaISA::Decoder::~Decoder
~Decoder()
Definition: decoder.cc:47
gem5::VegaISA::Inst_DS__DS_GWS_SEMA_V
Definition: instructions.hh:34845
gem5::VegaISA::Decoder::tableSubDecode_OP_VINTRP
static IsaDecodeMethod tableSubDecode_OP_VINTRP[4]
Definition: gpu_decoder.hh:74
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ANDN1_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN1_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10836
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SMAX
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:8857
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_RTN_B32
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_B32(MachInst)
Definition: decoder.cc:7475
gem5::VegaISA::Inst_VOPC__V_CMP_T_U32
Definition: instructions.hh:15459
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FF0_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FF0_I32_B64(MachInst)
Definition: decoder.cc:10632
gem5::VegaISA::Inst_VOPC__V_CMP_F_U32
Definition: instructions.hh:15221
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:8623
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I32(MachInst)
Definition: decoder.cc:12569
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RCP_IFLAG_F32
GPUStaticInst * decode_OP_VOP1__V_RCP_IFLAG_F32(MachInst)
Definition: decoder.cc:11400
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P2_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P2_F32(MachInst)
Definition: decoder.cc:6998
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_B64(MachInst)
Definition: decoder.cc:10656
gem5::VegaISA::Inst_VOP3__V_CVT_PK_U8_F32
Definition: instructions.hh:29019
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F64
Definition: instructions.hh:13555
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_F64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_F64(MachInst)
Definition: decoder.cc:8126
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP
Definition: instructions.hh:36927
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:10185
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SSHORT
Definition: instructions.hh:41760
gem5::VegaISA::Decoder::decode_OP_SOPC__S_BITCMP0_B64
GPUStaticInst * decode_OP_SOPC__S_BITCMP0_B64(MachInst)
Definition: decoder.cc:10955
gem5::VegaISA::Decoder::decode_OP_SOP2__S_SUB_U32
GPUStaticInst * decode_OP_SOP2__S_SUB_U32(MachInst)
Definition: decoder.cc:4181
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR_X2
Definition: instructions.hh:43028
gem5::VegaISA::Inst_SOP2__S_BFE_I64
Definition: instructions.hh:1405
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F64
Definition: instructions.hh:20559
gem5::VegaISA::Inst_SOPP__S_SENDMSG
Definition: instructions.hh:4903
gem5::VegaISA::Inst_DS__DS_READ_B128
Definition: instructions.hh:35611
gem5::VegaISA::Inst_DS__DS_READ2_B32
Definition: instructions.hh:32541
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F16
Definition: instructions.hh:18179
gem5::VegaISA::InFmt_MTBUF
Definition: gpu_decoder.hh:1680
gem5::VegaISA::Decoder::decode_OP_SOPC__S_BITCMP0_B32
GPUStaticInst * decode_OP_SOPC__S_BITCMP0_B32(MachInst)
Definition: decoder.cc:10943
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBREV_F16
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_F16(MachInst)
Definition: decoder.cc:6008
gem5::VegaISA::Inst_VOP3__V_FREXP_MANT_F32
Definition: instructions.hh:27275
gem5::VegaISA::Inst_VOP1__V_CVT_F16_F32
Definition: instructions.hh:8349
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_B32(MachInst)
Definition: decoder.cc:10650
gem5::VegaISA::Decoder::decode_OP_SOP1__S_GETPC_B64
GPUStaticInst * decode_OP_SOP1__S_GETPC_B64(MachInst)
Definition: decoder.cc:10710
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F16(MachInst)
Definition: decoder.cc:11861
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_ADD
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_ADD(MachInst)
Definition: decoder.cc:9631
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I32(MachInst)
Definition: decoder.cc:12599
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I16
Definition: instructions.hh:21443
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:10318
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I16(MachInst)
Definition: decoder.cc:5258
gem5::VegaISA::Inst_VOP3__V_SAD_U8
Definition: instructions.hh:28875
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_ADDTID_B32
GPUStaticInst * decode_OP_DS__DS_READ_ADDTID_B32(MachInst)
Definition: decoder.cc:8023
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U32
Definition: instructions.hh:15935
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_O
Definition: instructions.hh:40135
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I32_F32
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I32_F32(MachInst)
Definition: decoder.cc:11496
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F32
Definition: instructions.hh:12025
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F64(MachInst)
Definition: decoder.cc:12155
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I16
Definition: instructions.hh:13997
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I64(MachInst)
Definition: decoder.cc:5762
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_U32
GPUStaticInst * decode_OP_DS__DS_SUB_U32(MachInst)
Definition: decoder.cc:7234
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_U16
GPUStaticInst * decode_OP_VOP2__V_MAX_U16(MachInst)
Definition: decoder.cc:4127
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_L_O
Definition: instructions.hh:41143
gem5::VegaISA::Inst_VOP3__V_FREXP_MANT_F64
Definition: instructions.hh:27179
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D(MachInst)
Definition: decoder.cc:8959
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16_HI(MachInst)
Definition: decoder.cc:9894
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_HI_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_I32_I24(MachInst)
Definition: decoder.cc:5864
gem5::VegaISA::Inst_VOP1__V_SQRT_F64
Definition: instructions.hh:9309
gem5::VegaISA::Inst_VOP3__V_CVT_F16_F32
Definition: instructions.hh:25931
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE
Definition: instructions.hh:39271
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_F32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_F32(MachInst)
Definition: decoder.cc:6644
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U32
Definition: instructions.hh:22225
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_AND_OR_B32
GPUStaticInst * decode_OPU_VOP3__V_AND_OR_B32(MachInst)
Definition: decoder.cc:6950
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_PCK(MachInst)
Definition: decoder.cc:8767
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_WB
GPUStaticInst * decode_OP_SMEM__S_DCACHE_WB(MachInst)
Definition: decoder.cc:10122
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFE_I32
GPUStaticInst * decode_OP_SOP2__S_BFE_I32(MachInst)
Definition: decoder.cc:4403
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U32
Definition: instructions.hh:22803
gem5::VegaISA::Inst_SOPC__S_CMP_LT_I32
Definition: instructions.hh:3907
gem5::VegaISA::Inst_SOP1__S_MOV_B64
Definition: instructions.hh:2213
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U16
Definition: instructions.hh:21749
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_CL(MachInst)
Definition: decoder.cc:9268
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F16
Definition: instructions.hh:10733
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_U64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_U64(MachInst)
Definition: decoder.cc:7795
gem5::VegaISA::Inst_SOP1__S_QUADMASK_B32
Definition: instructions.hh:3459
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U16
Definition: instructions.hh:14201
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_LZ(MachInst)
Definition: decoder.cc:9178
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:8701
gem5::VegaISA::Inst_SOPC__S_BITCMP1_B64
Definition: instructions.hh:4259
gem5::VegaISA::Inst_DS__DS_INC_RTN_U64
Definition: instructions.hh:33589
gem5::VegaISA::Inst_SOP2__S_SUB_I32
Definition: instructions.hh:147
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ASHR_I32
GPUStaticInst * decode_OP_SOP2__S_ASHR_I32(MachInst)
Definition: decoder.cc:4367
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MIN_U32
GPUStaticInst * decode_OP_SOP2__S_MIN_U32(MachInst)
Definition: decoder.cc:4217
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I16
Definition: instructions.hh:13895
gem5::VegaISA::Inst_MUBUF__BUFFER_WBINVL1
Definition: instructions.hh:36831
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I16(MachInst)
Definition: decoder.cc:5270
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F32(MachInst)
Definition: decoder.cc:12029
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F16(MachInst)
Definition: decoder.cc:11729
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_LEGACY_F32
GPUStaticInst * decode_OP_VOP2__V_MUL_LEGACY_F32(MachInst)
Definition: decoder.cc:3869
gem5::VegaISA::InFmt_SOPP
Definition: gpu_decoder.hh:1770
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MAD_U32_U24(MachInst)
Definition: decoder.cc:6566
gem5::VegaISA::Inst_DS__DS_NOP
Definition: instructions.hh:31629
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_U32
GPUStaticInst * decode_OP_DS__DS_MIN_U32(MachInst)
Definition: decoder.cc:7270
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAX_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAX_I16(MachInst)
Definition: decoder.cc:12906
gem5::VegaISA::Inst_SOP1__S_QUADMASK_B64
Definition: instructions.hh:3491
gem5::VegaISA::Inst_VOP1__V_FREXP_MANT_F16
Definition: instructions.hh:10041
gem5::VegaISA::Inst_SOP2__S_ASHR_I32
Definition: instructions.hh:1133
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_WB_VOL
GPUStaticInst * decode_OP_SMEM__S_DCACHE_WB_VOL(MachInst)
Definition: decoder.cc:10134
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_BYTE
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_BYTE(MachInst)
Definition: decoder.cc:9831
gem5::VegaISA::Inst_SOP1__S_BITSET0_B32
Definition: instructions.hh:2949
gem5::VegaISA::Inst_DS__DS_OR_RTN_B32
Definition: instructions.hh:32099
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F64(MachInst)
Definition: decoder.cc:5126
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U64
Definition: instructions.hh:16513
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F32(MachInst)
Definition: decoder.cc:11903
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I64(MachInst)
Definition: decoder.cc:12785
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR
Definition: instructions.hh:42543
gem5::VegaISA::InFmt_MUBUF
Definition: gpu_decoder.hh:1701
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XY
Definition: instructions.hh:35681
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F16
Definition: instructions.hh:10631
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SUB
Definition: instructions.hh:36999
gem5::VegaISA::Inst_VOP3__V_MAX_U32
Definition: instructions.hh:24471
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_O(MachInst)
Definition: decoder.cc:9073
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_X
Definition: instructions.hh:35795
gem5::VegaISA::Decoder::decode_OP_SOP1__S_QUADMASK_B32
GPUStaticInst * decode_OP_SOP1__S_QUADMASK_B32(MachInst)
Definition: decoder.cc:10782
gem5::VegaISA::InstFormat::iFmt_SOP1
InFmt_SOP1 iFmt_SOP1
Definition: gpu_decoder.hh:1917
gem5::VegaISA::Inst_SMEM__S_ATC_PROBE
Definition: instructions.hh:6071
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16(MachInst)
Definition: decoder.cc:10004
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_SCALE_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_SCALE_F32(MachInst)
Definition: decoder.cc:6740
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORDX4(MachInst)
Definition: decoder.cc:10061
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LSHRREV_B32
GPUStaticInst * decode_OP_VOP2__V_LSHRREV_B32(MachInst)
Definition: decoder.cc:3941
gem5::VegaISA::Inst_VOP3__V_FRACT_F32
Definition: instructions.hh:26475
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F32(MachInst)
Definition: decoder.cc:11975
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_SHORT_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_SHORT_D16_HI(MachInst)
Definition: decoder.cc:9570
gem5::VegaISA::Inst_DS__DS_WRAP_RTN_B32
Definition: instructions.hh:32439
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F64
Definition: instructions.hh:20593
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LT_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LT_I32(MachInst)
Definition: decoder.cc:4537
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_O_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F32(MachInst)
Definition: decoder.cc:4904
gem5::VegaISA::Inst_VOP1__V_FREXP_EXP_I32_F64
Definition: instructions.hh:9565
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F32
Definition: instructions.hh:17261
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_F16
GPUStaticInst * decode_OP_VOP2__V_SUB_F16(MachInst)
Definition: decoder.cc:4037
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_U64(MachInst)
Definition: decoder.cc:8096
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_B_O
Definition: instructions.hh:40027
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_F16
GPUStaticInst * decode_OPU_VOP3__V_MIN3_F16(MachInst)
Definition: decoder.cc:6863
gem5::VegaISA::Inst_SOPC__S_CMP_LT_U32
Definition: instructions.hh:4099
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG2_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG2_RTN_B32(MachInst)
Definition: decoder.cc:7463
gem5::VegaISA::Decoder::decode_OP_SOP1__S_CMOV_B32
GPUStaticInst * decode_OP_SOP1__S_CMOV_B32(MachInst)
Definition: decoder.cc:10554
gem5::VegaISA::Inst_VOPC__V_CMP_T_U16
Definition: instructions.hh:14371
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F32
Definition: instructions.hh:12535
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_F64
GPUStaticInst * decode_OP_DS__DS_CMPST_F64(MachInst)
Definition: decoder.cc:7673
gem5::VegaISA::Inst_VOPC__V_CMP_F_F64
Definition: instructions.hh:12773
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOVRELD_B64
GPUStaticInst * decode_OP_SOP1__S_MOVRELD_B64(MachInst)
Definition: decoder.cc:10812
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_CL
Definition: instructions.hh:40675
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F64
Definition: instructions.hh:20457
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SLEEP
GPUStaticInst * decode_OP_SOPP__S_SLEEP(MachInst)
Definition: decoder.cc:11075
gem5::VegaISA::Inst_SOP1__S_XOR_SAVEEXEC_B64
Definition: instructions.hh:3267
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2
Definition: instructions.hh:37359
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U32(MachInst)
Definition: decoder.cc:12527
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_RTN_B64
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_B64(MachInst)
Definition: decoder.cc:7843
gem5::VegaISA::Inst_SOPK__S_CMPK_LE_I32
Definition: instructions.hh:1765
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_O_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F64(MachInst)
Definition: decoder.cc:12131
gem5::VegaISA::Decoder::decode_OP_SOP2__S_OR_B64
GPUStaticInst * decode_OP_SOP2__S_OR_B64(MachInst)
Definition: decoder.cc:4265
gem5::VegaISA::Inst_DS__DS_MIN_RTN_U64
Definition: instructions.hh:33725
gem5::VegaISA::Inst_SOPP__S_SENDMSGHALT
Definition: instructions.hh:4933
gem5::VegaISA::Inst_VOP1__V_RSQ_F32
Definition: instructions.hh:9181
gem5::VegaISA::Inst_SOPK__S_CMPK_GT_U32
Definition: instructions.hh:1861
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LT_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LT_U32(MachInst)
Definition: decoder.cc:4573
gem5::VegaISA::Inst_DS__DS_GWS_SEMA_RELEASE_ALL
Definition: instructions.hh:34783
gem5::VegaISA::Inst_VOP1__V_RCP_F32
Definition: instructions.hh:9117
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F32(MachInst)
Definition: decoder.cc:12011
gem5::VegaISA::Inst_VOPC__V_CMP_F_I64
Definition: instructions.hh:16037
gem5::VegaISA::Inst_SOP1__S_RFE_B64
Definition: instructions.hh:3171
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:8629
gem5::VegaISA::Inst_SOPK__S_CMPK_LT_U32
Definition: instructions.hh:1925
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F32
Definition: instructions.hh:19267
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_D
Definition: instructions.hh:39343
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADDC_CO_U32
GPUStaticInst * decode_OP_VOP2__V_ADDC_CO_U32(MachInst)
Definition: decoder.cc:4013
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LE_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LE_U32(MachInst)
Definition: decoder.cc:4579
gem5::VegaISA::Inst_DS__DS_READ_I8
Definition: instructions.hh:32609
gem5::VegaISA::Decoder::decode_OP_SOP1__S_NOT_B64
GPUStaticInst * decode_OP_SOP1__S_NOT_B64(MachInst)
Definition: decoder.cc:10572
gem5::VegaISA::Decoder::decode_OP_SOPP__S_ENDPGM_SAVED
GPUStaticInst * decode_OP_SOPP__S_ENDPGM_SAVED(MachInst)
Definition: decoder.cc:11153
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U64(MachInst)
Definition: decoder.cc:12713
gem5::VegaISA::InFmt_MIMG::OP
unsigned int OP
Definition: gpu_decoder.hh:1666
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32(MachInst)
Definition: decoder.cc:6836
gem5::VegaISA::Decoder::decode_OP_SOP1__S_CMOV_B64
GPUStaticInst * decode_OP_SOP1__S_CMOV_B64(MachInst)
Definition: decoder.cc:10560
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_B64
GPUStaticInst * decode_OP_DS__DS_CMPST_B64(MachInst)
Definition: decoder.cc:7667
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I32
Definition: instructions.hh:22531
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F64(MachInst)
Definition: decoder.cc:5192
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U16(MachInst)
Definition: decoder.cc:5408
gem5::VegaISA::Inst_SOP2__S_NOR_B32
Definition: instructions.hh:861
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F16_I16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_I16(MachInst)
Definition: decoder.cc:6434
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U32(MachInst)
Definition: decoder.cc:12653
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_I32_I24
GPUStaticInst * decode_OP_VOP2__V_MUL_I32_I24(MachInst)
Definition: decoder.cc:3881
gem5::VegaISA::Inst_MIMG__IMAGE_GET_LOD
Definition: instructions.hh:41287
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F64_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_I32(MachInst)
Definition: decoder.cc:6128
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F64(MachInst)
Definition: decoder.cc:5084
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F16(MachInst)
Definition: decoder.cc:4766
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX3
Definition: instructions.hh:42093
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_OFF_F32_I4
GPUStaticInst * decode_OPU_VOP3__V_CVT_OFF_F32_I4(MachInst)
Definition: decoder.cc:6188
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U64
Definition: instructions.hh:17091
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:9751
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_F32
GPUStaticInst * decode_OPU_VOP3__V_MAX_F32(MachInst)
Definition: decoder.cc:5888
gem5::VegaISA::Inst_VOP1__V_RNDNE_F16
Definition: instructions.hh:10201
gem5::VegaISA::Inst_VOP3__V_LSHL_ADD_U32
Definition: instructions.hh:29497
gem5::VegaISA::Inst_VOP3__V_LDEXP_F32
Definition: instructions.hh:30435
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U64(MachInst)
Definition: decoder.cc:12845
gem5::VegaISA::Inst_DS__DS_READ_I16
Definition: instructions.hh:32675
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I16(MachInst)
Definition: decoder.cc:12287
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_GE_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_GE_U32(MachInst)
Definition: decoder.cc:10925
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U64(MachInst)
Definition: decoder.cc:12809
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SBYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SBYTE(MachInst)
Definition: decoder.cc:9509
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_I8
GPUStaticInst * decode_OP_DS__DS_READ_I8(MachInst)
Definition: decoder.cc:7529
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FFBH_U32
GPUStaticInst * decode_OPU_VOP3__V_FFBH_U32(MachInst)
Definition: decoder.cc:6374
gem5::VegaISA::Inst_DS__DS_WRITE_B32
Definition: instructions.hh:31395
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F32(MachInst)
Definition: decoder.cc:11897
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_U32
GPUStaticInst * decode_OP_DS__DS_ADD_U32(MachInst)
Definition: decoder.cc:7228
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_CL_O(MachInst)
Definition: decoder.cc:9226
gem5::VegaISA::Inst_VOP3__V_DIV_SCALE_F64
Definition: instructions.hh:29165
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BREV_B32
GPUStaticInst * decode_OP_SOP1__S_BREV_B32(MachInst)
Definition: decoder.cc:10590
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16(MachInst)
Definition: decoder.cc:9901
gem5::VegaISA::Inst_VOP3__V_FFBH_I32
Definition: instructions.hh:27115
gem5::VegaISA::Inst_VOP1__V_CVT_F32_U32
Definition: instructions.hh:8221
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_I32
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_I32(MachInst)
Definition: decoder.cc:11226
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I64(MachInst)
Definition: decoder.cc:5642
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FF1_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FF1_I32_B32(MachInst)
Definition: decoder.cc:10638
gem5::VegaISA::Inst_VOP3__V_READLANE_B32
Definition: instructions.hh:30469
gem5::VegaISA::Inst_SOP2__S_MIN_U32
Definition: instructions.hh:283
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_U32
GPUStaticInst * decode_OPU_VOP3__V_MIN_U32(MachInst)
Definition: decoder.cc:5906
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F64
Definition: instructions.hh:13725
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U64
Definition: instructions.hh:16955
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ(MachInst)
Definition: decoder.cc:9322
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U32(MachInst)
Definition: decoder.cc:12557
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F64(MachInst)
Definition: decoder.cc:5078
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F16(MachInst)
Definition: decoder.cc:11777
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
Definition: instructions.hh:38397
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_EQ_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_U32(MachInst)
Definition: decoder.cc:10907
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:10283
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_O(MachInst)
Definition: decoder.cc:9220
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F16
Definition: instructions.hh:11243
gem5::VegaISA::Inst_VOP3__V_CVT_F32_U32
Definition: instructions.hh:25803
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_L_O
Definition: instructions.hh:40279
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F32(MachInst)
Definition: decoder.cc:12059
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MAX_U32
GPUStaticInst * decode_OP_SOP2__S_MAX_U32(MachInst)
Definition: decoder.cc:4229
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RCP_F64
GPUStaticInst * decode_OP_VOP1__V_RCP_F64(MachInst)
Definition: decoder.cc:11412
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB(MachInst)
Definition: decoder.cc:8617
gem5::VegaISA::Inst_SOP1__S_MOVRELS_B64
Definition: instructions.hh:3555
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I16
Definition: instructions.hh:20831
gem5::VegaISA::Inst_VOP3__V_FRACT_F16
Definition: instructions.hh:27815
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F32
Definition: instructions.hh:10393
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_DEC
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_DEC(MachInst)
Definition: decoder.cc:10262
gem5::VegaISA::Inst_SOPC__S_CMP_LG_I32
Definition: instructions.hh:3811
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:10339
gem5::VegaISA::Inst_VOP3__V_CMP_O_F32
Definition: instructions.hh:18757
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U16(MachInst)
Definition: decoder.cc:5390
gem5::VegaISA::Inst_DS__DS_DEC_U64
Definition: instructions.hh:32969
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F16
Definition: instructions.hh:17567
gem5::VegaISA::Inst_VOPC__V_CMP_U_F64
Definition: instructions.hh:13045
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F16
Definition: instructions.hh:17839
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I16
Definition: instructions.hh:14507
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_OR3_B32
GPUStaticInst * decode_OPU_VOP3__V_OR3_B32(MachInst)
Definition: decoder.cc:6956
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SMIN
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:8845
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_SHORT_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_SHORT_D16_HI(MachInst)
Definition: decoder.cc:8525
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U32(MachInst)
Definition: decoder.cc:12635
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PK_U8_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_U8_F32(MachInst)
Definition: decoder.cc:6722
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F32
Definition: instructions.hh:19029
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F32(MachInst)
Definition: decoder.cc:5048
gem5::VegaISA::Inst_VOP2__V_ADD_F32
Definition: instructions.hh:6175
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_U_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F16(MachInst)
Definition: decoder.cc:11849
gem5::VegaISA::Decoder::decode_OP_SOPC__S_SETVSKIP
GPUStaticInst * decode_OP_SOPC__S_SETVSKIP(MachInst)
Definition: decoder.cc:10967
gem5::VegaISA::Inst_SOPP__S_CBRANCH_EXECZ
Definition: instructions.hh:4663
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_LZ
Definition: instructions.hh:39811
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_B64
GPUStaticInst * decode_OP_DS__DS_OR_B64(MachInst)
Definition: decoder.cc:7631
gem5::VegaISA::Inst_SOP2__S_LSHL_B32
Definition: instructions.hh:997
gem5::VegaISA::Inst_VOP3__V_QSAD_PK_U16_U8
Definition: instructions.hh:29313
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I16
Definition: instructions.hh:20729
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B64
GPUStaticInst * decode_OP_DS__DS_WRITE_B64(MachInst)
Definition: decoder.cc:7649
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U32
Definition: instructions.hh:15901
gem5::VegaISA::Inst_SOP1__S_ANDN2_SAVEEXEC_B64
Definition: instructions.hh:3299
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_U16
GPUStaticInst * decode_OP_VOP2__V_MIN_U16(MachInst)
Definition: decoder.cc:4139
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_X
Definition: instructions.hh:37827
gem5::VegaISA::Inst_VOP3__V_EXP_LEGACY_F32
Definition: instructions.hh:27911
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_INV
GPUStaticInst * decode_OP_SMEM__S_DCACHE_INV(MachInst)
Definition: decoder.cc:10116
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F16
Definition: instructions.hh:17465
gem5::VegaISA::Inst_SOPP__S_INCPERFLEVEL
Definition: instructions.hh:5023
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_U32
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_U32(MachInst)
Definition: decoder.cc:11232
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F64(MachInst)
Definition: decoder.cc:12095
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX4
Definition: instructions.hh:5575
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFI_B32
GPUStaticInst * decode_OPU_VOP3__V_BFI_B32(MachInst)
Definition: decoder.cc:6608
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_F16
GPUStaticInst * decode_OPU_VOP3__V_MIN_F16(MachInst)
Definition: decoder.cc:6074
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:9733
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_SCALE_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_SCALE_F64(MachInst)
Definition: decoder.cc:6746
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_B_CL
Definition: instructions.hh:40783
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_RTN_U32
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_U32(MachInst)
Definition: decoder.cc:7379
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F32(MachInst)
Definition: decoder.cc:11933
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_I64
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_I64(MachInst)
Definition: decoder.cc:10668
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I16(MachInst)
Definition: decoder.cc:12305
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY(MachInst)
Definition: decoder.cc:9413
gem5::VegaISA::Inst_DS__DS_RSUB_SRC2_U32
Definition: instructions.hh:34363
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F16(MachInst)
Definition: decoder.cc:11723
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LERP_U8
GPUStaticInst * decode_OPU_VOP3__V_LERP_U8(MachInst)
Definition: decoder.cc:6626
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U64
Definition: instructions.hh:23925
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_B32
GPUStaticInst * decode_OP_DS__DS_XOR_B32(MachInst)
Definition: decoder.cc:7294
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ANDN1_WREXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN1_WREXEC_B64(MachInst)
Definition: decoder.cc:10850
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I32
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I32(MachInst)
Definition: decoder.cc:5924
gem5::VegaISA::Inst_SOPC__S_CMP_LG_U32
Definition: instructions.hh:4003
gem5::VegaISA::Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER
Definition: instructions.hh:5173
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_AND
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_AND(MachInst)
Definition: decoder.cc:10416
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_BYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_BYTE(MachInst)
Definition: decoder.cc:9551
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SQRT_F32
GPUStaticInst * decode_OP_VOP1__V_SQRT_F32(MachInst)
Definition: decoder.cc:11424
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_B32
GPUStaticInst * decode_OP_DS__DS_CMPST_B32(MachInst)
Definition: decoder.cc:7324
gem5::VegaISA::Decoder::subDecode_OPU_VOP3
GPUStaticInst * subDecode_OPU_VOP3(MachInst)
Definition: decoder.cc:3776
gem5::VegaISA::Inst_VOP1__V_FREXP_EXP_I16_F16
Definition: instructions.hh:10073
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAD_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAD_I16(MachInst)
Definition: decoder.cc:12857
gem5::VegaISA::Inst_VOP3__V_MAX_I32
Definition: instructions.hh:24403
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F64
Definition: instructions.hh:20491
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I64(MachInst)
Definition: decoder.cc:5756
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F64
Definition: instructions.hh:13623
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_U64
GPUStaticInst * decode_OP_DS__DS_SUB_U64(MachInst)
Definition: decoder.cc:7577
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORD(MachInst)
Definition: decoder.cc:9527
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F32(MachInst)
Definition: decoder.cc:11969
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAX_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAX_F16(MachInst)
Definition: decoder.cc:12983
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_D_CL
Definition: instructions.hh:39379
gem5::VegaISA::Inst_VOP3__V_CMP_T_I16
Definition: instructions.hh:20933
gem5::VegaISA::Inst_VOP3__V_RNDNE_F64
Definition: instructions.hh:26411
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U16
Definition: instructions.hh:14881
gem5::VegaISA::Decoder::decode_OP_SMEM__S_STORE_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORDX4(MachInst)
Definition: decoder.cc:10022
gem5::VegaISA::Inst_VOP3__V_FMA_F64
Definition: instructions.hh:28407
gem5::VegaISA::Inst_VOP1__V_RCP_IFLAG_F32
Definition: instructions.hh:9149
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:8707
gem5::VegaISA::Inst_SOP2__S_BFE_I32
Definition: instructions.hh:1337
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U16
Definition: instructions.hh:21103
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN(MachInst)
Definition: decoder.cc:8785
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_DEC
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_DEC(MachInst)
Definition: decoder.cc:8893
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_RTN_U64
GPUStaticInst * decode_OP_DS__DS_SUB_RTN_U64(MachInst)
Definition: decoder.cc:7753
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U16_D16_HI
GPUStaticInst * decode_OP_DS__DS_READ_U16_D16_HI(MachInst)
Definition: decoder.cc:7740
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U32
Definition: instructions.hh:15391
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F16
Definition: instructions.hh:10971
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F16(MachInst)
Definition: decoder.cc:11789
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_TRUNC_F16
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F16(MachInst)
Definition: decoder.cc:6506
gem5::VegaISA::Inst_VOP3__V_MAX_F32
Definition: instructions.hh:24335
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:9727
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F32
Definition: instructions.hh:12093
gem5::VegaISA::Inst_VOP3__V_LOG_F32
Definition: instructions.hh:26667
gem5::VegaISA::Inst_DS__DS_WRXCHG_RTN_B64
Definition: instructions.hh:33929
gem5::VegaISA::Inst_VOP3__V_SQRT_F64
Definition: instructions.hh:26891
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16_HI(MachInst)
Definition: decoder.cc:10085
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:8749
gem5::VegaISA::Inst_DS__DS_RSUB_RTN_U32
Definition: instructions.hh:31827
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LG_U64
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_U64(MachInst)
Definition: decoder.cc:10985
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CEIL_F16
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F16(MachInst)
Definition: decoder.cc:6500
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PK_I16_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_I16_I32(MachInst)
Definition: decoder.cc:7173
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_READLANE_B32
GPUStaticInst * decode_OPU_VOP3__V_READLANE_B32(MachInst)
Definition: decoder.cc:7089
gem5::VegaISA::Inst_VOP2__V_SUB_F16
Definition: instructions.hh:7247
gem5::VegaISA::Inst_VOP3__V_MAC_F16
Definition: instructions.hh:25137
gem5::VegaISA::Inst_FLAT__FLAT_STORE_BYTE
Definition: instructions.hh:41945
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:8452
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX2
Definition: instructions.hh:5359
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F16
Definition: instructions.hh:18417
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ(MachInst)
Definition: decoder.cc:9419
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_SHORT
Definition: instructions.hh:36609
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SMAX
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:10402
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F64
Definition: instructions.hh:13521
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_U64
GPUStaticInst * decode_OP_DS__DS_INC_U64(MachInst)
Definition: decoder.cc:7589
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F64(MachInst)
Definition: decoder.cc:4652
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_SHORT_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_SHORT_D16_HI(MachInst)
Definition: decoder.cc:9852
gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B32
Definition: instructions.hh:2757
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U32(MachInst)
Definition: decoder.cc:5582
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I64(MachInst)
Definition: decoder.cc:12707
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F16
Definition: instructions.hh:10529
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_I16
GPUStaticInst * decode_OPU_VOP3__V_MAD_I16(MachInst)
Definition: decoder.cc:6974
gem5::VegaISA::Decoder::decode_OP_VINTRP__V_INTERP_P2_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_P2_F32(MachInst)
Definition: decoder.cc:11184
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_B
Definition: instructions.hh:40747
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_U64(MachInst)
Definition: decoder.cc:7583
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U16
Definition: instructions.hh:21001
gem5::VegaISA::Decoder::decode_OP_DS__DS_MSKOR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_MSKOR_RTN_B32(MachInst)
Definition: decoder.cc:7451
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW
Definition: instructions.hh:35909
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RNDNE_F16
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F16(MachInst)
Definition: decoder.cc:6512
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U32
Definition: instructions.hh:22633
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_U16
GPUStaticInst * decode_OPU_VOP3__V_MAX3_U16(MachInst)
Definition: decoder.cc:6898
gem5::VegaISA::Decoder::decode_OP_SOPP__S_ICACHE_INV
GPUStaticInst * decode_OP_SOPP__S_ICACHE_INV(MachInst)
Definition: decoder.cc:11105
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16(MachInst)
Definition: decoder.cc:10067
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I64
Definition: instructions.hh:16785
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U64(MachInst)
Definition: decoder.cc:12851
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_UBYTE
Definition: instructions.hh:36251
gem5::VegaISA::Inst_VOP3__V_LDEXP_F64
Definition: instructions.hh:30299
gem5::VegaISA::Inst_DS__DS_SUB_U64
Definition: instructions.hh:32873
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND
Definition: instructions.hh:42469
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX4
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:9824
gem5::VegaISA::Inst_DS__DS_MAX_RTN_I64
Definition: instructions.hh:33691
gem5::VegaISA::Inst_SOPP__S_SET_GPR_IDX_OFF
Definition: instructions.hh:5263
gem5::VegaISA::Inst_VOP3__V_OR_B32
Definition: instructions.hh:24641
gem5::VegaISA::Inst_VOP2__V_MUL_LEGACY_F32
Definition: instructions.hh:6277
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F16
Definition: instructions.hh:17941
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
Definition: instructions.hh:36023
gem5::VegaISA::Decoder::tableSubDecode_OP_SCRATCH
static IsaDecodeMethod tableSubDecode_OP_SCRATCH[128]
Definition: gpu_decoder.hh:69
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_F64(MachInst)
Definition: decoder.cc:6194
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_F32
GPUStaticInst * decode_OP_VOP2__V_MUL_F32(MachInst)
Definition: decoder.cc:3875
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_F32
GPUStaticInst * decode_OP_VOP2__V_SUB_F32(MachInst)
Definition: decoder.cc:3857
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_STORE_MIP
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_MIP(MachInst)
Definition: decoder.cc:8797
gem5::VegaISA::Inst_DS__DS_CONDXCHG32_RTN_B64
Definition: instructions.hh:34269
gem5::VegaISA::Inst_VOP3__V_CUBESC_F32
Definition: instructions.hh:28155
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F64(MachInst)
Definition: decoder.cc:5228
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FRACT_F16
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F16(MachInst)
Definition: decoder.cc:6518
gem5::VegaISA::Inst_DS__DS_MAX_RTN_F64
Definition: instructions.hh:34133
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F16(MachInst)
Definition: decoder.cc:4658
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I32(MachInst)
Definition: decoder.cc:12611
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LG_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F16(MachInst)
Definition: decoder.cc:11735
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10752
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_F32
GPUStaticInst * decode_OP_VOP2__V_SUBREV_F32(MachInst)
Definition: decoder.cc:3863
gem5::VegaISA::Inst_VOPC__V_CMP_F_F32
Definition: instructions.hh:11685
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CUBETC_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBETC_F32(MachInst)
Definition: decoder.cc:6584
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_SUB_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_SUB_U16(MachInst)
Definition: decoder.cc:12934
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F16(MachInst)
Definition: decoder.cc:11825
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F16(MachInst)
Definition: decoder.cc:11855
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I32
Definition: instructions.hh:22327
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SAD_HI_U8
GPUStaticInst * decode_OPU_VOP3__V_SAD_HI_U8(MachInst)
Definition: decoder.cc:6704
gem5::VegaISA::Inst_SOP2__S_ORN2_B32
Definition: instructions.hh:725
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F32(MachInst)
Definition: decoder.cc:4868
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XY
Definition: instructions.hh:38017
gem5::VegaISA::Inst_VOP1__V_COS_F32
Definition: instructions.hh:9373
gem5::VegaISA::Inst_VOP1__V_FRACT_F32
Definition: instructions.hh:8893
gem5::VegaISA::Inst_VOPC__V_CMP_T_I32
Definition: instructions.hh:15187
gem5::VegaISA::Inst_VOP3__V_INTERP_P1LL_F16
Definition: instructions.hh:30057
gem5::VegaISA::Inst_VOP2__V_OR_B32
Definition: instructions.hh:6821
gem5::VegaISA::Inst_VOPC__V_CMP_F_I32
Definition: instructions.hh:14949
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:8695
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:8416
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B(MachInst)
Definition: decoder.cc:8977
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_I16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_I16_F16(MachInst)
Definition: decoder.cc:11539
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:10493
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F64
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F64(MachInst)
Definition: decoder.cc:6398
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U64(MachInst)
Definition: decoder.cc:5792
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F32
Definition: instructions.hh:19063
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F16(MachInst)
Definition: decoder.cc:4724
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SQRT_F64
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F64(MachInst)
Definition: decoder.cc:6344
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I16(MachInst)
Definition: decoder.cc:5252
gem5::VegaISA::Decoder::decode_OP_DS__DS_MSKOR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_MSKOR_RTN_B64(MachInst)
Definition: decoder.cc:7819
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F32(MachInst)
Definition: decoder.cc:4886
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U32(MachInst)
Definition: decoder.cc:5522
gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE1
Definition: instructions.hh:8605
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I32
Definition: instructions.hh:15493
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GET_RESINFO
GPUStaticInst * decode_OP_MIMG__IMAGE_GET_RESINFO(MachInst)
Definition: decoder.cc:8815
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F32
Definition: instructions.hh:19097
gem5::VegaISA::Inst_DS__DS_SUB_RTN_U32
Definition: instructions.hh:31793
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_U32
GPUStaticInst * decode_OP_VOP2__V_ADD_U32(MachInst)
Definition: decoder.cc:4157
gem5::VegaISA::Inst_VOP1__V_CVT_I16_F16
Definition: instructions.hh:9849
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_O(MachInst)
Definition: decoder.cc:9286
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_INC_SRC2_U64(MachInst)
Definition: decoder.cc:8066
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F32
Definition: instructions.hh:12229
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F64
Definition: instructions.hh:13487
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U32
Definition: instructions.hh:15969
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
Definition: instructions.hh:37941
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U64(MachInst)
Definition: decoder.cc:12755
gem5::VegaISA::Inst_VOP2__V_MUL_F16
Definition: instructions.hh:7315
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_BYTE
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_BYTE(MachInst)
Definition: decoder.cc:8506
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_AND
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_AND(MachInst)
Definition: decoder.cc:10234
gem5::VegaISA::Inst_SOP2__S_NAND_B64
Definition: instructions.hh:827
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U64(MachInst)
Definition: decoder.cc:5780
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ2ST64_B32
GPUStaticInst * decode_OP_DS__DS_READ2ST64_B32(MachInst)
Definition: decoder.cc:7523
gem5::VegaISA::IsaDecodeMethod
GPUStaticInst *(Decoder::*)(MachInst) IsaDecodeMethod
Definition: gpu_decoder.hh:50
gem5::VegaISA::Inst_VOP3__V_PERM_B32
Definition: instructions.hh:29785
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F64(MachInst)
Definition: decoder.cc:6734
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I32
Definition: instructions.hh:22361
gem5::VegaISA::Inst_VOP2__V_AND_B32
Definition: instructions.hh:6787
gem5::VegaISA::Inst_VOP3__V_TRUNC_F32
Definition: instructions.hh:26507
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B128
GPUStaticInst * decode_OP_DS__DS_WRITE_B128(MachInst)
Definition: decoder.cc:8144
gem5::VegaISA::Inst_SOP1__S_BREV_B32
Definition: instructions.hh:2437
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U16(MachInst)
Definition: decoder.cc:12461
gem5::VegaISA::Decoder::decode_OP_VOP1__V_LOG_F16
GPUStaticInst * decode_OP_VOP1__V_LOG_F16(MachInst)
Definition: decoder.cc:11563
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BCNT0_I32_B64
GPUStaticInst * decode_OP_SOP1__S_BCNT0_I32_B64(MachInst)
Definition: decoder.cc:10608
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_CL
Definition: instructions.hh:40459
gem5::VegaISA::Inst_VOP3__V_CVT_I16_F16
Definition: instructions.hh:27431
gem5::VegaISA::Inst_VOP3__V_ADD3_U32
Definition: instructions.hh:29569
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE_D16_HI(MachInst)
Definition: decoder.cc:8564
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_U32(MachInst)
Definition: decoder.cc:6140
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX4
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX4(MachInst)
Definition: decoder.cc:9595
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_B64
GPUStaticInst * decode_OP_DS__DS_AND_B64(MachInst)
Definition: decoder.cc:7625
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F32(MachInst)
Definition: decoder.cc:6728
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_I16
GPUStaticInst * decode_OPU_VOP3__V_MED3_I16(MachInst)
Definition: decoder.cc:6912
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_U32_U16
GPUStaticInst * decode_OPU_VOP3__V_MAD_U32_U16(MachInst)
Definition: decoder.cc:6842
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MIN_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_MIN_I16(MachInst)
Definition: decoder.cc:12913
gem5::VegaISA::Inst_MIMG__IMAGE_STORE_PCK
Definition: instructions.hh:38723
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F64(MachInst)
Definition: decoder.cc:12191
gem5::VegaISA::Inst_VOP2__V_SUB_CO_U32
Definition: instructions.hh:7027
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I32(MachInst)
Definition: decoder.cc:5534
gem5::VegaISA::Inst_VOP3__V_MIN_F64
Definition: instructions.hh:30231
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_ASHRREV_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_ASHRREV_I16(MachInst)
Definition: decoder.cc:12899
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U32(MachInst)
Definition: decoder.cc:5516
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U16(MachInst)
Definition: decoder.cc:12335
gem5::VegaISA::Inst_VOP3__V_CUBEID_F32
Definition: instructions.hh:28119
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P1LL_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1LL_F16(MachInst)
Definition: decoder.cc:7010
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:10472
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U8
GPUStaticInst * decode_OP_DS__DS_READ_U8(MachInst)
Definition: decoder.cc:7535
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_U32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_U32(MachInst)
Definition: decoder.cc:7427
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_U16
GPUStaticInst * decode_OPU_VOP3__V_MED3_U16(MachInst)
Definition: decoder.cc:6919
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:10206
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U16(MachInst)
Definition: decoder.cc:5426
gem5::VegaISA::InstFormat::iFmt_FLAT
InFmt_FLAT iFmt_FLAT
Definition: gpu_decoder.hh:1906
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE2_B64
GPUStaticInst * decode_OP_DS__DS_WRITE2_B64(MachInst)
Definition: decoder.cc:7655
gem5::VegaISA::Inst_SOPP__S_CBRANCH_CDBGSYS
Definition: instructions.hh:5113
gem5::VegaISA::Inst_VOP1__V_EXP_F32
Definition: instructions.hh:9053
gem5::VegaISA::InFmt_VOPC::OP
unsigned int OP
Definition: gpu_decoder.hh:1828
gem5::VegaISA::Inst_VOP3__V_AND_OR_B32
Definition: instructions.hh:29641
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL_B32
GPUStaticInst * decode_OP_SOP2__S_LSHL_B32(MachInst)
Definition: decoder.cc:4343
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_F64
GPUStaticInst * decode_OPU_VOP3__V_ADD_F64(MachInst)
Definition: decoder.cc:7035
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RNDNE_F64
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F64(MachInst)
Definition: decoder.cc:6254
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:10311
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_I16
GPUStaticInst * decode_OP_VOP2__V_MAX_I16(MachInst)
Definition: decoder.cc:4133
gem5::VegaISA::Inst_DS__DS_SUB_SRC2_U64
Definition: instructions.hh:35095
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I32(MachInst)
Definition: decoder.cc:5546
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:10220
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I64(MachInst)
Definition: decoder.cc:5738
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ
Definition: instructions.hh:35871
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_U16
GPUStaticInst * decode_OPU_VOP3__V_SUB_U16(MachInst)
Definition: decoder.cc:6032
gem5::VegaISA::Inst_VOP3__V_CMP_F_U64
Definition: instructions.hh:23143
gem5::VegaISA::Inst_DS__DS_CMPST_RTN_F64
Definition: instructions.hh:34065
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_DWORDX2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_DWORDX2(MachInst)
Definition: decoder.cc:8539
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MSAD_U8
GPUStaticInst * decode_OPU_VOP3__V_MSAD_U8(MachInst)
Definition: decoder.cc:6764
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U32(MachInst)
Definition: decoder.cc:5600
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_MOV_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_MOV_F32(MachInst)
Definition: decoder.cc:7004
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ASHRREV_I32
GPUStaticInst * decode_OP_VOP2__V_ASHRREV_I32(MachInst)
Definition: decoder.cc:3947
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F16(MachInst)
Definition: decoder.cc:4664
gem5::VegaISA::InstFormat::iFmt_VOP3B
InFmt_VOP3B iFmt_VOP3B
Definition: gpu_decoder.hh:1927
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_DISCARD_X2
GPUStaticInst * decode_OP_SMEM__S_DCACHE_DISCARD_X2(MachInst)
Definition: decoder.cc:10171
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I64(MachInst)
Definition: decoder.cc:5744
gem5::VegaISA::Inst_VOP1__V_FRACT_F16
Definition: instructions.hh:10233
gem5::VegaISA::Decoder::decode_OP_SOP1__S_RFE_B64
GPUStaticInst * decode_OP_SOP1__S_RFE_B64(MachInst)
Definition: decoder.cc:10728
gem5::VegaISA::Inst_VOPC__V_CMP_T_I16
Definition: instructions.hh:14099
gem5::VegaISA::Inst_DS__DS_XOR_B32
Definition: instructions.hh:31331
gem5::VegaISA::Inst_VOP3__V_LSHRREV_B64
Definition: instructions.hh:30673
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_INC_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:8743
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F16
Definition: instructions.hh:11481
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FMA_F64
GPUStaticInst * decode_OPU_VOP3__V_FMA_F64(MachInst)
Definition: decoder.cc:6620
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER8H_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER8H_PCK(MachInst)
Definition: decoder.cc:9153
gem5::VegaISA::Inst_DS__DS_MSKOR_RTN_B32
Definition: instructions.hh:32167
gem5::VegaISA::Inst_DS__DS_CMPST_RTN_B64
Definition: instructions.hh:34031
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I64(MachInst)
Definition: decoder.cc:5750
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_B96
GPUStaticInst * decode_OP_DS__DS_READ_B96(MachInst)
Definition: decoder.cc:8150
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE2
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE2(MachInst)
Definition: decoder.cc:11304
gem5::VegaISA::Inst_SOPK__S_CMPK_GT_I32
Definition: instructions.hh:1669
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U64
Definition: instructions.hh:23755
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOV_B64
GPUStaticInst * decode_OP_SOP1__S_MOV_B64(MachInst)
Definition: decoder.cc:10548
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBREV_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_CO_U32(MachInst)
Definition: decoder.cc:5972
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U64(MachInst)
Definition: decoder.cc:12737
gem5::VegaISA::Inst_SOPK__S_CMPK_LT_I32
Definition: instructions.hh:1733
gem5::VegaISA::Inst_SOP2__S_SUBB_U32
Definition: instructions.hh:215
gem5::VegaISA::Inst_SOPK__S_CMPK_GE_U32
Definition: instructions.hh:1893
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_I64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_I64(MachInst)
Definition: decoder.cc:7783
gem5::VegaISA::Inst_VOP1__V_MOV_B32
Definition: instructions.hh:8061
gem5::VegaISA::Inst_SOP1__S_CMOV_B64
Definition: instructions.hh:2277
gem5::VegaISA::Inst_DS__DS_XOR_B64
Definition: instructions.hh:33193
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_LO_U16
GPUStaticInst * decode_OP_VOP2__V_MUL_LO_U16(MachInst)
Definition: decoder.cc:4091
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F16(MachInst)
Definition: decoder.cc:11771
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P1_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1_F32(MachInst)
Definition: decoder.cc:6992
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY(MachInst)
Definition: decoder.cc:9340
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F32(MachInst)
Definition: decoder.cc:12017
gem5::VegaISA::Inst_VOP2__V_XOR_B32
Definition: instructions.hh:6855
gem5::VegaISA::Inst_VOP3__V_LSHLREV_B64
Definition: instructions.hh:30639
gem5::VegaISA::Decoder::decode_OP_VOP2__V_CNDMASK_B32
GPUStaticInst * decode_OP_VOP2__V_CNDMASK_B32(MachInst)
Definition: decoder.cc:3845
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RCP_IFLAG_F32
GPUStaticInst * decode_OPU_VOP3__V_RCP_IFLAG_F32(MachInst)
Definition: decoder.cc:6314
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_F16
GPUStaticInst * decode_OPU_VOP3__V_MAX_F16(MachInst)
Definition: decoder.cc:6068
gem5::VegaISA::Inst_DS__DS_WRXCHG_RTN_B32
Definition: instructions.hh:32201
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_U32
GPUStaticInst * decode_OPU_VOP3__V_MAX_U32(MachInst)
Definition: decoder.cc:5912
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FFBH_U32
GPUStaticInst * decode_OP_VOP1__V_FFBH_U32(MachInst)
Definition: decoder.cc:11460
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_I32_F32(MachInst)
Definition: decoder.cc:6152
gem5::VegaISA::Inst_SOP2__S_MIN_I32
Definition: instructions.hh:249
gem5::VegaISA::Decoder::decode_OP_SOP2__S_XNOR_B64
GPUStaticInst * decode_OP_SOP2__S_XNOR_B64(MachInst)
Definition: decoder.cc:4337
gem5::VegaISA::Inst_VOP1__V_EXP_LEGACY_F32
Definition: instructions.hh:10329
gem5::VegaISA::InFmt_VINTRP
Definition: gpu_decoder.hh:1776
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_F32(MachInst)
Definition: decoder.cc:7975
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_O(MachInst)
Definition: decoder.cc:9043
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I16(MachInst)
Definition: decoder.cc:12383
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_LOAD_DWORD
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_LOAD_DWORD(MachInst)
Definition: decoder.cc:9959
gem5::VegaISA::Decoder::decode_OP_SOP1__S_AND_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_AND_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10734
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I16_F16
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I16_F16(MachInst)
Definition: decoder.cc:11581
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD(MachInst)
Definition: decoder.cc:9601
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F64
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F64(MachInst)
Definition: decoder.cc:11484
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_L_O
Definition: instructions.hh:40927
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F16(MachInst)
Definition: decoder.cc:4694
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CLREXCP
GPUStaticInst * decode_OP_VOP1__V_CLREXCP(MachInst)
Definition: decoder.cc:11508
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F32(MachInst)
Definition: decoder.cc:4964
gem5::VegaISA::Inst_VOP3__V_MUL_HI_U32_U24
Definition: instructions.hh:24267
gem5::VegaISA::Inst_SOPK__S_SETREG_B32
Definition: instructions.hh:2117
gem5::VegaISA::Inst_SOPP__S_ENDPGM
Definition: instructions.hh:4449
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MAX_I32
GPUStaticInst * decode_OP_SOP2__S_MAX_I32(MachInst)
Definition: decoder.cc:4223
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_I32
GPUStaticInst * decode_OPU_VOP3__V_MED3_I32(MachInst)
Definition: decoder.cc:6686
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I32
Definition: instructions.hh:15663
gem5::VegaISA::Inst_VOP3__V_RSQ_F32
Definition: instructions.hh:26763
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F64(MachInst)
Definition: decoder.cc:5144
gem5::VegaISA::InFmt_FLAT::SEG
unsigned int SEG
Definition: gpu_decoder.hh:1636
gem5::VegaISA::Inst_VOP3__V_RCP_F32
Definition: instructions.hh:26699
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U16
Definition: instructions.hh:14269
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F32(MachInst)
Definition: decoder.cc:11957
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U16
Definition: instructions.hh:21681
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U64(MachInst)
Definition: decoder.cc:12839
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD(MachInst)
Definition: decoder.cc:8755
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I64(MachInst)
Definition: decoder.cc:12773
gem5::VegaISA::Inst_VOP3__V_MAX_F64
Definition: instructions.hh:30265
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP(MachInst)
Definition: decoder.cc:8761
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ORN1_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ORN1_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10843
gem5::VegaISA::Inst_SOP2__S_ANDN2_B32
Definition: instructions.hh:657
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_HI_I32
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_I32(MachInst)
Definition: decoder.cc:7077
gem5::VegaISA::Inst_SOP2__S_XNOR_B32
Definition: instructions.hh:929
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F64
Definition: instructions.hh:20049
gem5::VegaISA::Inst_SOPP__S_ICACHE_INV
Definition: instructions.hh:4993
gem5::VegaISA::InstFormat::iFmt_VOP2
InFmt_VOP2 iFmt_VOP2
Definition: gpu_decoder.hh:1924
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_USHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_USHORT(MachInst)
Definition: decoder.cc:9515
gem5::VegaISA::Decoder::decode_OP_DS__DS_APPEND
GPUStaticInst * decode_OP_DS__DS_APPEND(MachInst)
Definition: decoder.cc:8036
gem5::VegaISA::Inst_DS__DS_MAX_RTN_U64
Definition: instructions.hh:33759
gem5::VegaISA::Decoder::decode_OP_VOP1__V_COS_F32
GPUStaticInst * decode_OP_VOP1__V_COS_F32(MachInst)
Definition: decoder.cc:11442
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F64
Definition: instructions.hh:20219
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_L
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_L(MachInst)
Definition: decoder.cc:8923
gem5::VegaISA::Inst_VOP3__V_INTERP_MOV_F32
Definition: instructions.hh:30023
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:10521
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F64(MachInst)
Definition: decoder.cc:12251
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FMA_F32
GPUStaticInst * decode_OPU_VOP3__V_FMA_F32(MachInst)
Definition: decoder.cc:6614
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MADAK_F32
GPUStaticInst * decode_OP_VOP2__V_MADAK_F32(MachInst)
Definition: decoder.cc:3989
gem5::VegaISA::Inst_VOP1__V_FLOOR_F16
Definition: instructions.hh:10105
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U16
Definition: instructions.hh:14167
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PK_U16_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_U16_U32(MachInst)
Definition: decoder.cc:7167
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O(MachInst)
Definition: decoder.cc:9013
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I16
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I16(MachInst)
Definition: decoder.cc:6062
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ADDC_U32
GPUStaticInst * decode_OP_SOP2__S_ADDC_U32(MachInst)
Definition: decoder.cc:4199
gem5::VegaISA::Inst_DS__DS_MSKOR_RTN_B64
Definition: instructions.hh:33895
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O
Definition: instructions.hh:41575
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I64
Definition: instructions.hh:23483
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F64
Definition: instructions.hh:13113
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_PACK_B32_F16
GPUStaticInst * decode_OPU_VOP3__V_PACK_B32_F16(MachInst)
Definition: decoder.cc:7221
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I64(MachInst)
Definition: decoder.cc:5636
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX4
Definition: instructions.hh:36525
gem5::VegaISA::Inst_SOP2__S_CBRANCH_G_FORK
Definition: instructions.hh:1439
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_U16
GPUStaticInst * decode_OPU_VOP3__V_MAX_U16(MachInst)
Definition: decoder.cc:6080
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_OR_RTN_B32(MachInst)
Definition: decoder.cc:7439
gem5::VegaISA::Inst_VOP3__V_SUB_U16
Definition: instructions.hh:25205
gem5::VegaISA::Inst_VOP2__V_MIN_U32
Definition: instructions.hh:6617
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I64(MachInst)
Definition: decoder.cc:12797
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SBYTE_D16
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SBYTE_D16(MachInst)
Definition: decoder.cc:8274
gem5::VegaISA::Inst_SOP1__S_BITSET0_B64
Definition: instructions.hh:2981
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F64(MachInst)
Definition: decoder.cc:12173
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F32
Definition: instructions.hh:12569
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F64(MachInst)
Definition: decoder.cc:5090
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_QSAD_PK_U16_U8
GPUStaticInst * decode_OPU_VOP3__V_QSAD_PK_U16_U8(MachInst)
Definition: decoder.cc:6770
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:8827
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FMA_LEGACY_F16
GPUStaticInst * decode_OPU_VOP3__V_FMA_LEGACY_F16(MachInst)
Definition: decoder.cc:6824
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:9715
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F64_I32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_I32(MachInst)
Definition: decoder.cc:11220
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:9992
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_U16
GPUStaticInst * decode_OP_VOP2__V_SUBREV_U16(MachInst)
Definition: decoder.cc:4085
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SWAP
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:10360
gem5::VegaISA::Inst_VOP2__V_ASHRREV_I16
Definition: instructions.hh:7659
gem5::VegaISA::Inst_VOP3__V_CVT_OFF_F32_I4
Definition: instructions.hh:26059
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_WBINVL1
GPUStaticInst * decode_OP_MUBUF__BUFFER_WBINVL1(MachInst)
Definition: decoder.cc:9607
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SUB
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SUB(MachInst)
Definition: decoder.cc:8839
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX4
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX4(MachInst)
Definition: decoder.cc:8254
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_OR_B32
GPUStaticInst * decode_OPU_VOP3__V_OR_B32(MachInst)
Definition: decoder.cc:5942
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U16(MachInst)
Definition: decoder.cc:5402
gem5::VegaISA::Inst_SMEM__S_STORE_DWORD
Definition: instructions.hh:5683
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FFBL_B32
GPUStaticInst * decode_OPU_VOP3__V_FFBL_B32(MachInst)
Definition: decoder.cc:6380
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I16(MachInst)
Definition: decoder.cc:5276
gem5::VegaISA::Inst_VOP3__V_SUB_CO_U32
Definition: instructions.hh:24815
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_AND_B32
GPUStaticInst * decode_OPU_VOP3__V_AND_B32(MachInst)
Definition: decoder.cc:5936
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I64(MachInst)
Definition: decoder.cc:5768
gem5::VegaISA::Inst_VOP1__V_CVT_FLR_I32_F32
Definition: instructions.hh:8445
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_L
Definition: instructions.hh:40495
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_AND_X2
Definition: instructions.hh:37647
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U64(MachInst)
Definition: decoder.cc:5696
gem5::VegaISA::Inst_DS__DS_AND_B32
Definition: instructions.hh:31267
gem5::VegaISA::Inst_SMEM__S_BUFFER_STORE_DWORDX4
Definition: instructions.hh:5863
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_I16
GPUStaticInst * decode_OPU_VOP3__V_ADD_I16(MachInst)
Definition: decoder.cc:7207
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_XOR
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_XOR(MachInst)
Definition: decoder.cc:8881
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I16
Definition: instructions.hh:21409
gem5::VegaISA::Inst_SOPP__S_BARRIER
Definition: instructions.hh:4723
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I64
Definition: instructions.hh:16207
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFE_U32
GPUStaticInst * decode_OP_SOP2__S_BFE_U32(MachInst)
Definition: decoder.cc:4397
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_OR_SRC2_B64(MachInst)
Definition: decoder.cc:8108
gem5::VegaISA::Decoder::decode_invalid
GPUStaticInst * decode_invalid(MachInst)
Definition: decoder.cc:13011
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_EQ_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_EQ_I32(MachInst)
Definition: decoder.cc:4513
gem5::VegaISA::InFmt_VOP3P
Definition: gpu_decoder.hh:1883
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BREV_B64
GPUStaticInst * decode_OP_SOP1__S_BREV_B64(MachInst)
Definition: decoder.cc:10596
gem5::VegaISA::Inst_SOP1__S_FF0_I32_B32
Definition: instructions.hh:2629
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C(MachInst)
Definition: decoder.cc:9134
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U32(MachInst)
Definition: decoder.cc:12617
gem5::VegaISA::Inst_VOP1__V_CVT_F32_I32
Definition: instructions.hh:8189
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SAD_U16
GPUStaticInst * decode_OPU_VOP3__V_SAD_U16(MachInst)
Definition: decoder.cc:6710
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F16(MachInst)
Definition: decoder.cc:11717
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LT_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LT_I32(MachInst)
Definition: decoder.cc:10895
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F32(MachInst)
Definition: decoder.cc:12005
gem5::VegaISA::Inst_VOP3__V_MSAD_U8
Definition: instructions.hh:29277
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U16(MachInst)
Definition: decoder.cc:12341
gem5::VegaISA::Inst_SOPP__S_ENDPGM_SAVED
Definition: instructions.hh:5233
gem5::VegaISA::Decoder::subDecode_OP_MTBUF
GPUStaticInst * subDecode_OP_MTBUF(MachInst)
Definition: decoder.cc:3829
gem5::VegaISA::Inst_VOP1__V_NOT_B32
Definition: instructions.hh:9405
gem5::VegaISA::Decoder::decode_OP_DS__DS_SWIZZLE_B32
GPUStaticInst * decode_OP_DS__DS_SWIZZLE_B32(MachInst)
Definition: decoder.cc:7553
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B32
GPUStaticInst * decode_OP_DS__DS_WRITE_B32(MachInst)
Definition: decoder.cc:7306
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_X2
Definition: instructions.hh:42730
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F32
Definition: instructions.hh:18995
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_UMAX
Definition: instructions.hh:39067
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB_X2
Definition: instructions.hh:42769
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F16(MachInst)
Definition: decoder.cc:11699
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_LZ_O
Definition: instructions.hh:41035
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RCP_F32
GPUStaticInst * decode_OP_VOP1__V_RCP_F32(MachInst)
Definition: decoder.cc:11394
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_LO_U32
GPUStaticInst * decode_OPU_VOP3__V_MUL_LO_U32(MachInst)
Definition: decoder.cc:7065
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I16(MachInst)
Definition: decoder.cc:12389
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SIN_F16
GPUStaticInst * decode_OPU_VOP3__V_SIN_F16(MachInst)
Definition: decoder.cc:6524
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_MAD_MIXLO_F16
GPUStaticInst * decode_OP_VOP3P__V_MAD_MIXLO_F16(MachInst)
Definition: decoder.cc:12997
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I16(MachInst)
Definition: decoder.cc:12299
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_LZ
Definition: instructions.hh:40603
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F64
Definition: instructions.hh:13419
gem5::VegaISA::Inst_VOP3__V_CMP_F_U16
Definition: instructions.hh:20967
gem5::VegaISA::Inst_VOP3__V_CVT_F32_I32
Definition: instructions.hh:25771
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:9763
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_F32(MachInst)
Definition: decoder.cc:7969
gem5::VegaISA::Inst_SOP1__S_MOV_B32
Definition: instructions.hh:2181
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_UMIN
Definition: instructions.hh:38999
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORD
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORD(MachInst)
Definition: decoder.cc:10049
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U32
Definition: instructions.hh:15799
gem5::VegaISA::Inst_SOP1__S_AND_SAVEEXEC_B64
Definition: instructions.hh:3203
gem5::VegaISA::Inst_DS__DS_ADD_SRC2_U64
Definition: instructions.hh:35065
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAC_F16
GPUStaticInst * decode_OP_VOP2__V_MAC_F16(MachInst)
Definition: decoder.cc:4055
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MUL_HI_I32
GPUStaticInst * decode_OP_SOP2__S_MUL_HI_I32(MachInst)
Definition: decoder.cc:4446
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I16
Definition: instructions.hh:14065
gem5::VegaISA::Inst_VOP1__V_TRUNC_F32
Definition: instructions.hh:8925
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F32(MachInst)
Definition: decoder.cc:5036
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O(MachInst)
Definition: decoder.cc:9085
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SENDMSG
GPUStaticInst * decode_OP_SOPP__S_SENDMSG(MachInst)
Definition: decoder.cc:11087
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORD
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORD(MachInst)
Definition: decoder.cc:9980
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O(MachInst)
Definition: decoder.cc:9031
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_ADD
Definition: instructions.hh:38897
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRAP_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRAP_RTN_B32(MachInst)
Definition: decoder.cc:7499
gem5::VegaISA::Inst_SOPC__S_SET_GPR_IDX_ON
Definition: instructions.hh:4323
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:9370
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_U64_U32
GPUStaticInst * decode_OPU_VOP3__V_MAD_U64_U32(MachInst)
Definition: decoder.cc:6788
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:9941
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I64
Definition: instructions.hh:16683
gem5::VegaISA::Decoder::tableSubDecode_OP_MUBUF
static IsaDecodeMethod tableSubDecode_OP_MUBUF[128]
Definition: gpu_decoder.hh:68
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_LZ_O(MachInst)
Definition: decoder.cc:9037
gem5::VegaISA::Inst_VOP3__V_CVT_PKRTZ_F16_F32
Definition: instructions.hh:30877
gem5::VegaISA::Inst_VOP2__V_MIN_U16
Definition: instructions.hh:7829
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U16(MachInst)
Definition: decoder.cc:5432
gem5::VegaISA::Decoder::decode_OP_VOP1__V_BFREV_B32
GPUStaticInst * decode_OP_VOP1__V_BFREV_B32(MachInst)
Definition: decoder.cc:11454
gem5::VegaISA::Inst_VOP3__V_MAX3_U32
Definition: instructions.hh:28731
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F16
Definition: instructions.hh:10801
gem5::VegaISA::Decoder::decode_OP_SOP2__S_CSELECT_B32
GPUStaticInst * decode_OP_SOP2__S_CSELECT_B32(MachInst)
Definition: decoder.cc:4235
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE1
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE1(MachInst)
Definition: decoder.cc:6212
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I32
Definition: instructions.hh:14983
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_F32
GPUStaticInst * decode_OPU_VOP3__V_MIN_F32(MachInst)
Definition: decoder.cc:5882
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F64
Definition: instructions.hh:13283
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE(MachInst)
Definition: decoder.cc:8464
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_ADD
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_ADD(MachInst)
Definition: decoder.cc:8314
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I16
Definition: instructions.hh:13963
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_L_O(MachInst)
Definition: decoder.cc:9067
gem5::VegaISA::Inst_DS__DS_OR_B64
Definition: instructions.hh:33161
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_I32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_I32_F64(MachInst)
Definition: decoder.cc:11214
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_OR
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_OR(MachInst)
Definition: decoder.cc:8875
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_WRITE_SRC2_B32(MachInst)
Definition: decoder.cc:7963
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F16(MachInst)
Definition: decoder.cc:11807
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_MIP_PCK
Definition: instructions.hh:38579
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8(MachInst)
Definition: decoder.cc:9998
gem5::VegaISA::Inst_VOP3__V_ADD_F32
Definition: instructions.hh:23995
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX3
Definition: instructions.hh:41871
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC_X2
Definition: instructions.hh:43065
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_U32(MachInst)
Definition: decoder.cc:7891
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F16(MachInst)
Definition: decoder.cc:11783
gem5::VegaISA::Decoder::decode_OP_VOP1__V_EXP_F16
GPUStaticInst * decode_OP_VOP1__V_EXP_F16(MachInst)
Definition: decoder.cc:11569
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F64(MachInst)
Definition: decoder.cc:12113
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F64(MachInst)
Definition: decoder.cc:5066
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ASHR_I64
GPUStaticInst * decode_OP_SOP2__S_ASHR_I64(MachInst)
Definition: decoder.cc:4373
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SWAP
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:9619
gem5::VegaISA::Decoder::subDecode_OP_FLAT
GPUStaticInst * subDecode_OP_FLAT(MachInst)
Definition: decoder.cc:3800
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_I32_F32(MachInst)
Definition: decoder.cc:11244
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F32
Definition: instructions.hh:11719
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CEIL_F32
GPUStaticInst * decode_OP_VOP1__V_CEIL_F32(MachInst)
Definition: decoder.cc:11364
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:9769
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_DWORDX3
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_DWORDX3(MachInst)
Definition: decoder.cc:8545
gem5::VegaISA::Inst_VOP3__V_MAD_F32
Definition: instructions.hh:28011
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F16
Definition: instructions.hh:10699
gem5::VegaISA::Decoder::decode_OP_VOP1__V_NOT_B32
GPUStaticInst * decode_OP_VOP1__V_NOT_B32(MachInst)
Definition: decoder.cc:11448
gem5::VegaISA::Inst_SOPC__S_CMP_LG_U64
Definition: instructions.hh:4387
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ORN2_B64
GPUStaticInst * decode_OP_SOP2__S_ORN2_B64(MachInst)
Definition: decoder.cc:4301
gem5::VegaISA::Inst_VOP3__V_DIV_FMAS_F32
Definition: instructions.hh:29203
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F32
Definition: instructions.hh:12365
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B32
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B32(MachInst)
Definition: decoder.cc:5930
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4H
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4H(MachInst)
Definition: decoder.cc:9103
gem5::VegaISA::Inst_VOP3__V_MAD_LEGACY_F32
Definition: instructions.hh:27975
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_CL(MachInst)
Definition: decoder.cc:9140
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL1_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_LSHL1_ADD_U32(MachInst)
Definition: decoder.cc:4452
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F32(MachInst)
Definition: decoder.cc:5000
gem5::VegaISA::InstFormat::iFmt_DS
InFmt_DS iFmt_DS
Definition: gpu_decoder.hh:1902
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_RTN_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_RTN_U32(MachInst)
Definition: decoder.cc:7391
gem5::VegaISA::Inst_VOP2__V_ADD_U16
Definition: instructions.hh:7455
gem5::VegaISA::Inst_VOP2__V_MUL_HI_U32_U24
Definition: instructions.hh:6447
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B16
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B16(MachInst)
Definition: decoder.cc:6056
gem5::VegaISA::Decoder::decode_OP_SOP2__S_NAND_B64
GPUStaticInst * decode_OP_SOP2__S_NAND_B64(MachInst)
Definition: decoder.cc:4313
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I32(MachInst)
Definition: decoder.cc:12485
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I32
Definition: instructions.hh:15629
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_U32
GPUStaticInst * decode_OP_VOP2__V_SUB_U32(MachInst)
Definition: decoder.cc:4163
gem5::VegaISA::Inst_DS__DS_OR_SRC2_B64
Definition: instructions.hh:35365
gem5::VegaISA::Inst_VOP3__V_DIV_FMAS_F64
Definition: instructions.hh:29241
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:9388
gem5::VegaISA::Inst_VOP3__V_SAD_U32
Definition: instructions.hh:28983
gem5::VegaISA::Inst_VOP3__V_MAX3_I32
Definition: instructions.hh:28695
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U32
Definition: instructions.hh:15765
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_HI_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_HI_X(MachInst)
Definition: decoder.cc:10103
gem5::VegaISA::Decoder::subDecode_OP_MUBUF
GPUStaticInst * subDecode_OP_MUBUF(MachInst)
Definition: decoder.cc:3821
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F32(MachInst)
Definition: decoder.cc:5018
gem5::VegaISA::Inst_VOP3__V_SAD_HI_U8
Definition: instructions.hh:28911
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F16
Definition: instructions.hh:17873
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_D_O
Definition: instructions.hh:40207
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_U16
GPUStaticInst * decode_OPU_VOP3__V_ADD_U16(MachInst)
Definition: decoder.cc:6026
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_LO_U16
GPUStaticInst * decode_OPU_VOP3__V_MUL_LO_U16(MachInst)
Definition: decoder.cc:6044
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I32(MachInst)
Definition: decoder.cc:12605
gem5::VegaISA::Inst_VOP2__V_ADDC_CO_U32
Definition: instructions.hh:7099
gem5::VegaISA::Inst_VOP3__V_MAX3_F32
Definition: instructions.hh:28659
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F16
Definition: instructions.hh:11073
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FLBIT_I32
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32(MachInst)
Definition: decoder.cc:10662
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_XOR_SRC2_B32(MachInst)
Definition: decoder.cc:7957
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U16
GPUStaticInst * decode_OP_DS__DS_READ_U16(MachInst)
Definition: decoder.cc:7547
gem5::VegaISA::Inst_VOP3__V_COS_F32
Definition: instructions.hh:26955
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_B_CL
Definition: instructions.hh:39487
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F64(MachInst)
Definition: decoder.cc:5234
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F16
Definition: instructions.hh:11345
gem5::VegaISA::Inst_VOP3__V_ADDC_CO_U32
Definition: instructions.hh:24887
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F16(MachInst)
Definition: decoder.cc:11765
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_USHORT
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_USHORT(MachInst)
Definition: decoder.cc:9789
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SCREEN_PARTITION_4SE_B32
GPUStaticInst * decode_OP_VOP1__V_SCREEN_PARTITION_4SE_B32(MachInst)
Definition: decoder.cc:11514
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X(MachInst)
Definition: decoder.cc:9310
gem5::VegaISA::Decoder::decode_OP_SOPP__S_TTRACEDATA
GPUStaticInst * decode_OP_SOPP__S_TTRACEDATA(MachInst)
Definition: decoder.cc:11123
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_INC
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_INC(MachInst)
Definition: decoder.cc:9685
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LOG_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_LOG_LEGACY_F32(MachInst)
Definition: decoder.cc:6542
gem5::VegaISA::Inst_DS__DS_RSUB_U64
Definition: instructions.hh:32905
gem5::VegaISA::InFmt_VOP3A::OP
unsigned int OP
Definition: gpu_decoder.hh:1805
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_RPI_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_RPI_I32_F32(MachInst)
Definition: decoder.cc:11262
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F32(MachInst)
Definition: decoder.cc:12065
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I16
Definition: instructions.hh:14609
gem5::VegaISA::Inst_VOP3__V_SUB_F16
Definition: instructions.hh:25035
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:8605
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I64
Definition: instructions.hh:23041
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_D_O
Definition: instructions.hh:39919
gem5::VegaISA::Decoder::decode_OP_SOPC__S_BITCMP1_B32
GPUStaticInst * decode_OP_SOPC__S_BITCMP1_B32(MachInst)
Definition: decoder.cc:10949
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F16
Definition: instructions.hh:18247
gem5::VegaISA::Inst_VOP3__V_WRITELANE_B32
Definition: instructions.hh:30503
gem5::VegaISA::Inst_VOP2__V_MAX_U16
Definition: instructions.hh:7761
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F64(MachInst)
Definition: decoder.cc:5138
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F64(MachInst)
Definition: decoder.cc:5210
gem5::VegaISA::Inst_VOP3__V_CMP_F_F64
Definition: instructions.hh:19607
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL4_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_LSHL4_ADD_U32(MachInst)
Definition: decoder.cc:4473
gem5::VegaISA::Inst_VOPC__V_CMP_O_F64
Definition: instructions.hh:13011
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_AND
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_AND(MachInst)
Definition: decoder.cc:8350
gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE3
Definition: instructions.hh:8669
gem5::VegaISA::Decoder::decode_OP_VOP1__V_READFIRSTLANE_B32
GPUStaticInst * decode_OP_VOP1__V_READFIRSTLANE_B32(MachInst)
Definition: decoder.cc:11208
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_TRUNC_F64
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F64(MachInst)
Definition: decoder.cc:6242
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F64
Definition: instructions.hh:13691
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_CL_O(MachInst)
Definition: decoder.cc:9190
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I16(MachInst)
Definition: decoder.cc:5378
gem5::VegaISA::InFmt_MTBUF::OP
unsigned int OP
Definition: gpu_decoder.hh:1685
gpu_decoder.hh
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_OR
Definition: instructions.hh:39135
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I32_F64
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I32_F64(MachInst)
Definition: decoder.cc:11478
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F16
Definition: instructions.hh:11413
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
Definition: instructions.hh:36061
gem5::VegaISA::Inst_VOP3__V_CMP_F_I64
Definition: instructions.hh:22871
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_F16
GPUStaticInst * decode_OP_VOP2__V_MIN_F16(MachInst)
Definition: decoder.cc:4121
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE_D16_HI(MachInst)
Definition: decoder.cc:8578
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F32(MachInst)
Definition: decoder.cc:11987
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_I16_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_I16_F16(MachInst)
Definition: decoder.cc:6446
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F16(MachInst)
Definition: decoder.cc:4820
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_DEC
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_DEC(MachInst)
Definition: decoder.cc:10444
gem5::VegaISA::Decoder::decode_OP_SOP1__S_QUADMASK_B64
GPUStaticInst * decode_OP_SOP1__S_QUADMASK_B64(MachInst)
Definition: decoder.cc:10788
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U64
Definition: instructions.hh:16921
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_ADD_X2
Definition: instructions.hh:37431
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U64(MachInst)
Definition: decoder.cc:5804
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_OR
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_OR(MachInst)
Definition: decoder.cc:10241
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RNDNE_F64
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F64(MachInst)
Definition: decoder.cc:11340
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F64
Definition: instructions.hh:13181
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE3
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE3(MachInst)
Definition: decoder.cc:11310
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FFBL_B32
GPUStaticInst * decode_OP_VOP1__V_FFBL_B32(MachInst)
Definition: decoder.cc:11466
gem5::VegaISA::Inst_DS__DS_RSUB_RTN_U64
Definition: instructions.hh:33555
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F32(MachInst)
Definition: decoder.cc:4934
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I16
Definition: instructions.hh:20899
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F16(MachInst)
Definition: decoder.cc:4778
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:8677
gem5::VegaISA::Decoder::tableSubDecode_OP_MTBUF
static IsaDecodeMethod tableSubDecode_OP_MTBUF[16]
Definition: gpu_decoder.hh:67
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_I32
GPUStaticInst * decode_OP_VOP2__V_MIN_I32(MachInst)
Definition: decoder.cc:3917
gem5::VegaISA::Inst_VOPC__V_CMP_F_U16
Definition: instructions.hh:14133
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_GE_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_GE_I32(MachInst)
Definition: decoder.cc:10889
gem5::VegaISA::Inst_VOP3__V_CMP_U_F32
Definition: instructions.hh:18791
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U32
Definition: instructions.hh:22599
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F16
Definition: instructions.hh:17635
gem5::VegaISA::Inst_SOPK__S_CMPK_GE_I32
Definition: instructions.hh:1701
gem5::VegaISA::Inst_SOP1__S_CBRANCH_JOIN
Definition: instructions.hh:3651
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SET_GPR_IDX_OFF
GPUStaticInst * decode_OP_SOPP__S_SET_GPR_IDX_OFF(MachInst)
Definition: decoder.cc:11159
gem5::VegaISA::Inst_VOP3__V_SUBREV_U16
Definition: instructions.hh:25239
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F16(MachInst)
Definition: decoder.cc:11813
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_INC_SRC2_U32(MachInst)
Definition: decoder.cc:7909
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F64(MachInst)
Definition: decoder.cc:5162
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F32
Definition: instructions.hh:18961
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I32
Definition: instructions.hh:21817
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_AND
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_AND(MachInst)
Definition: decoder.cc:9667
gem5::VegaISA::Inst_VOP3__V_EXP_F32
Definition: instructions.hh:26635
gem5::VegaISA::Inst_VOP1__V_CVT_F16_U16
Definition: instructions.hh:9753
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORD
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORD(MachInst)
Definition: decoder.cc:8186
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I16
Definition: instructions.hh:20797
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAC_F32
GPUStaticInst * decode_OPU_VOP3__V_MAC_F32(MachInst)
Definition: decoder.cc:5954
gem5::VegaISA::Inst_DS__DS_OR_B32
Definition: instructions.hh:31299
gem5::VegaISA::Inst_VOP3__V_FREXP_MANT_F16
Definition: instructions.hh:27623
gem5::VegaISA::Inst_SOPP__S_CBRANCH_EXECNZ
Definition: instructions.hh:4693
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F32
Definition: instructions.hh:18553
gem5::VegaISA::Decoder::decode_OP_VOP1__V_COS_F16
GPUStaticInst * decode_OP_VOP1__V_COS_F16(MachInst)
Definition: decoder.cc:11623
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I16(MachInst)
Definition: decoder.cc:5366
gem5::VegaISA::Inst_DS__DS_SUB_SRC2_U32
Definition: instructions.hh:34333
gem5::VegaISA::Inst_SOP1__S_CMOV_B32
Definition: instructions.hh:2245
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U64
Definition: instructions.hh:23313
gem5::VegaISA::Inst_DS__DS_XOR_SRC2_B64
Definition: instructions.hh:35395
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F16
Definition: instructions.hh:17533
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U16
Definition: instructions.hh:14847
gem5::VegaISA::Inst_VOP3__V_MUL_F16
Definition: instructions.hh:25103
gem5::VegaISA::Decoder::decode_OP_SOPK__S_ADDK_I32
GPUStaticInst * decode_OP_SOPK__S_ADDK_I32(MachInst)
Definition: decoder.cc:4585
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_ADD
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_ADD(MachInst)
Definition: decoder.cc:8833
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F32
Definition: instructions.hh:12433
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_X(MachInst)
Definition: decoder.cc:9431
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O(MachInst)
Definition: decoder.cc:9079
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX16
Definition: instructions.hh:5467
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X
Definition: instructions.hh:35947
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F64(MachInst)
Definition: decoder.cc:12257
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BCNT1_I32_B64
GPUStaticInst * decode_OP_SOP1__S_BCNT1_I32_B64(MachInst)
Definition: decoder.cc:10620
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_BYTE_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_BYTE_D16_HI(MachInst)
Definition: decoder.cc:8512
gem5::VegaISA::Inst_VOP3__V_MAD_U32_U24
Definition: instructions.hh:28083
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_SEMA_BR
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_BR(MachInst)
Definition: decoder.cc:8005
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F32
Definition: instructions.hh:19573
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_L_O(MachInst)
Definition: decoder.cc:9232
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I32
Definition: instructions.hh:15017
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MUL_I32_I24(MachInst)
Definition: decoder.cc:5858
gem5::VegaISA::Inst_SOP1__S_SET_GPR_IDX_IDX
Definition: instructions.hh:3747
gem5::VegaISA::Inst_VOP3__V_INTERP_P1LV_F16
Definition: instructions.hh:30091
gem5::VegaISA::Inst_VOP3__V_CVT_F16_U16
Definition: instructions.hh:27335
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_DWORDX4
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_DWORDX4(MachInst)
Definition: decoder.cc:9880
gem5::VegaISA::Inst_VOP3__V_AND_B32
Definition: instructions.hh:24607
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_HI_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_HI_X(MachInst)
Definition: decoder.cc:10109
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_U32
GPUStaticInst * decode_OP_VOP2__V_SUBREV_U32(MachInst)
Definition: decoder.cc:4169
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I32
Definition: instructions.hh:15697
gem5::VegaISA::Inst_VOP1__V_CVT_F32_F64
Definition: instructions.hh:8509
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F32(MachInst)
Definition: decoder.cc:4928
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_F64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_F64(MachInst)
Definition: decoder.cc:7855
gem5::VegaISA::Inst_VOP3__V_MOV_B32
Definition: instructions.hh:25675
gem5::VegaISA::Inst_VOP3__V_CMP_U_F64
Definition: instructions.hh:19879
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I16(MachInst)
Definition: decoder.cc:5282
gem5::VegaISA::Inst_VOP2__V_MIN_I32
Definition: instructions.hh:6549
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U64
Definition: instructions.hh:23823
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F64
Definition: instructions.hh:20525
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F16(MachInst)
Definition: decoder.cc:4814
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F32(MachInst)
Definition: decoder.cc:12077
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F32
Definition: instructions.hh:11753
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I32(MachInst)
Definition: decoder.cc:5552
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F16(MachInst)
Definition: decoder.cc:11801
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LG_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_I32(MachInst)
Definition: decoder.cc:10877
gem5::VegaISA::Inst_VOP3__V_CUBEMA_F32
Definition: instructions.hh:28227
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_LEGACY_F16
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_LEGACY_F16(MachInst)
Definition: decoder.cc:6830
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_LZ(MachInst)
Definition: decoder.cc:8989
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MIN_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_MIN_U16(MachInst)
Definition: decoder.cc:12948
gem5::VegaISA::Decoder::subDecode_OP_VINTRP
GPUStaticInst * subDecode_OP_VINTRP(MachInst)
Definition: decoder.cc:3784
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I32
Definition: instructions.hh:22565
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F16(MachInst)
Definition: decoder.cc:11873
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U16
Definition: instructions.hh:21171
gem5::VegaISA::Inst_VOP3__V_CVT_F32_F64
Definition: instructions.hh:26091
gem5::VegaISA::Inst_VOP2__V_MIN_F32
Definition: instructions.hh:6481
gem5::VegaISA::Inst_VOPC__V_CMP_O_F32
Definition: instructions.hh:11923
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR
Definition: instructions.hh:42506
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBBREV_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBBREV_CO_U32(MachInst)
Definition: decoder.cc:5990
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_F16
GPUStaticInst * decode_OPU_VOP3__V_MAX3_F16(MachInst)
Definition: decoder.cc:6884
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F16(MachInst)
Definition: decoder.cc:4754
gem5::VegaISA::Inst_SOP1__S_BCNT1_I32_B32
Definition: instructions.hh:2565
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_F16
GPUStaticInst * decode_OPU_VOP3__V_MAD_F16(MachInst)
Definition: decoder.cc:6962
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F32(MachInst)
Definition: decoder.cc:11963
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_B_CL_O
Definition: instructions.hh:40999
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN_X2
Definition: instructions.hh:42806
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ2_B64
GPUStaticInst * decode_OP_DS__DS_READ2_B64(MachInst)
Definition: decoder.cc:7873
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O(MachInst)
Definition: decoder.cc:9304
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_U64
Definition: instructions.hh:35305
instructions.hh
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBB_CO_U32
GPUStaticInst * decode_OP_VOP2__V_SUBB_CO_U32(MachInst)
Definition: decoder.cc:4019
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMAX
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:8344
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U16
Definition: instructions.hh:21579
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F32(MachInst)
Definition: decoder.cc:4946
gem5::VegaISA::Inst_VOP3__V_TRIG_PREOP_F64
Definition: instructions.hh:30741
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U32
Definition: instructions.hh:22089
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F32
Definition: instructions.hh:17227
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F64(MachInst)
Definition: decoder.cc:11687
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORD
Definition: instructions.hh:36411
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F16(MachInst)
Definition: decoder.cc:11795
gem5::VegaISA::Decoder::decode_OP_SOPC__S_SET_GPR_IDX_ON
GPUStaticInst * decode_OP_SOPC__S_SET_GPR_IDX_ON(MachInst)
Definition: decoder.cc:10973
gem5::VegaISA::Inst_SOPC__S_CMP_LE_I32
Definition: instructions.hh:3939
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I32
Definition: instructions.hh:15731
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_U_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F32(MachInst)
Definition: decoder.cc:11945
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U16
Definition: instructions.hh:21069
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CL_O
Definition: instructions.hh:40171
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_ADD
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_ADD(MachInst)
Definition: decoder.cc:10374
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITREPLICATE_B64_B32
GPUStaticInst * decode_OP_SOP1__S_BITREPLICATE_B64_B32(MachInst)
Definition: decoder.cc:10864
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U64(MachInst)
Definition: decoder.cc:12749
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_RTN_U64
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_U64(MachInst)
Definition: decoder.cc:7747
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_X
Definition: instructions.hh:35643
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RSQ_F16
GPUStaticInst * decode_OP_VOP1__V_RSQ_F16(MachInst)
Definition: decoder.cc:11557
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_GT_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_GT_I32(MachInst)
Definition: decoder.cc:10883
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_O_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F64(MachInst)
Definition: decoder.cc:5096
gem5::VegaISA::Inst_VOP3__V_LSHRREV_B32
Definition: instructions.hh:24505
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_LZ_O
Definition: instructions.hh:41251
gem5::VegaISA::Decoder::decode_OP_SOP2__S_HH_B32_B16
GPUStaticInst * decode_OP_SOP2__S_HH_B32_B16(MachInst)
Definition: decoder.cc:4494
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MBCNT_LO_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_MBCNT_LO_U32_B32(MachInst)
Definition: decoder.cc:7107
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_F16
GPUStaticInst * decode_OP_VOP2__V_ADD_F16(MachInst)
Definition: decoder.cc:4031
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LG_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LG_I32(MachInst)
Definition: decoder.cc:4519
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F64
Definition: instructions.hh:19981
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_DEC_SRC2_U32(MachInst)
Definition: decoder.cc:7915
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_U_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F16(MachInst)
Definition: decoder.cc:4718
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F64(MachInst)
Definition: decoder.cc:12089
gem5::VegaISA::Inst_FLAT__FLAT_STORE_SHORT
Definition: instructions.hh:41982
gem5::VegaISA::Inst_VOP3__V_MUL_HI_I32_I24
Definition: instructions.hh:24199
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE0
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE0(MachInst)
Definition: decoder.cc:11292
gem5::VegaISA::Inst_VOP3__V_XOR_B32
Definition: instructions.hh:24711
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_PCK_SGN
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_PCK_SGN(MachInst)
Definition: decoder.cc:8773
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I16
Definition: instructions.hh:21239
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F64
Definition: instructions.hh:20287
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_RTN_U64
GPUStaticInst * decode_OP_DS__DS_DEC_RTN_U64(MachInst)
Definition: decoder.cc:7771
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CL_O
Definition: instructions.hh:39883
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_INC_X2
Definition: instructions.hh:37755
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F64(MachInst)
Definition: decoder.cc:12149
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F16
Definition: instructions.hh:10767
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SETKILL
GPUStaticInst * decode_OP_SOPP__S_SETKILL(MachInst)
Definition: decoder.cc:11057
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_NOT_B32
GPUStaticInst * decode_OPU_VOP3__V_NOT_B32(MachInst)
Definition: decoder.cc:6362
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F16(MachInst)
Definition: decoder.cc:4796
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F64
Definition: instructions.hh:13079
gem5::VegaISA::Inst_DS__DS_ADD_F32
Definition: instructions.hh:31659
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I64
Definition: instructions.hh:23551
gem5::VegaISA::Inst_VOP3__V_LSHLREV_B32
Definition: instructions.hh:24573
gem5::VegaISA::Inst_SOP1__S_WQM_B64
Definition: instructions.hh:2405
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F64
Definition: instructions.hh:20423
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U64(MachInst)
Definition: decoder.cc:12725
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB
Definition: instructions.hh:42284
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX2
Definition: instructions.hh:36449
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_U32
GPUStaticInst * decode_OPU_VOP3__V_MED3_U32(MachInst)
Definition: decoder.cc:6692
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_OR_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:8434
gem5::VegaISA::Inst_SOPC__S_BITCMP1_B32
Definition: instructions.hh:4195
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F16
Definition: instructions.hh:17975
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SBYTE_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SBYTE_D16_HI(MachInst)
Definition: decoder.cc:8281
gem5::VegaISA::Inst_VOP3__V_CMP_F_F16
Definition: instructions.hh:17431
gem5::VegaISA::InstFormat::iFmt_SOPC
InFmt_SOPC iFmt_SOPC
Definition: gpu_decoder.hh:1919
gem5::VegaISA::Inst_SOPC__S_CMP_LE_U32
Definition: instructions.hh:4131
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFM_B32
GPUStaticInst * decode_OPU_VOP3__V_BFM_B32(MachInst)
Definition: decoder.cc:7143
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F32(MachInst)
Definition: decoder.cc:5030
gem5::VegaISA::Inst_DS__DS_INC_RTN_U32
Definition: instructions.hh:31861
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F32
Definition: instructions.hh:12603
gem5::VegaISA::Inst_SOPP__S_SETPRIO
Definition: instructions.hh:4873
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ADD_I32
GPUStaticInst * decode_OP_SOP2__S_ADD_I32(MachInst)
Definition: decoder.cc:4187
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I16
Definition: instructions.hh:14405
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_GE_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GE_I32(MachInst)
Definition: decoder.cc:4531
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CUBESC_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBESC_F32(MachInst)
Definition: decoder.cc:6578
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_U16_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_U16_F16(MachInst)
Definition: decoder.cc:6440
gem5::VegaISA::Inst_VOP2__V_SUBREV_U16
Definition: instructions.hh:7523
gem5::VegaISA::Inst_VOP3__V_MBCNT_HI_U32_B32
Definition: instructions.hh:30605
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U16(MachInst)
Definition: decoder.cc:5306
gem5::VegaISA::Inst_VOP2__V_MIN_I16
Definition: instructions.hh:7863
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_AND_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:8725
gem5::VegaISA::Inst_VOP3__V_BCNT_U32_B32
Definition: instructions.hh:30537
gem5::VegaISA::Decoder::decode_OP_SOPP__S_NOP
GPUStaticInst * decode_OP_SOPP__S_NOP(MachInst)
Definition: decoder.cc:10991
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F64
Definition: instructions.hh:13589
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F16
Definition: instructions.hh:18043
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I64(MachInst)
Definition: decoder.cc:12677
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F32
Definition: instructions.hh:19233
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_I16
GPUStaticInst * decode_OPU_VOP3__V_SUB_I16(MachInst)
Definition: decoder.cc:7214
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F64(MachInst)
Definition: decoder.cc:5120
gem5::VegaISA::Decoder::tableSubDecode_OP_VOPC
static IsaDecodeMethod tableSubDecode_OP_VOPC[256]
Definition: gpu_decoder.hh:76
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F16
Definition: instructions.hh:11141
gem5::VegaISA::Inst_VOP3__V_CMP_F_I16
Definition: instructions.hh:20695
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2
Definition: instructions.hh:37503
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE3
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE3(MachInst)
Definition: decoder.cc:6224
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I16(MachInst)
Definition: decoder.cc:12395
gem5::VegaISA::Decoder::decode_OP_SOP2__S_SUB_I32
GPUStaticInst * decode_OP_SOP2__S_SUB_I32(MachInst)
Definition: decoder.cc:4193
gem5::VegaISA::Inst_VOP1__V_FLOOR_F64
Definition: instructions.hh:8861
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_DWORD
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_DWORD(MachInst)
Definition: decoder.cc:9859
gem5::VegaISA::Inst_DS__DS_CMPST_RTN_F32
Definition: instructions.hh:32337
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW(MachInst)
Definition: decoder.cc:9449
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MUL_U32_U24(MachInst)
Definition: decoder.cc:5870
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW(MachInst)
Definition: decoder.cc:9425
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I16
Definition: instructions.hh:21307
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I16(MachInst)
Definition: decoder.cc:12281
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_U16
GPUStaticInst * decode_OPU_VOP3__V_MIN3_U16(MachInst)
Definition: decoder.cc:6877
gem5::VegaISA::Inst_VOP3__V_FRACT_F64
Definition: instructions.hh:27211
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I16(MachInst)
Definition: decoder.cc:5342
gem5::VegaISA::Inst_VOP3__V_ASHRREV_I16
Definition: instructions.hh:25375
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U16(MachInst)
Definition: decoder.cc:12467
gem5::VegaISA::Inst_VOP2__V_MIN_F16
Definition: instructions.hh:7727
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O(MachInst)
Definition: decoder.cc:9292
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_B
Definition: instructions.hh:40531
gem5::VegaISA::Inst_SOP1__S_ABS_I32
Definition: instructions.hh:3683
gem5::VegaISA::Inst_VOP2__V_LSHRREV_B32
Definition: instructions.hh:6685
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F16(MachInst)
Definition: decoder.cc:4736
gem5::VegaISA::Inst_DS__DS_CMPST_RTN_B32
Definition: instructions.hh:32303
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F64(MachInst)
Definition: decoder.cc:12269
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U16(MachInst)
Definition: decoder.cc:12455
gem5::VegaISA::Inst_DS__DS_READ_B32
Definition: instructions.hh:32507
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ
Definition: instructions.hh:35719
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG_RTN_B64(MachInst)
Definition: decoder.cc:7825
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LG_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F32(MachInst)
Definition: decoder.cc:11927
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_OR_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:8731
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F32
Definition: instructions.hh:12739
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_HI_U32_U24
GPUStaticInst * decode_OP_VOP2__V_MUL_HI_U32_U24(MachInst)
Definition: decoder.cc:3899
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U64(MachInst)
Definition: decoder.cc:5798
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U32
Definition: instructions.hh:22667
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I32
Definition: instructions.hh:21851
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F16_I16
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_I16(MachInst)
Definition: decoder.cc:11527
gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B32
Definition: instructions.hh:2501
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_F32
GPUStaticInst * decode_OP_VOP2__V_MIN_F32(MachInst)
Definition: decoder.cc:3905
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F16
Definition: instructions.hh:17363
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F64(MachInst)
Definition: decoder.cc:12101
gem5::VegaISA::Inst_VOP3__V_NOT_B32
Definition: instructions.hh:26987
gem5::VegaISA::Inst_SOP1__S_BCNT1_I32_B64
Definition: instructions.hh:2597
gem5::VegaISA::Inst_SOP1__S_FLBIT_I32
Definition: instructions.hh:2821
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I64(MachInst)
Definition: decoder.cc:5648
gem5::VegaISA::Decoder::decode_OP_SOP2__S_AND_B64
GPUStaticInst * decode_OP_SOP2__S_AND_B64(MachInst)
Definition: decoder.cc:4253
gem5::VegaISA::Inst_VOP3__V_SUBREV_F16
Definition: instructions.hh:25069
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SBYTE
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SBYTE(MachInst)
Definition: decoder.cc:8168
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD(MachInst)
Definition: decoder.cc:9262
gem5::VegaISA::Inst_DS__DS_ADD_U32
Definition: instructions.hh:30979
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MQSAD_PK_U16_U8
GPUStaticInst * decode_OPU_VOP3__V_MQSAD_PK_U16_U8(MachInst)
Definition: decoder.cc:6776
gem5::VegaISA::Inst_VOP3__V_FREXP_EXP_I32_F64
Definition: instructions.hh:27147
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_DEC
Definition: instructions.hh:37323
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_AND
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_AND(MachInst)
Definition: decoder.cc:8647
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F32
Definition: instructions.hh:18587
gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32
Definition: instructions.hh:6753
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MAD_I32_I24(MachInst)
Definition: decoder.cc:6560
gem5::VegaISA::Inst_SOP1__S_SETPC_B64
Definition: instructions.hh:3107
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMOVK_I32
GPUStaticInst * decode_OP_SOPK__S_CMOVK_I32(MachInst)
Definition: decoder.cc:4507
gem5::VegaISA::Decoder::decode_OP_VOP1__V_LOG_F32
GPUStaticInst * decode_OP_VOP1__V_LOG_F32(MachInst)
Definition: decoder.cc:11388
gem5::VegaISA::Inst_VOP2__V_ADD_F16
Definition: instructions.hh:7213
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F64
Definition: instructions.hh:13793
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:8386
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_EXP_F32
GPUStaticInst * decode_OPU_VOP3__V_EXP_F32(MachInst)
Definition: decoder.cc:6296
gem5::VegaISA::Inst_VOP1__V_EXP_F16
Definition: instructions.hh:10009
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_OR_SRC2_B32(MachInst)
Definition: decoder.cc:7951
gem5::VegaISA::Inst_VOP2__V_MADMK_F32
Definition: instructions.hh:6923
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP
Definition: instructions.hh:42206
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX_X2
Definition: instructions.hh:42880
gem5::VegaISA::Inst_SOPP__S_NOP
Definition: instructions.hh:4419
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_FLR_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_FLR_I32_F32(MachInst)
Definition: decoder.cc:6182
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U32(MachInst)
Definition: decoder.cc:12629
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE(MachInst)
Definition: decoder.cc:9775
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C(MachInst)
Definition: decoder.cc:8947
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_U64(MachInst)
Definition: decoder.cc:8048
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_O_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F16(MachInst)
Definition: decoder.cc:4712
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITSET0_B32
GPUStaticInst * decode_OP_SOP1__S_BITSET0_B32(MachInst)
Definition: decoder.cc:10686
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:9497
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_STORE_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_PCK(MachInst)
Definition: decoder.cc:8803
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_RTN_F32
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_F32(MachInst)
Definition: decoder.cc:7505
gem5::VegaISA::Inst_SMEM__S_DCACHE_WB_VOL
Definition: instructions.hh:5983
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADDC_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_ADDC_CO_U32(MachInst)
Definition: decoder.cc:5978
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F16
Definition: instructions.hh:18383
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I32(MachInst)
Definition: decoder.cc:12581
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX8
Definition: instructions.hh:5431
gem5::VegaISA::Inst_VOP2__V_LDEXP_F16
Definition: instructions.hh:7897
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I32(MachInst)
Definition: decoder.cc:12575
gem5::VegaISA::InstFormat::iFmt_SOP2
InFmt_SOP2 iFmt_SOP2
Definition: gpu_decoder.hh:1918
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U16(MachInst)
Definition: decoder.cc:12443
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I64(MachInst)
Definition: decoder.cc:5630
gem5::VegaISA::Inst_DS__DS_AND_RTN_B32
Definition: instructions.hh:32065
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F32
Definition: instructions.hh:19437
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_OR_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:10514
gem5::VegaISA::Decoder::decode_OP_SOP2__S_NOR_B32
GPUStaticInst * decode_OP_SOP2__S_NOR_B32(MachInst)
Definition: decoder.cc:4319
gem5::VegaISA::Decoder::tableSubDecode_OP_FLAT
static IsaDecodeMethod tableSubDecode_OP_FLAT[128]
Definition: gpu_decoder.hh:64
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_EQ_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_I32(MachInst)
Definition: decoder.cc:10871
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F64(MachInst)
Definition: decoder.cc:12179
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_D_CL
Definition: instructions.hh:39667
gem5::VegaISA::Decoder::Decoder
Decoder()
Definition: decoder.cc:43
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CEIL_F32
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F32(MachInst)
Definition: decoder.cc:6278
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I32(MachInst)
Definition: decoder.cc:5558
gem5::VegaISA::Inst_VOP1__V_FREXP_EXP_I32_F32
Definition: instructions.hh:9661
gem5::VegaISA::Inst_DS__DS_MIN_F64
Definition: instructions.hh:33423
gem5::VegaISA::Inst_VOP3__V_FMA_F16
Definition: instructions.hh:29849
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_B_CL_O
Definition: instructions.hh:41215
gem5::VegaISA::Inst_DS__DS_WRITE_SRC2_B64
Definition: instructions.hh:35425
gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE2
Definition: instructions.hh:26219
gem5::VegaISA::Decoder::tableSubDecode_OP_SOPP
static IsaDecodeMethod tableSubDecode_OP_SOPP[128]
Definition: gpu_decoder.hh:73
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_PERM_B32
GPUStaticInst * decode_OPU_VOP3__V_PERM_B32(MachInst)
Definition: decoder.cc:6818
gem5::VegaISA::Inst_VOP2__V_MAX_I16
Definition: instructions.hh:7795
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U64
Definition: instructions.hh:16479
gem5::VegaISA::Decoder::subDecode_OP_VOPC
GPUStaticInst * subDecode_OP_VOPC(MachInst)
Definition: decoder.cc:3720
gem5::VegaISA::Inst_SOPP__S_SETKILL
Definition: instructions.hh:4753
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_ADD_CO_U32(MachInst)
Definition: decoder.cc:5960
gem5::VegaISA::Inst_VINTRP__V_INTERP_P2_F32
Definition: instructions.hh:17159
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F32
Definition: instructions.hh:19131
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LDEXP_F16
GPUStaticInst * decode_OP_VOP2__V_LDEXP_F16(MachInst)
Definition: decoder.cc:4151
gem5::VegaISA::Inst_VOP3__V_CVT_RPI_I32_F32
Definition: instructions.hh:25995
gem5::VegaISA::Inst_DS__DS_MIN_I64
Definition: instructions.hh:33001
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_LZ_O
Definition: instructions.hh:40099
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U64(MachInst)
Definition: decoder.cc:12743
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_BYTE_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_BYTE_D16_HI(MachInst)
Definition: decoder.cc:9838
gem5::VegaISA::Inst_DS__DS_DEC_SRC2_U64
Definition: instructions.hh:35185
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CD_CL_O
Definition: instructions.hh:41503
gem5::VegaISA::Inst_EXP__EXP
Definition: instructions.hh:41611
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORD
Definition: instructions.hh:41797
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CD
Definition: instructions.hh:41395
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE(MachInst)
Definition: decoder.cc:8899
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORD
Definition: instructions.hh:5323
gem5::VegaISA::Inst_DS__DS_WRITE2_B32
Definition: instructions.hh:31429
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_EXP_F16
GPUStaticInst * decode_OPU_VOP3__V_EXP_F16(MachInst)
Definition: decoder.cc:6476
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I32
Definition: instructions.hh:22395
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MADAK_F16
GPUStaticInst * decode_OP_VOP2__V_MADAK_F16(MachInst)
Definition: decoder.cc:4067
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U32
Definition: instructions.hh:22123
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F32
Definition: instructions.hh:12263
gem5::VegaISA::Inst_VOP2__V_MAX_F16
Definition: instructions.hh:7693
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F16
Definition: instructions.hh:17601
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F32
Definition: instructions.hh:12059
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FMA_F16
GPUStaticInst * decode_OPU_VOP3__V_FMA_F16(MachInst)
Definition: decoder.cc:6980
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F64
Definition: instructions.hh:10461
gem5::VegaISA::Inst_VOP3__V_BFE_U32
Definition: instructions.hh:28263
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U16(MachInst)
Definition: decoder.cc:12347
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I64
Definition: instructions.hh:16071
gem5::VegaISA::Inst_SOP2__S_ANDN2_B64
Definition: instructions.hh:691
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORDX2(MachInst)
Definition: decoder.cc:10055
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U32(MachInst)
Definition: decoder.cc:5528
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX3
Definition: instructions.hh:36487
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F64(MachInst)
Definition: decoder.cc:5108
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U64(MachInst)
Definition: decoder.cc:12719
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_OR
Definition: instructions.hh:37215
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I16(MachInst)
Definition: decoder.cc:5354
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_L
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_L(MachInst)
Definition: decoder.cc:8971
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_CL_O(MachInst)
Definition: decoder.cc:9208
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F32
Definition: instructions.hh:10427
gem5::VegaISA::Decoder::tableSubDecode_OP_VOP1
static IsaDecodeMethod tableSubDecode_OP_VOP1[256]
Definition: gpu_decoder.hh:75
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:9376
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I32
Definition: instructions.hh:15527
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I64
Definition: instructions.hh:16105
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE2
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE2(MachInst)
Definition: decoder.cc:6218
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U16
Definition: instructions.hh:14337
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U16
Definition: instructions.hh:21545
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U64(MachInst)
Definition: decoder.cc:5702
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP
Definition: instructions.hh:42167
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOVRELS_B32
GPUStaticInst * decode_OP_SOP1__S_MOVRELS_B32(MachInst)
Definition: decoder.cc:10794
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F64
Definition: instructions.hh:12807
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ORN2_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ORN2_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10758
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F32(MachInst)
Definition: decoder.cc:4940
gem5::VegaISA::Inst_VOP3__V_SUBREV_F32
Definition: instructions.hh:24063
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F64
Definition: instructions.hh:20627
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_USHORT
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_USHORT(MachInst)
Definition: decoder.cc:8470
gem5::VegaISA::Inst_DS__DS_MIN_U64
Definition: instructions.hh:33065
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_RTN_U32
GPUStaticInst * decode_OP_DS__DS_INC_RTN_U32(MachInst)
Definition: decoder.cc:7397
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F64
Definition: instructions.hh:20083
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_MAD_MIX_F32
GPUStaticInst * decode_OP_VOP3P__V_MAD_MIX_F32(MachInst)
Definition: decoder.cc:12990
gem5::VegaISA::Inst_VOP2__V_MUL_HI_I32_I24
Definition: instructions.hh:6379
gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B64
Definition: instructions.hh:2533
gem5::VegaISA::Inst_VOP2__V_MAC_F32
Definition: instructions.hh:6889
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F64
Definition: instructions.hh:12841
gem5::VegaISA::Inst_MIMG__IMAGE_STORE_MIP_PCK
Definition: instructions.hh:38759
gem5::VegaISA::Inst_VOP1__V_FLOOR_F32
Definition: instructions.hh:9021
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U32
Definition: instructions.hh:15255
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN_X2
Definition: instructions.hh:42843
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F16
Definition: instructions.hh:10903
gem5::VegaISA::Decoder::decode_OP_VOP2__V_XOR_B32
GPUStaticInst * decode_OP_VOP2__V_XOR_B32(MachInst)
Definition: decoder.cc:3971
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:9757
gem5::VegaISA::Decoder::decode_OP_SOP1__S_XNOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_XNOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10776
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_AND
Definition: instructions.hh:37179
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F32(MachInst)
Definition: decoder.cc:4916
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_SCC1
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_SCC1(MachInst)
Definition: decoder.cc:11021
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD(MachInst)
Definition: decoder.cc:8611
gem5::VegaISA::Inst_VOPC__V_CMP_F_F16
Definition: instructions.hh:10597
gem5::VegaISA::Inst_VOP3__V_MIN_U32
Definition: instructions.hh:24437
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_F32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_F32(MachInst)
Definition: decoder.cc:6662
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U16
Definition: instructions.hh:14235
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B16
GPUStaticInst * decode_OP_DS__DS_WRITE_B16(MachInst)
Definition: decoder.cc:7373
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_COS_F32
GPUStaticInst * decode_OPU_VOP3__V_COS_F32(MachInst)
Definition: decoder.cc:6356
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F32(MachInst)
Definition: decoder.cc:4880
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_HI_I32_I24
GPUStaticInst * decode_OP_VOP2__V_MUL_HI_I32_I24(MachInst)
Definition: decoder.cc:3887
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_B_O
Definition: instructions.hh:40963
gem5::VegaISA::Inst_MIMG__IMAGE_GET_RESINFO
Definition: instructions.hh:38795
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U32(MachInst)
Definition: decoder.cc:5618
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN
Definition: instructions.hh:42321
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG2ST64_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG2ST64_RTN_B32(MachInst)
Definition: decoder.cc:7469
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F32
Definition: instructions.hh:19471
gem5::VegaISA::Inst_VOP2__V_MUL_U32_U24
Definition: instructions.hh:6413
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I32(MachInst)
Definition: decoder.cc:12515
gem5::VegaISA::Inst_VOPC__V_CMP_F_I16
Definition: instructions.hh:13861
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F32(MachInst)
Definition: decoder.cc:5012
gem5::VegaISA::Decoder::decode_OP_SOP2__S_PACK_LL_B32_B16
GPUStaticInst * decode_OP_SOP2__S_PACK_LL_B32_B16(MachInst)
Definition: decoder.cc:4480
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_L_O(MachInst)
Definition: decoder.cc:9019
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_FMA_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_FMA_F16(MachInst)
Definition: decoder.cc:12955
gem5::VegaISA::Decoder::decode_OP_VOP2__V_AND_B32
GPUStaticInst * decode_OP_VOP2__V_AND_B32(MachInst)
Definition: decoder.cc:3959
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F32(MachInst)
Definition: decoder.cc:12083
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX2
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX2(MachInst)
Definition: decoder.cc:8242
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U32
Definition: instructions.hh:22701
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:8635
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F32
Definition: instructions.hh:12671
gem5::VegaISA::Inst_VOP2__V_SUBREV_F16
Definition: instructions.hh:7281
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_INC
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_INC(MachInst)
Definition: decoder.cc:10437
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE1
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE1(MachInst)
Definition: decoder.cc:11298
gem5::VegaISA::Inst_DS__DS_MSKOR_B64
Definition: instructions.hh:33225
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P2_LEGACY_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P2_LEGACY_F16(MachInst)
Definition: decoder.cc:7022
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_FLR_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_FLR_I32_F32(MachInst)
Definition: decoder.cc:11268
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MUL_HI_U32
GPUStaticInst * decode_OP_SOP2__S_MUL_HI_U32(MachInst)
Definition: decoder.cc:4439
gem5::VegaISA::Inst_VOP1__V_SIN_F32
Definition: instructions.hh:9341
gem5::VegaISA::Inst_VOP3__V_FMA_F32
Definition: instructions.hh:28371
gem5::VegaISA::Decoder::decode_OP_SMEM__S_STORE_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORDX2(MachInst)
Definition: decoder.cc:10016
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RCP_F32
GPUStaticInst * decode_OPU_VOP3__V_RCP_F32(MachInst)
Definition: decoder.cc:6308
gem5::VegaISA::Inst_SOPP__S_WAKEUP
Definition: instructions.hh:4509
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4H_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4H_PCK(MachInst)
Definition: decoder.cc:9146
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U16(MachInst)
Definition: decoder.cc:5420
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F16
Definition: instructions.hh:18009
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX3
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:8494
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_U32
GPUStaticInst * decode_OP_VOP2__V_MIN_U32(MachInst)
Definition: decoder.cc:3929
gem5::VegaISA::Inst_VOP3__V_FREXP_EXP_I16_F16
Definition: instructions.hh:27655
gem5::VegaISA::Decoder::tableDecodePrimary
static IsaDecodeMethod tableDecodePrimary[512]
Definition: gpu_decoder.hh:61
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_INV_VOL
GPUStaticInst * decode_OP_SMEM__S_DCACHE_INV_VOL(MachInst)
Definition: decoder.cc:10128
gem5::VegaISA::Inst_SMEM__S_STORE_DWORDX4
Definition: instructions.hh:5755
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SUB
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SUB(MachInst)
Definition: decoder.cc:10381
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
Definition: instructions.hh:36213
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U32(MachInst)
Definition: decoder.cc:12545
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATC_PROBE_BUFFER
GPUStaticInst * decode_OP_SMEM__S_ATC_PROBE_BUFFER(MachInst)
Definition: decoder.cc:10158
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_XOR
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_XOR(MachInst)
Definition: decoder.cc:10430
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16_HI(MachInst)
Definition: decoder.cc:9922
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMAX
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:9661
gem5::VegaISA::InstFormat
Definition: gpu_decoder.hh:1901
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U64
Definition: instructions.hh:16989
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW(MachInst)
Definition: decoder.cc:9328
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_O(MachInst)
Definition: decoder.cc:9202
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_O(MachInst)
Definition: decoder.cc:9238
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I16
Definition: instructions.hh:21273
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_I64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_I64(MachInst)
Definition: decoder.cc:8078
gem5::VegaISA::Inst_VOP3__V_MUL_U32_U24
Definition: instructions.hh:24233
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_CL(MachInst)
Definition: decoder.cc:8935
gem5::VegaISA::Inst_SOPP__S_BRANCH
Definition: instructions.hh:4479
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_XOR_X2
Definition: instructions.hh:37719
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:9485
gem5::VegaISA::Inst_SOP1__S_SEXT_I32_I8
Definition: instructions.hh:2885
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY(MachInst)
Definition: decoder.cc:9316
gem5::VegaISA::Decoder::decode_OP_SOP2__S_PACK_LH_B32_B16
GPUStaticInst * decode_OP_SOP2__S_PACK_LH_B32_B16(MachInst)
Definition: decoder.cc:4487
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_O(MachInst)
Definition: decoder.cc:9184
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F16
Definition: instructions.hh:11549
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_UMAX
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:8863
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_U16
GPUStaticInst * decode_OP_VOP2__V_ADD_U16(MachInst)
Definition: decoder.cc:4073
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG_RTN_B32(MachInst)
Definition: decoder.cc:7457
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F16_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_F32(MachInst)
Definition: decoder.cc:11250
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ABS_I32
GPUStaticInst * decode_OP_SOP1__S_ABS_I32(MachInst)
Definition: decoder.cc:10824
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16_HI(MachInst)
Definition: decoder.cc:10073
gem5::VegaISA::Inst_DS__DS_WRXCHG2_RTN_B32
Definition: instructions.hh:32235
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B32
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B32(MachInst)
Definition: decoder.cc:5918
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_I32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_I32_F64(MachInst)
Definition: decoder.cc:6122
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I64
Definition: instructions.hh:16173
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U16(MachInst)
Definition: decoder.cc:12449
gem5::VegaISA::Inst_SOPC__S_BITCMP0_B64
Definition: instructions.hh:4227
gem5::VegaISA::Inst_SOP1__S_MOVRELD_B32
Definition: instructions.hh:3587
gem5::VegaISA::InFmt_MUBUF::OP
unsigned int OP
Definition: gpu_decoder.hh:1709
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F64(MachInst)
Definition: decoder.cc:5060
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:8404
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U64(MachInst)
Definition: decoder.cc:5678
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_B_O
Definition: instructions.hh:41179
gem5::VegaISA::Decoder::decode_OP_SOPK__S_GETREG_B32
GPUStaticInst * decode_OP_SOPK__S_GETREG_B32(MachInst)
Definition: decoder.cc:4603
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F32
Definition: instructions.hh:18859
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_I16
GPUStaticInst * decode_OPU_VOP3__V_MAX_I16(MachInst)
Definition: decoder.cc:6086
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U16(MachInst)
Definition: decoder.cc:12359
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F32
Definition: instructions.hh:19165
gem5::VegaISA::Inst_DS__DS_RSUB_U32
Definition: instructions.hh:31043
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_VCCZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_VCCZ(MachInst)
Definition: decoder.cc:11027
gem5::VegaISA::Inst_VOP3__V_MOV_FED_B32
Definition: instructions.hh:25899
gem5::VegaISA::Inst_DS__DS_READ_B64
Definition: instructions.hh:34167
gem5::VegaISA::Decoder::subDecode_OP_DS
GPUStaticInst * subDecode_OP_DS(MachInst)
Definition: decoder.cc:3792
gem5::VegaISA::Inst_SOP1__S_SWAPPC_B64
Definition: instructions.hh:3139
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX4
Definition: instructions.hh:41908
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U16
Definition: instructions.hh:14745
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_DEC
Definition: instructions.hh:39237
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U64(MachInst)
Definition: decoder.cc:5684
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F64(MachInst)
Definition: decoder.cc:12221
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F64
Definition: instructions.hh:12909
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMAX
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:8338
gem5::VegaISA::Inst_VOP1__V_FRACT_F64
Definition: instructions.hh:9629
gem5::VegaISA::Inst_VOP2__V_MADAK_F16
Definition: instructions.hh:7419
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_OFF_F32_I4
GPUStaticInst * decode_OP_VOP1__V_CVT_OFF_F32_I4(MachInst)
Definition: decoder.cc:11274
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAC_F16
GPUStaticInst * decode_OPU_VOP3__V_MAC_F16(MachInst)
Definition: decoder.cc:6020
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I64(MachInst)
Definition: decoder.cc:12791
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_SHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_SHORT(MachInst)
Definition: decoder.cc:9564
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F32
Definition: instructions.hh:11991
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I32
Definition: instructions.hh:22429
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ALIGNBIT_B32
GPUStaticInst * decode_OPU_VOP3__V_ALIGNBIT_B32(MachInst)
Definition: decoder.cc:6632
gem5::VegaISA::Inst_VOP3__V_MIN_U16
Definition: instructions.hh:25545
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F16
Definition: instructions.hh:18281
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F64(MachInst)
Definition: decoder.cc:12215
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F64(MachInst)
Definition: decoder.cc:12185
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_SEMA_V
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_V(MachInst)
Definition: decoder.cc:7999
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CL_O(MachInst)
Definition: decoder.cc:9001
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F64
Definition: instructions.hh:13385
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U32
Definition: instructions.hh:16003
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F64(MachInst)
Definition: decoder.cc:5216
gem5::VegaISA::Inst_SOPP__S_TTRACEDATA
Definition: instructions.hh:5083
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_LSHLREV_B16
GPUStaticInst * decode_OP_VOP3P__V_PK_LSHLREV_B16(MachInst)
Definition: decoder.cc:12885
gem5::VegaISA::Inst_SOP2__S_AND_B32
Definition: instructions.hh:453
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I64
Definition: instructions.hh:22905
gem5::VegaISA::Decoder::decode_OP_SOPP__S_INCPERFLEVEL
GPUStaticInst * decode_OP_SOPP__S_INCPERFLEVEL(MachInst)
Definition: decoder.cc:11111
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F16(MachInst)
Definition: decoder.cc:4742
gem5::VegaISA::Inst_DS__DS_SUB_RTN_U64
Definition: instructions.hh:33521
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SIN_F32
GPUStaticInst * decode_OP_VOP1__V_SIN_F32(MachInst)
Definition: decoder.cc:11436
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U32(MachInst)
Definition: decoder.cc:5492
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I32
Definition: instructions.hh:15051
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I64
Definition: instructions.hh:16649
gem5::VegaISA::Inst_VOP3__V_INTERP_P2_F16
Definition: instructions.hh:30127
gem5::VegaISA::Inst_VOP1__V_CVT_F16_I16
Definition: instructions.hh:9785
gem5::VegaISA::InstFormat::iFmt_SMEM
InFmt_SMEM iFmt_SMEM
Definition: gpu_decoder.hh:1915
gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE0
Definition: instructions.hh:8573
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I16(MachInst)
Definition: decoder.cc:12323
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_CO_U32
GPUStaticInst * decode_OP_VOP2__V_SUB_CO_U32(MachInst)
Definition: decoder.cc:4001
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_I64_I32
GPUStaticInst * decode_OPU_VOP3__V_MAD_I64_I32(MachInst)
Definition: decoder.cc:6794
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F64
Definition: instructions.hh:19641
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I64
Definition: instructions.hh:22939
gem5::VegaISA::Inst_VOP3__V_BFE_I32
Definition: instructions.hh:28299
gem5::VegaISA::Inst_SOP2__S_NAND_B32
Definition: instructions.hh:793
gem5::VegaISA::InFmt_VOP1
Definition: gpu_decoder.hh:1785
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:10269
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX_X2
Definition: instructions.hh:42917
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CD
Definition: instructions.hh:41323
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F16(MachInst)
Definition: decoder.cc:4856
gem5::VegaISA::Inst_DS__DS_GWS_INIT
Definition: instructions.hh:34813
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:9364
gem5::VegaISA::InstFormat::iFmt_EXP
InFmt_EXP iFmt_EXP
Definition: gpu_decoder.hh:1904
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX2
Definition: instructions.hh:41834
gem5::VegaISA::Inst_VOP2__V_SUBREV_CO_U32
Definition: instructions.hh:7063
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN
Definition: instructions.hh:42358
gem5::VegaISA::Inst_VOP3__V_CVT_PK_U16_U32
Definition: instructions.hh:30911
gem5::VegaISA::Inst_VOPC__V_CMP_T_U64
Definition: instructions.hh:16547
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F32
Definition: instructions.hh:11787
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F64
Definition: instructions.hh:19675
gem5::VegaISA::Decoder::tableSubDecode_OP_VOP3P
static IsaDecodeMethod tableSubDecode_OP_VOP3P[128]
Definition: gpu_decoder.hh:77
gem5::VegaISA::Inst_DS__DS_INC_U32
Definition: instructions.hh:31075
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F64(MachInst)
Definition: decoder.cc:12209
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_I32
GPUStaticInst * decode_OP_DS__DS_MAX_I32(MachInst)
Definition: decoder.cc:7264
gem5::VegaISA::Inst_SOP1__S_SEXT_I32_I16
Definition: instructions.hh:2917
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMIN
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:8332
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_LZ
Definition: instructions.hh:39523
gem5::VegaISA::Inst_SOP1__S_NOT_B64
Definition: instructions.hh:2341
gem5::VegaISA::Inst_VOP3__V_ADD_U16
Definition: instructions.hh:25171
gem5::VegaISA::Inst_VOP3__V_MAD_U64_U32
Definition: instructions.hh:29421
gem5::VegaISA::Inst_VOP3__V_CVT_F16_I16
Definition: instructions.hh:27367
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:10290
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F32(MachInst)
Definition: decoder.cc:4898
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I32(MachInst)
Definition: decoder.cc:12491
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I16(MachInst)
Definition: decoder.cc:5246
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U32(MachInst)
Definition: decoder.cc:5612
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F64_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_U32(MachInst)
Definition: decoder.cc:6236
gem5::VegaISA::Inst_DS__DS_ORDERED_COUNT
Definition: instructions.hh:35033
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_B_CL
Definition: instructions.hh:39775
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F16
Definition: instructions.hh:18315
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F16(MachInst)
Definition: decoder.cc:4676
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_DWORD
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_DWORD(MachInst)
Definition: decoder.cc:9803
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U64
Definition: instructions.hh:23857
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORD
Definition: instructions.hh:36647
gem5::VegaISA::Inst_DS__DS_ADD_RTN_F32
Definition: instructions.hh:32473
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
Definition: instructions.hh:38169
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U16
Definition: instructions.hh:14677
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FFBH_I32
GPUStaticInst * decode_OPU_VOP3__V_FFBH_I32(MachInst)
Definition: decoder.cc:6386
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F64(MachInst)
Definition: decoder.cc:5204
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F32
Definition: instructions.hh:12637
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X(MachInst)
Definition: decoder.cc:9479
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SHORT_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SHORT_D16_HI(MachInst)
Definition: decoder.cc:8592
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I16
Definition: instructions.hh:14575
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MIN_I32
GPUStaticInst * decode_OP_SOP2__S_MIN_I32(MachInst)
Definition: decoder.cc:4211
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I16(MachInst)
Definition: decoder.cc:12413
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_RTN_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_RTN_U64(MachInst)
Definition: decoder.cc:7759
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F64
Definition: instructions.hh:20661
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_F64
GPUStaticInst * decode_OPU_VOP3__V_MUL_F64(MachInst)
Definition: decoder.cc:7041
gem5::VegaISA::Inst_VOP3__V_MIN_I32
Definition: instructions.hh:24369
gem5::VegaISA::Decoder::decode_OP_VOP1__V_MOV_B32
GPUStaticInst * decode_OP_VOP1__V_MOV_B32(MachInst)
Definition: decoder.cc:11202
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MADMK_F16
GPUStaticInst * decode_OP_VOP2__V_MADMK_F16(MachInst)
Definition: decoder.cc:4061
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U32
Definition: instructions.hh:15289
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F64
Definition: instructions.hh:13759
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MUL_LO_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_MUL_LO_U16(MachInst)
Definition: decoder.cc:12864
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I64(MachInst)
Definition: decoder.cc:5672
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U32(MachInst)
Definition: decoder.cc:12539
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_O
Definition: instructions.hh:39847
gem5::VegaISA::Inst_DS__DS_WRXCHG2ST64_RTN_B32
Definition: instructions.hh:32269
gem5::VegaISA::Inst_VOP3__V_CVT_FLR_I32_F32
Definition: instructions.hh:26027
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B(MachInst)
Definition: decoder.cc:9166
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U64(MachInst)
Definition: decoder.cc:5816
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_CL(MachInst)
Definition: decoder.cc:8917
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_D_CL_O
Definition: instructions.hh:39955
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_F32(MachInst)
Definition: decoder.cc:6548
gem5::VegaISA::Inst_SOP1__S_NAND_SAVEEXEC_B64
Definition: instructions.hh:3363
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X
Definition: instructions.hh:36099
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE0
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE0(MachInst)
Definition: decoder.cc:6206
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MOV_B32
GPUStaticInst * decode_OPU_VOP3__V_MOV_B32(MachInst)
Definition: decoder.cc:6116
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGUSER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGUSER(MachInst)
Definition: decoder.cc:11135
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U32
Definition: instructions.hh:15833
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F16
Definition: instructions.hh:10937
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_I16
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_I16(MachInst)
Definition: decoder.cc:6812
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F16(MachInst)
Definition: decoder.cc:11711
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
Definition: instructions.hh:38359
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U64
Definition: instructions.hh:23177
gem5::VegaISA::InFmt_SOP1
Definition: gpu_decoder.hh:1741
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_UBYTE
Definition: instructions.hh:41649
gem5::VegaISA::Inst_VOP3__V_MIN_F32
Definition: instructions.hh:24301
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_CL(MachInst)
Definition: decoder.cc:9097
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_I64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_I64(MachInst)
Definition: decoder.cc:7777
gem5::VegaISA::Inst_VOP3__V_FLOOR_F16
Definition: instructions.hh:27687
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U32(MachInst)
Definition: decoder.cc:12563
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:8713
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RNDNE_F32
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F32(MachInst)
Definition: decoder.cc:11370
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_DEC_SRC2_U64(MachInst)
Definition: decoder.cc:8072
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LT_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LT_U32(MachInst)
Definition: decoder.cc:10931
gem5::VegaISA::Inst_VOP3__V_MAX_U16
Definition: instructions.hh:25477
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_U64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_U64(MachInst)
Definition: decoder.cc:7789
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_SUB_CO_U32(MachInst)
Definition: decoder.cc:5966
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F64(MachInst)
Definition: decoder.cc:4646
gem5::VegaISA::Inst_SOPK__S_CBRANCH_I_FORK
Definition: instructions.hh:2053
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F16(MachInst)
Definition: decoder.cc:4748
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B64
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B64(MachInst)
Definition: decoder.cc:7119
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX4
Definition: instructions.hh:36761
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U64
Definition: instructions.hh:23211
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U32
Definition: instructions.hh:22837
gem5::VegaISA::Inst_DS__DS_PERMUTE_B32
Definition: instructions.hh:32773
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_F64
Definition: instructions.hh:35485
gem5::VegaISA::Inst_VINTRP__V_INTERP_MOV_F32
Definition: instructions.hh:17193
gem5::VegaISA::Decoder::decode_OP_VOP2__V_OR_B32
GPUStaticInst * decode_OP_VOP2__V_OR_B32(MachInst)
Definition: decoder.cc:3965
gem5::VegaISA::Inst_DS__DS_MIN_RTN_I32
Definition: instructions.hh:31929
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITSET0_B64
GPUStaticInst * decode_OP_SOP1__S_BITSET0_B64(MachInst)
Definition: decoder.cc:10692
gem5::VegaISA::Inst_VOP3__V_TRUNC_F64
Definition: instructions.hh:26347
gem5::VegaISA::Inst_MUBUF__BUFFER_WBINVL1_VOL
Definition: instructions.hh:36861
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMAX
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:9655
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RSQ_F32
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F32(MachInst)
Definition: decoder.cc:6320
gem5::VegaISA::Decoder::tableSubDecode_OP_GLOBAL
static IsaDecodeMethod tableSubDecode_OP_GLOBAL[128]
Definition: gpu_decoder.hh:65
gem5::VegaISA::Inst_SOPP__S_SETHALT
Definition: instructions.hh:4813
gem5::VegaISA::Inst_DS__DS_MIN_F32
Definition: instructions.hh:31565
gem5::VegaISA::InFmt_VOPC
Definition: gpu_decoder.hh:1825
gem5::VegaISA::Inst_DS__DS_DEC_RTN_U32
Definition: instructions.hh:31895
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW
Definition: instructions.hh:35757
gem5::VegaISA::Inst_DS__DS_MAX_F32
Definition: instructions.hh:31597
gem5::VegaISA::Decoder::decode_OP_SOP1__S_NAND_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_NAND_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10764
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F32(MachInst)
Definition: decoder.cc:4952
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_U32
GPUStaticInst * decode_OP_DS__DS_DEC_U32(MachInst)
Definition: decoder.cc:7252
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MIN_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_MIN_F16(MachInst)
Definition: decoder.cc:12976
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_I64
Definition: instructions.hh:35245
gem5::VegaISA::Inst_DS__DS_MIN_RTN_F32
Definition: instructions.hh:32371
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_B_O
Definition: instructions.hh:40315
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_AND
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_AND(MachInst)
Definition: decoder.cc:8869
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I64
Definition: instructions.hh:23415
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I64
Definition: instructions.hh:23007
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ANDN2_WREXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN2_WREXEC_B64(MachInst)
Definition: decoder.cc:10857
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD(MachInst)
Definition: decoder.cc:9274
gem5::VegaISA::Inst_DS__DS_MIN_I32
Definition: instructions.hh:31139
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I64(MachInst)
Definition: decoder.cc:5666
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F32(MachInst)
Definition: decoder.cc:4634
gem5::VegaISA::Inst_DS__DS_MAX_I32
Definition: instructions.hh:31171
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_B128
GPUStaticInst * decode_OP_DS__DS_READ_B128(MachInst)
Definition: decoder.cc:8156
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I64(MachInst)
Definition: decoder.cc:12701
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX16
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX16(MachInst)
Definition: decoder.cc:9953
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F32(MachInst)
Definition: decoder.cc:11675
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_MAD_MIXHI_F16
GPUStaticInst * decode_OP_VOP3P__V_MAD_MIXHI_F16(MachInst)
Definition: decoder.cc:13004
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F16
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F16(MachInst)
Definition: decoder.cc:6986
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW(MachInst)
Definition: decoder.cc:9352
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_I32_I16
GPUStaticInst * decode_OPU_VOP3__V_MAD_I32_I16(MachInst)
Definition: decoder.cc:6849
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_L
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_L(MachInst)
Definition: decoder.cc:9110
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I64
Definition: instructions.hh:23585
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_CO_U32
GPUStaticInst * decode_OP_VOP2__V_SUBREV_CO_U32(MachInst)
Definition: decoder.cc:4007
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F64
Definition: instructions.hh:19743
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_LZ_O
Definition: instructions.hh:40387
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_DWORD
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_DWORD(MachInst)
Definition: decoder.cc:8482
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LSHRREV_B16
GPUStaticInst * decode_OP_VOP2__V_LSHRREV_B16(MachInst)
Definition: decoder.cc:4103
gem5::VegaISA::InFmt_VOP3P::OP
unsigned int OP
Definition: gpu_decoder.hh:1889
gem5::VegaISA::Inst_DS__DS_READ2ST64_B32
Definition: instructions.hh:32575
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U32(MachInst)
Definition: decoder.cc:12659
gem5::VegaISA::Inst_DS__DS_CMPST_B64
Definition: instructions.hh:33359
gem5::VegaISA::Inst_SOPC__S_CMP_GT_I32
Definition: instructions.hh:3843
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F64
Definition: instructions.hh:20151
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_I16
GPUStaticInst * decode_OPU_VOP3__V_MAX3_I16(MachInst)
Definition: decoder.cc:6891
gem5::VegaISA::Decoder::subDecode_OP_SOPC
GPUStaticInst * subDecode_OP_SOPC(MachInst)
Definition: decoder.cc:3752
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4
Definition: instructions.hh:5395
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I64
Definition: instructions.hh:16581
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_I32(MachInst)
Definition: decoder.cc:6134
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F32
Definition: instructions.hh:19403
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBREV_F32
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_F32(MachInst)
Definition: decoder.cc:5840
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B96
GPUStaticInst * decode_OP_DS__DS_WRITE_B96(MachInst)
Definition: decoder.cc:8138
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F16
Definition: instructions.hh:11447
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX2
Definition: instructions.hh:36685
gem5::VegaISA::Decoder::decode_OP_VOP1__V_EXP_LEGACY_F32
GPUStaticInst * decode_OP_VOP1__V_EXP_LEGACY_F32(MachInst)
Definition: decoder.cc:11629
gem5::VegaISA::Inst_VOP3__V_CMP_U_F16
Definition: instructions.hh:17703
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITSET1_B64
GPUStaticInst * decode_OP_SOP1__S_BITSET1_B64(MachInst)
Definition: decoder.cc:10704
gem5::VegaISA::Inst_DS__DS_CMPST_F64
Definition: instructions.hh:33391
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U16
Definition: instructions.hh:21511
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U32(MachInst)
Definition: decoder.cc:5486
gem5::VegaISA::Inst_VOP3__V_CVT_PKNORM_U16_F32
Definition: instructions.hh:30843
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I64(MachInst)
Definition: decoder.cc:12767
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F64
Definition: instructions.hh:13317
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F16(MachInst)
Definition: decoder.cc:4688
gem5::VegaISA::Inst_VOP1__V_RSQ_F16
Definition: instructions.hh:9945
gem5::VegaISA::Inst_SOP2__S_ORN2_B64
Definition: instructions.hh:759
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW
Definition: instructions.hh:38093
gem5::VegaISA::Inst_VOP3__V_CMP_O_F64
Definition: instructions.hh:19845
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_I64
GPUStaticInst * decode_OP_DS__DS_MIN_I64(MachInst)
Definition: decoder.cc:7601
gem5::VegaISA::Inst_VOP1__V_RCP_F16
Definition: instructions.hh:9881
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOV_B32
GPUStaticInst * decode_OP_SOP1__S_MOV_B32(MachInst)
Definition: decoder.cc:10542
gem5::VegaISA::Inst_VOP3__V_EXP_F16
Definition: instructions.hh:27591
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F16(MachInst)
Definition: decoder.cc:11879
gem5::VegaISA::Inst_VOP1__V_CVT_F64_U32
Definition: instructions.hh:8733
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FLOOR_F16
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F16(MachInst)
Definition: decoder.cc:6494
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I32
Definition: instructions.hh:21885
gem5::VegaISA::Inst_DS__DS_MIN_U32
Definition: instructions.hh:31203
gem5::VegaISA::Inst_DS__DS_MAX_U32
Definition: instructions.hh:31235
gem5::VegaISA::Inst_VOP3__V_MIN_I16
Definition: instructions.hh:25579
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_ADD_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_ADD_I16(MachInst)
Definition: decoder.cc:12871
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F32(MachInst)
Definition: decoder.cc:12023
gem5::VegaISA::Inst_DS__DS_MSKOR_B32
Definition: instructions.hh:31363
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC_X2
Definition: instructions.hh:43102
gem5::VegaISA::InFmt_SOPC
Definition: gpu_decoder.hh:1756
gem5::VegaISA::Inst_VOP1__V_BFREV_B32
Definition: instructions.hh:9437
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_CL(MachInst)
Definition: decoder.cc:9122
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SQRT_F16
GPUStaticInst * decode_OP_VOP1__V_SQRT_F16(MachInst)
Definition: decoder.cc:11551
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X(MachInst)
Definition: decoder.cc:9382
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U64(MachInst)
Definition: decoder.cc:12731
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ASHRREV_I16
GPUStaticInst * decode_OP_VOP2__V_ASHRREV_I16(MachInst)
Definition: decoder.cc:4109
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_U32
GPUStaticInst * decode_OP_VOP2__V_MAX_U32(MachInst)
Definition: decoder.cc:3935
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_O
Definition: instructions.hh:41539
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F32
Definition: instructions.hh:18621
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F64(MachInst)
Definition: decoder.cc:12239
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F32
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F32(MachInst)
Definition: decoder.cc:6416
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I16(MachInst)
Definition: decoder.cc:5288
gem5::VegaISA::Inst_SOPC__S_CMP_GT_U32
Definition: instructions.hh:4035
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U16
Definition: instructions.hh:14711
gem5::VegaISA::Inst_VOP3__V_RCP_IFLAG_F32
Definition: instructions.hh:26731
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F64_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_F32(MachInst)
Definition: decoder.cc:6200
gem5::VegaISA::Inst_VOP3__V_CVT_F64_U32
Definition: instructions.hh:26315
gem5::VegaISA::Inst_VOP3__V_MIN_F16
Definition: instructions.hh:25443
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:8689
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
Definition: instructions.hh:37395
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_F16
GPUStaticInst * decode_OP_VOP2__V_SUBREV_F16(MachInst)
Definition: decoder.cc:4043
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_O_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F16(MachInst)
Definition: decoder.cc:11747
gem5::VegaISA::Inst_VOP1__V_RNDNE_F32
Definition: instructions.hh:8989
gem5::VegaISA::Inst_VOP3__V_LDEXP_F16
Definition: instructions.hh:25613
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U64(MachInst)
Definition: decoder.cc:5774
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F16(MachInst)
Definition: decoder.cc:4682
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_U_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F64(MachInst)
Definition: decoder.cc:12233
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F32(MachInst)
Definition: decoder.cc:4892
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U64
Definition: instructions.hh:23279
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_EXECNZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_EXECNZ(MachInst)
Definition: decoder.cc:11045
gem5::VegaISA::Inst_DS__DS_WRITE_B16
Definition: instructions.hh:31725
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD3_U32
GPUStaticInst * decode_OPU_VOP3__V_ADD3_U32(MachInst)
Definition: decoder.cc:6938
gem5::VegaISA::Decoder::decode
GPUStaticInst * decode(MachInst mach_inst)
Definition: decoder.cc:3712
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SHORT_D16
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SHORT_D16(MachInst)
Definition: decoder.cc:8585
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CD_O
Definition: instructions.hh:41467
gem5::VegaISA::Inst_DS__DS_AND_SRC2_B32
Definition: instructions.hh:34573
gem5::VegaISA::Inst_SMEM__S_DCACHE_WB
Definition: instructions.hh:5927
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F16(MachInst)
Definition: decoder.cc:11837
gem5::VegaISA::Inst_SOP1__S_GETPC_B64
Definition: instructions.hh:3077
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O(MachInst)
Definition: decoder.cc:9244
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_I16
GPUStaticInst * decode_OPU_VOP3__V_MIN_I16(MachInst)
Definition: decoder.cc:6098
gem5::VegaISA::Inst_SOP1__S_NOR_SAVEEXEC_B64
Definition: instructions.hh:3395
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F16
Definition: instructions.hh:17805
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F32
Definition: instructions.hh:18927
gem5::VegaISA::Inst_VOP1__V_SQRT_F16
Definition: instructions.hh:9913
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORD
Definition: instructions.hh:42019
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9986
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O(MachInst)
Definition: decoder.cc:9049
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F64
Definition: instructions.hh:13827
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F16(MachInst)
Definition: decoder.cc:4760
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
Definition: instructions.hh:38245
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_PCK_SGN
Definition: instructions.hh:38543
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SQRT_F64
GPUStaticInst * decode_OP_VOP1__V_SQRT_F64(MachInst)
Definition: decoder.cc:11430
gem5::VegaISA::Inst_VOP3__V_ADD_F16
Definition: instructions.hh:25001
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FLOOR_F64
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F64(MachInst)
Definition: decoder.cc:6260
gem5::VegaISA::Inst_VOP1__V_CEIL_F64
Definition: instructions.hh:8797
gem5::VegaISA::Inst_DS__DS_DEC_SRC2_U32
Definition: instructions.hh:34423
gem5::VegaISA::Inst_SOP1__S_BITSET1_B32
Definition: instructions.hh:3013
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_F32(MachInst)
Definition: decoder.cc:7981
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P1LV_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1LV_F16(MachInst)
Definition: decoder.cc:7016
gem5::VegaISA::Inst_VOPC__V_CMP_U_F32
Definition: instructions.hh:11957
gem5::VegaISA::Inst_VOP3__V_MUL_LO_U16
Definition: instructions.hh:25273
gem5::VegaISA::Decoder::subDecode_OP_MIMG
GPUStaticInst * subDecode_OP_MIMG(MachInst)
Definition: decoder.cc:3837
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U32
Definition: instructions.hh:15867
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_XOR
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_XOR(MachInst)
Definition: decoder.cc:9679
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F64(MachInst)
Definition: decoder.cc:12125
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_GT_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GT_I32(MachInst)
Definition: decoder.cc:4525
gem5::VegaISA::Decoder::decode_OP_SOPK__S_MULK_I32
GPUStaticInst * decode_OP_SOPK__S_MULK_I32(MachInst)
Definition: decoder.cc:4591
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFE_U32
GPUStaticInst * decode_OPU_VOP3__V_BFE_U32(MachInst)
Definition: decoder.cc:6596
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_O
Definition: instructions.hh:40855
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_SHORT_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_SHORT_D16_HI(MachInst)
Definition: decoder.cc:8229
gem5::VegaISA::Inst_DS__DS_WRITE_B128
Definition: instructions.hh:35547
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_F16
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_F16(MachInst)
Definition: decoder.cc:6800
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:8683
gem5::VegaISA::InstFormat::iFmt_VOP3A
InFmt_VOP3A iFmt_VOP3A
Definition: gpu_decoder.hh:1925
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBBREV_CO_U32
GPUStaticInst * decode_OP_VOP2__V_SUBBREV_CO_U32(MachInst)
Definition: decoder.cc:4025
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F32
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F32(MachInst)
Definition: decoder.cc:11502
gem5::VegaISA::Inst_VOP3__V_MQSAD_U32_U8
Definition: instructions.hh:29385
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_U32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_U32(MachInst)
Definition: decoder.cc:6656
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FFBH_I32
GPUStaticInst * decode_OP_VOP1__V_FFBH_I32(MachInst)
Definition: decoder.cc:11472
gem5::VegaISA::Inst_DS__DS_ADD_RTN_U32
Definition: instructions.hh:31759
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE2ST64_B64
GPUStaticInst * decode_OP_DS__DS_WRITE2ST64_B64(MachInst)
Definition: decoder.cc:7661
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U32
Definition: instructions.hh:22157
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F16(MachInst)
Definition: decoder.cc:11741
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F16(MachInst)
Definition: decoder.cc:4808
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U64(MachInst)
Definition: decoder.cc:12827
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_XOR_RTN_B64(MachInst)
Definition: decoder.cc:7813
gem5::VegaISA::Inst_MIMG__IMAGE_STORE_MIP
Definition: instructions.hh:38687
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F32
Definition: instructions.hh:19301
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I16(MachInst)
Definition: decoder.cc:12317
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F32(MachInst)
Definition: decoder.cc:4982
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F64(MachInst)
Definition: decoder.cc:5174
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_I64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_I64(MachInst)
Definition: decoder.cc:8084
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_XOR
Definition: instructions.hh:39169
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS(MachInst)
Definition: decoder.cc:11129
gem5::VegaISA::Inst_VOP3__V_ADD_LSHL_U32
Definition: instructions.hh:29533
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F64(MachInst)
Definition: decoder.cc:5150
gem5::VegaISA::InFmt_SOPC::OP
unsigned int OP
Definition: gpu_decoder.hh:1759
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I32(MachInst)
Definition: decoder.cc:5444
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX3
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:8198
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL(MachInst)
Definition: decoder.cc:8965
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F64(MachInst)
Definition: decoder.cc:5180
gem5::VegaISA::Inst_SOP1__S_BREV_B64
Definition: instructions.hh:2469
gem5::VegaISA::Inst_VOP3__V_MAX_I16
Definition: instructions.hh:25511
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:10304
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4
Definition: instructions.hh:40423
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F32
Definition: instructions.hh:12467
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_OR_RTN_B64(MachInst)
Definition: decoder.cc:7807
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CD_CL
Definition: instructions.hh:41359
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SSHORT
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SSHORT(MachInst)
Definition: decoder.cc:8180
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F16(MachInst)
Definition: decoder.cc:4784
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F16(MachInst)
Definition: decoder.cc:4772
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F32
Definition: instructions.hh:11855
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_BYTE
Definition: instructions.hh:36563
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U16(MachInst)
Definition: decoder.cc:12425
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_BARRIER
GPUStaticInst * decode_OP_DS__DS_GWS_BARRIER(MachInst)
Definition: decoder.cc:8017
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U64(MachInst)
Definition: decoder.cc:12821
gem5::VegaISA::Decoder::decode_OP_SOPP__S_BRANCH
GPUStaticInst * decode_OP_SOPP__S_BRANCH(MachInst)
Definition: decoder.cc:11003
gem5::VegaISA::Inst_SOP2__S_RFE_RESTORE_B64
Definition: instructions.hh:1507
gem5::VegaISA::Inst_SOPC__S_CMP_GE_I32
Definition: instructions.hh:3875
gem5::VegaISA::Inst_VOP3__V_ALIGNBIT_B32
Definition: instructions.hh:28479
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_RTN_F32
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_F32(MachInst)
Definition: decoder.cc:7481
gem5::VegaISA::Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER
Definition: instructions.hh:5203
gem5::VegaISA::Inst_SMEM__S_MEMREALTIME
Definition: instructions.hh:6041
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_F32
GPUStaticInst * decode_OPU_VOP3__V_MED3_F32(MachInst)
Definition: decoder.cc:6680
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:10213
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_U64
Definition: instructions.hh:35275
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL(MachInst)
Definition: decoder.cc:7987
gem5::VegaISA::Inst_VOP3__V_MAX_F16
Definition: instructions.hh:25409
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFREV_B32
GPUStaticInst * decode_OPU_VOP3__V_BFREV_B32(MachInst)
Definition: decoder.cc:6368
gem5::VegaISA::InstFormat::iFmt_SOPK
InFmt_SOPK iFmt_SOPK
Definition: gpu_decoder.hh:1920
gem5::VegaISA::Inst_VOP3__V_DIV_FIXUP_F32
Definition: instructions.hh:29055
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U64
Definition: instructions.hh:23721
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F16
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F16(MachInst)
Definition: decoder.cc:11575
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR(MachInst)
Definition: decoder.cc:8659
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U16(MachInst)
Definition: decoder.cc:12431
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F16
Definition: instructions.hh:11515
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F32
Definition: instructions.hh:19505
gem5::VegaISA::Decoder::decode_OP_SOPC__S_BITCMP1_B64
GPUStaticInst * decode_OP_SOPC__S_BITCMP1_B64(MachInst)
Definition: decoder.cc:10961
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ORN2_B32
GPUStaticInst * decode_OP_SOP2__S_ORN2_B32(MachInst)
Definition: decoder.cc:4295
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MADMK_F32
GPUStaticInst * decode_OP_VOP2__V_MADMK_F32(MachInst)
Definition: decoder.cc:3983
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_F32
GPUStaticInst * decode_OP_VOP2__V_ADD_F32(MachInst)
Definition: decoder.cc:3851
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SMIN
Definition: instructions.hh:37035
gem5::VegaISA::Inst_DS__DS_AND_RTN_B64
Definition: instructions.hh:33793
gem5::VegaISA::Inst_VOP3__V_SIN_F32
Definition: instructions.hh:26923
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O(MachInst)
Definition: decoder.cc:9250
gem5::VegaISA::Inst_SOP1__S_WQM_B32
Definition: instructions.hh:2373
gem5::VegaISA::Inst_DS__DS_APPEND
Definition: instructions.hh:35001
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_I16
GPUStaticInst * decode_OP_VOP2__V_MIN_I16(MachInst)
Definition: decoder.cc:4145
gem5::VegaISA::Inst_DS__DS_MIN_RTN_U32
Definition: instructions.hh:31997
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U64
Definition: instructions.hh:16343
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CALL_B64
GPUStaticInst * decode_OP_SOPK__S_CALL_B64(MachInst)
Definition: decoder.cc:4621
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_SUB
Definition: instructions.hh:38931
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X(MachInst)
Definition: decoder.cc:9358
gem5::VegaISA::Inst_VOP3__V_CUBETC_F32
Definition: instructions.hh:28191
gem5::VegaISA::Inst_SOPK__S_GETREG_B32
Definition: instructions.hh:2085
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_B
Definition: instructions.hh:39451
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_NOP
GPUStaticInst * decode_OPU_VOP3__V_NOP(MachInst)
Definition: decoder.cc:6110
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_I16
GPUStaticInst * decode_OP_DS__DS_READ_I16(MachInst)
Definition: decoder.cc:7541
gem5::VegaISA::Inst_VOP3__V_CVT_PK_I16_I32
Definition: instructions.hh:30945
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_I8_D16
GPUStaticInst * decode_OP_DS__DS_READ_I8_D16(MachInst)
Definition: decoder.cc:7719
gem5::VegaISA::Decoder::tableSubDecode_OP_DS
static IsaDecodeMethod tableSubDecode_OP_DS[256]
Definition: gpu_decoder.hh:63
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F16
Definition: instructions.hh:11005
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMIN
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:8326
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I16(MachInst)
Definition: decoder.cc:5360
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U64
Definition: instructions.hh:16377
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F32
Definition: instructions.hh:12195
gem5::VegaISA::Inst_SOPK__S_MOVK_I32
Definition: instructions.hh:1541
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX3
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:9817
gem5::VegaISA::Decoder::decode_OP_DS__DS_BPERMUTE_B32
GPUStaticInst * decode_OP_DS__DS_BPERMUTE_B32(MachInst)
Definition: decoder.cc:7565
gem5::VegaISA::Inst_VOP3__V_MAC_F32
Definition: instructions.hh:24745
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORD(MachInst)
Definition: decoder.cc:9577
gem5::VegaISA::Inst_VOPC__V_CMP_U_F16
Definition: instructions.hh:10869
gem5::VegaISA::Inst_DS__DS_ADD_U64
Definition: instructions.hh:32841
gem5::VegaISA::Inst_SOPC__S_CMP_GE_U32
Definition: instructions.hh:4067
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_MUL_LEGACY_F32(MachInst)
Definition: decoder.cc:5846
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_DWORDX3
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_DWORDX3(MachInst)
Definition: decoder.cc:9873
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_XOR_RTN_B32(MachInst)
Definition: decoder.cc:7445
gem5::VegaISA::InFmt_FLAT
Definition: gpu_decoder.hh:1633
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_MIP
Definition: instructions.hh:38471
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C
Definition: instructions.hh:40639
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:9721
gem5::VegaISA::Inst_SOP2__S_BFM_B64
Definition: instructions.hh:1235
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I16(MachInst)
Definition: decoder.cc:12419
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I16(MachInst)
Definition: decoder.cc:12377
gem5::VegaISA::Inst_DS__DS_OR_SRC2_B32
Definition: instructions.hh:34603
gem5::VegaISA::InstFormat::iFmt_MUBUF
InFmt_MUBUF iFmt_MUBUF
Definition: gpu_decoder.hh:1913
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:8440
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_DEC
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_DEC(MachInst)
Definition: decoder.cc:9691
gem5::VegaISA::Inst_VOP1__V_COS_F16
Definition: instructions.hh:10297
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_U32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_U32_F64(MachInst)
Definition: decoder.cc:6230
gem5::VegaISA::Decoder::decode_OP_SOP2__S_AND_B32
GPUStaticInst * decode_OP_SOP2__S_AND_B32(MachInst)
Definition: decoder.cc:4247
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LDEXP_F64
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F64(MachInst)
Definition: decoder.cc:7059
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U64(MachInst)
Definition: decoder.cc:12815
gem5::VegaISA::Inst_VOP1__V_RSQ_F64
Definition: instructions.hh:9245
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_U32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_U32(MachInst)
Definition: decoder.cc:7421
gem5::VegaISA::Decoder::decode_OP_SOP2__S_NAND_B32
GPUStaticInst * decode_OP_SOP2__S_NAND_B32(MachInst)
Definition: decoder.cc:4307
gem5::VegaISA::Inst_VOP1__V_TRUNC_F64
Definition: instructions.hh:8765
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATC_PROBE
GPUStaticInst * decode_OP_SMEM__S_ATC_PROBE(MachInst)
Definition: decoder.cc:10152
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RNDNE_F16
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F16(MachInst)
Definition: decoder.cc:11605
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_INIT
GPUStaticInst * decode_OP_DS__DS_GWS_INIT(MachInst)
Definition: decoder.cc:7993
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SAT_PK_U8_I16
GPUStaticInst * decode_OP_VOP1__V_SAT_PK_U8_I16(MachInst)
Definition: decoder.cc:11655
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MUL_I32
GPUStaticInst * decode_OP_SOP2__S_MUL_I32(MachInst)
Definition: decoder.cc:4391
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U32(MachInst)
Definition: decoder.cc:12647
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX4
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:8500
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F64
Definition: instructions.hh:20185
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_O_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F32(MachInst)
Definition: decoder.cc:11939
gem5::VegaISA::Inst_VOP3__V_MUL_HI_U32
Definition: instructions.hh:30367
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_F16
GPUStaticInst * decode_OPU_VOP3__V_SUB_F16(MachInst)
Definition: decoder.cc:6002
gem5::VegaISA::Inst_SOPP__S_CBRANCH_VCCNZ
Definition: instructions.hh:4631
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_I32
GPUStaticInst * decode_OPU_VOP3__V_MAX_I32(MachInst)
Definition: decoder.cc:5900
gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE1
Definition: instructions.hh:26187
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_I64
GPUStaticInst * decode_OP_DS__DS_MAX_I64(MachInst)
Definition: decoder.cc:7607
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B(MachInst)
Definition: decoder.cc:8929
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16(MachInst)
Definition: decoder.cc:9915
gem5::VegaISA::Inst_VOP3__V_INTERP_P1_F32
Definition: instructions.hh:29955
gem5::VegaISA::Inst_VOP1__V_NOP
Definition: instructions.hh:8033
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_SUB_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_SUB_I16(MachInst)
Definition: decoder.cc:12878
gem5::VegaISA::Inst_VOPC__V_CMP_T_I64
Definition: instructions.hh:16275
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_LZ
Definition: instructions.hh:40819
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F16(MachInst)
Definition: decoder.cc:4844
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U64
Definition: instructions.hh:17023
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B8
GPUStaticInst * decode_OP_DS__DS_WRITE_B8(MachInst)
Definition: decoder.cc:7367
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LDEXP_F16
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F16(MachInst)
Definition: decoder.cc:6104
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:8599
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_B32
GPUStaticInst * decode_OP_DS__DS_READ_B32(MachInst)
Definition: decoder.cc:7511
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_U32
GPUStaticInst * decode_OP_DS__DS_MAX_U32(MachInst)
Definition: decoder.cc:7276
gem5::VegaISA::Inst_VOP3__V_LOG_LEGACY_F32
Definition: instructions.hh:27943
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_L_O(MachInst)
Definition: decoder.cc:9196
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I64
Definition: instructions.hh:23449
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_F64
GPUStaticInst * decode_OP_DS__DS_MIN_F64(MachInst)
Definition: decoder.cc:7679
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SWAPPC_B64
GPUStaticInst * decode_OP_SOP1__S_SWAPPC_B64(MachInst)
Definition: decoder.cc:10722
gem5::VegaISA::Inst_VOP3__V_MED3_U32
Definition: instructions.hh:28839
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LE_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LE_U32(MachInst)
Definition: decoder.cc:10937
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_F32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_F32(MachInst)
Definition: decoder.cc:7487
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_DEC_X2
Definition: instructions.hh:37791
gem5::VegaISA::Inst_VOP2__V_MUL_F32
Definition: instructions.hh:6311
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O
Definition: instructions.hh:40351
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RSQ_F64
GPUStaticInst * decode_OP_VOP1__V_RSQ_F64(MachInst)
Definition: decoder.cc:11418
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD
Definition: instructions.hh:42245
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F16
Definition: instructions.hh:18349
gem5::VegaISA::Inst_SOP1__S_MOVRELD_B64
Definition: instructions.hh:3619
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F32(MachInst)
Definition: decoder.cc:4970
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16_HI(MachInst)
Definition: decoder.cc:10097
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F64
Definition: instructions.hh:13453
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U16
Definition: instructions.hh:21647
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_INC
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_INC(MachInst)
Definition: decoder.cc:8368
gem5::VegaISA::Inst_VOP3__V_RNDNE_F16
Definition: instructions.hh:27783
gem5::VegaISA::Inst_SOP1__S_FF1_I32_B64
Definition: instructions.hh:2725
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_INC
Definition: instructions.hh:37287
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U64(MachInst)
Definition: decoder.cc:5690
gem5::VegaISA::Inst_DS__DS_ADD_RTN_U64
Definition: instructions.hh:33487

Generated on Tue Feb 8 2022 11:46:42 for gem5 by doxygen 1.8.17