gem5  v21.2.1.0
•All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
remote_gdb.cc
Go to the documentation of this file.
1 /*
2  * Copyright 2015 LabWare
3  * Copyright 2014 Google, Inc.
4  * Copyright (c) 2007 The Hewlett-Packard Development Company
5  * All rights reserved.
6  *
7  * The license below extends only to copyright in the software and shall
8  * not be construed as granting a license to any other intellectual
9  * property including but not limited to intellectual property relating
10  * to a hardware implementation of the functionality of the software
11  * licensed hereunder. You may use the software subject to the license
12  * terms below provided that you ensure that this notice is replicated
13  * unmodified and in its entirety in all distributions of the software,
14  * modified or unmodified, in source code or in binary form.
15  *
16  * Redistribution and use in source and binary forms, with or without
17  * modification, are permitted provided that the following conditions are
18  * met: redistributions of source code must retain the above copyright
19  * notice, this list of conditions and the following disclaimer;
20  * redistributions in binary form must reproduce the above copyright
21  * notice, this list of conditions and the following disclaimer in the
22  * documentation and/or other materials provided with the distribution;
23  * neither the name of the copyright holders nor the names of its
24  * contributors may be used to endorse or promote products derived from
25  * this software without specific prior written permission.
26  *
27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38  */
39 
40 #include "arch/x86/remote_gdb.hh"
41 
42 #include <sys/signal.h>
43 #include <unistd.h>
44 
45 #include <string>
46 
47 #include "arch/x86/mmu.hh"
48 #include "arch/x86/pagetable_walker.hh"
49 #include "arch/x86/process.hh"
50 #include "arch/x86/regs/int.hh"
51 #include "arch/x86/regs/misc.hh"
52 #include "base/loader/object_file.hh"
53 #include "base/logging.hh"
54 #include "base/remote_gdb.hh"
55 #include "base/socket.hh"
56 #include "base/trace.hh"
57 #include "cpu/base.hh"
58 #include "cpu/thread_context.hh"
59 #include "debug/GDBAcc.hh"
60 #include "mem/page_table.hh"
61 #include "sim/full_system.hh"
62 #include "sim/workload.hh"
63 
64 namespace gem5
65 {
66 
67 using namespace X86ISA;
68 
69 RemoteGDB::RemoteGDB(System *_system, int _port) :
70  BaseRemoteGDB(_system, _port), regCache32(this), regCache64(this)
71 {}
72 
73 bool
74 RemoteGDB::acc(Addr va, size_t len)
75 {
76  if (FullSystem) {
77  Walker *walker = dynamic_cast<MMU *>(
78  context()->getMMUPtr())->getDataWalker();
79  unsigned logBytes;
80  Fault fault = walker->startFunctional(context(), va, logBytes,
81  BaseMMU::Read);
82  if (fault != NoFault)
83  return false;
84 
85  Addr endVa = va + len - 1;
86  if ((va & ~mask(logBytes)) == (endVa & ~mask(logBytes)))
87  return true;
88 
89  fault = walker->startFunctional(context(), endVa, logBytes,
90  BaseMMU::Read);
91  return fault == NoFault;
92  } else {
93  return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
94  }
95 }
96 
97 BaseGdbRegCache*
98 RemoteGDB::gdbRegs()
99 {
100  // First, try to figure out which type of register cache to return based
101  // on the architecture reported by the workload.
102  if (system()->workload) {
103  auto arch = system()->workload->getArch();
104  if (arch == loader::X86_64) {
105  return &regCache64;
106  } else if (arch == loader::I386) {
107  return &regCache32;
108  } else if (arch != loader::UnknownArch) {
109  panic("Unrecognized workload arch %s.",
110  loader::archToString(arch));
111  }
112  }
113 
114  // If that didn't work, decide based on the current mode of the context.
115  HandyM5Reg m5reg = context()->readMiscRegNoEffect(MISCREG_M5_REG);
116  if (m5reg.submode == SixtyFourBitMode)
117  return &regCache64;
118  else
119  return &regCache32;
120 }
121 
122 
123 
124 void
125 RemoteGDB::AMD64GdbRegCache::getRegs(ThreadContext *context)
126 {
127  DPRINTF(GDBAcc, "getRegs in remotegdb \n");
128  r.rax = context->readIntReg(INTREG_RAX);
129  r.rbx = context->readIntReg(INTREG_RBX);
130  r.rcx = context->readIntReg(INTREG_RCX);
131  r.rdx = context->readIntReg(INTREG_RDX);
132  r.rsi = context->readIntReg(INTREG_RSI);
133  r.rdi = context->readIntReg(INTREG_RDI);
134  r.rbp = context->readIntReg(INTREG_RBP);
135  r.rsp = context->readIntReg(INTREG_RSP);
136  r.r8 = context->readIntReg(INTREG_R8);
137  r.r9 = context->readIntReg(INTREG_R9);
138  r.r10 = context->readIntReg(INTREG_R10);
139  r.r11 = context->readIntReg(INTREG_R11);
140  r.r12 = context->readIntReg(INTREG_R12);
141  r.r13 = context->readIntReg(INTREG_R13);
142  r.r14 = context->readIntReg(INTREG_R14);
143  r.r15 = context->readIntReg(INTREG_R15);
144  r.rip = context->pcState().instAddr();
145  r.eflags = context->readMiscRegNoEffect(MISCREG_RFLAGS);
146  r.cs = context->readMiscRegNoEffect(MISCREG_CS);
147  r.ss = context->readMiscRegNoEffect(MISCREG_SS);
148  r.ds = context->readMiscRegNoEffect(MISCREG_DS);
149  r.es = context->readMiscRegNoEffect(MISCREG_ES);
150  r.fs = context->readMiscRegNoEffect(MISCREG_FS);
151  r.gs = context->readMiscRegNoEffect(MISCREG_GS);
152 }
153 
154 void
155 RemoteGDB::X86GdbRegCache::getRegs(ThreadContext *context)
156 {
157  DPRINTF(GDBAcc, "getRegs in remotegdb \n");
158  r.eax = context->readIntReg(INTREG_RAX);
159  r.ecx = context->readIntReg(INTREG_RCX);
160  r.edx = context->readIntReg(INTREG_RDX);
161  r.ebx = context->readIntReg(INTREG_RBX);
162  r.esp = context->readIntReg(INTREG_RSP);
163  r.ebp = context->readIntReg(INTREG_RBP);
164  r.esi = context->readIntReg(INTREG_RSI);
165  r.edi = context->readIntReg(INTREG_RDI);
166  r.eip = context->pcState().instAddr();
167  r.eflags = context->readMiscRegNoEffect(MISCREG_RFLAGS);
168  r.cs = context->readMiscRegNoEffect(MISCREG_CS);
169  r.ss = context->readMiscRegNoEffect(MISCREG_SS);
170  r.ds = context->readMiscRegNoEffect(MISCREG_DS);
171  r.es = context->readMiscRegNoEffect(MISCREG_ES);
172  r.fs = context->readMiscRegNoEffect(MISCREG_FS);
173  r.gs = context->readMiscRegNoEffect(MISCREG_GS);
174 }
175 
176 void
177 RemoteGDB::AMD64GdbRegCache::setRegs(ThreadContext *context) const
178 {
179  DPRINTF(GDBAcc, "setRegs in remotegdb \n");
180  context->setIntReg(INTREG_RAX, r.rax);
181  context->setIntReg(INTREG_RBX, r.rbx);
182  context->setIntReg(INTREG_RCX, r.rcx);
183  context->setIntReg(INTREG_RDX, r.rdx);
184  context->setIntReg(INTREG_RSI, r.rsi);
185  context->setIntReg(INTREG_RDI, r.rdi);
186  context->setIntReg(INTREG_RBP, r.rbp);
187  context->setIntReg(INTREG_RSP, r.rsp);
188  context->setIntReg(INTREG_R8, r.r8);
189  context->setIntReg(INTREG_R9, r.r9);
190  context->setIntReg(INTREG_R10, r.r10);
191  context->setIntReg(INTREG_R11, r.r11);
192  context->setIntReg(INTREG_R12, r.r12);
193  context->setIntReg(INTREG_R13, r.r13);
194  context->setIntReg(INTREG_R14, r.r14);
195  context->setIntReg(INTREG_R15, r.r15);
196  context->pcState(r.rip);
197  context->setMiscReg(MISCREG_RFLAGS, r.eflags);
198  if (r.cs != context->readMiscRegNoEffect(MISCREG_CS))
199  warn("Remote gdb: Ignoring update to CS.\n");
200  if (r.ss != context->readMiscRegNoEffect(MISCREG_SS))
201  warn("Remote gdb: Ignoring update to SS.\n");
202  if (r.ds != context->readMiscRegNoEffect(MISCREG_DS))
203  warn("Remote gdb: Ignoring update to DS.\n");
204  if (r.es != context->readMiscRegNoEffect(MISCREG_ES))
205  warn("Remote gdb: Ignoring update to ES.\n");
206  if (r.fs != context->readMiscRegNoEffect(MISCREG_FS))
207  warn("Remote gdb: Ignoring update to FS.\n");
208  if (r.gs != context->readMiscRegNoEffect(MISCREG_GS))
209  warn("Remote gdb: Ignoring update to GS.\n");
210 }
211 
212 void
213 RemoteGDB::X86GdbRegCache::setRegs(ThreadContext *context) const
214 {
215  DPRINTF(GDBAcc, "setRegs in remotegdb \n");
216  context->setIntReg(INTREG_RAX, r.eax);
217  context->setIntReg(INTREG_RCX, r.ecx);
218  context->setIntReg(INTREG_RDX, r.edx);
219  context->setIntReg(INTREG_RBX, r.ebx);
220  context->setIntReg(INTREG_RSP, r.esp);
221  context->setIntReg(INTREG_RBP, r.ebp);
222  context->setIntReg(INTREG_RSI, r.esi);
223  context->setIntReg(INTREG_RDI, r.edi);
224  context->pcState(r.eip);
225  context->setMiscReg(MISCREG_RFLAGS, r.eflags);
226  if (r.cs != context->readMiscRegNoEffect(MISCREG_CS))
227  warn("Remote gdb: Ignoring update to CS.\n");
228  if (r.ss != context->readMiscRegNoEffect(MISCREG_SS))
229  warn("Remote gdb: Ignoring update to SS.\n");
230  if (r.ds != context->readMiscRegNoEffect(MISCREG_DS))
231  warn("Remote gdb: Ignoring update to DS.\n");
232  if (r.es != context->readMiscRegNoEffect(MISCREG_ES))
233  warn("Remote gdb: Ignoring update to ES.\n");
234  if (r.fs != context->readMiscRegNoEffect(MISCREG_FS))
235  warn("Remote gdb: Ignoring update to FS.\n");
236  if (r.gs != context->readMiscRegNoEffect(MISCREG_GS))
237  warn("Remote gdb: Ignoring update to GS.\n");
238 }
239 
240 } // namespace gem5
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::X86ISA::MISCREG_ES
@ MISCREG_ES
Definition: misc.hh:302
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::BaseMMU::Read
@ Read
Definition: mmu.hh:56
socket.hh
gem5::SparcISA::RemoteGDB::gdbRegs
BaseGdbRegCache * gdbRegs()
gem5::X86ISA::MISCREG_M5_REG
@ MISCREG_M5_REG
Definition: misc.hh:143
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ArmISA::len
Bitfield< 18, 16 > len
Definition: misc_types.hh:445
gem5::X86ISA::MISCREG_DS
@ MISCREG_DS
Definition: misc.hh:305
warn
#define warn(...)
Definition: logging.hh:246
gem5::X86ISA::RemoteGDB::RemoteGDB
RemoteGDB(System *system, int _port)
mmu.hh
remote_gdb.hh
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::loader::X86_64
@ X86_64
Definition: object_file.hh:56
pagetable_walker.hh
gem5::System::workload
Workload * workload
OS kernel.
Definition: system.hh:330
gem5::EmulationPageTable::lookup
const Entry * lookup(Addr vaddr)
Lookup function.
Definition: page_table.cc:133
workload.hh
gem5::SparcISA::RemoteGDB::acc
bool acc(Addr addr, size_t len)
gem5::X86ISA::SixtyFourBitMode
@ SixtyFourBitMode
Definition: types.hh:198
gem5::X86ISA::MISCREG_GS
@ MISCREG_GS
Definition: misc.hh:307
gem5::Workload::getArch
virtual loader::Arch getArch() const =0
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::SparcISA::RemoteGDB::regCache64
SPARC64GdbRegCache regCache64
Definition: remote_gdb.hh:108
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
int.hh
gem5::Process::pTable
EmulationPageTable * pTable
Definition: process.hh:185
gem5::SparcISA::RemoteGDB::regCache32
SPARCGdbRegCache regCache32
Definition: remote_gdb.hh:107
remote_gdb.hh
gem5::loader::archToString
const char * archToString(Arch arch)
Definition: object_file.cc:46
gem5::X86ISA::MISCREG_RFLAGS
@ MISCREG_RFLAGS
Definition: misc.hh:140
gem5::X86ISA::MISCREG_FS
@ MISCREG_FS
Definition: misc.hh:306
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::MISCREG_SS
@ MISCREG_SS
Definition: misc.hh:304
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:276
full_system.hh
gem5::X86ISA::MISCREG_CS
@ MISCREG_CS
Definition: misc.hh:303
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::loader::UnknownArch
@ UnknownArch
Definition: object_file.hh:52
process.hh
base.hh
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
logging.hh
gem5::loader::I386
@ I386
Definition: object_file.hh:57
gem5::BaseRemoteGDB::context
ThreadContext * context()
Definition: remote_gdb.hh:395
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::BaseRemoteGDB::system
System * system()
Definition: remote_gdb.hh:396
trace.hh
page_table.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
misc.hh
object_file.hh
thread_context.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
Generated on Tue Feb 8 2022 11:46:58 for gem5 by doxygen 1.8.17