gem5
v21.2.1.0
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#include <isa.hh>
Public Types | |
using | Params = X86ISAParams |
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typedef std::vector< RegClass > | RegClasses |
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typedef SimObjectParams | Params |
Public Member Functions | |
void | clear () |
PCStateBase * | newPCState (Addr new_inst_addr=0) const override |
ISA (const Params &p) | |
RegVal | readMiscRegNoEffect (int miscReg) const |
RegVal | readMiscReg (int miscReg) |
void | setMiscRegNoEffect (int miscReg, RegVal val) |
void | setMiscReg (int miscReg, RegVal val) |
RegId | flattenRegId (const RegId ®Id) const |
int | flattenIntIndex (int reg) const |
int | flattenFloatIndex (int reg) const |
int | flattenVecIndex (int reg) const |
int | flattenVecElemIndex (int reg) const |
int | flattenVecPredIndex (int reg) const |
int | flattenCCIndex (int reg) const |
int | flattenMiscIndex (int reg) const |
bool | inUserMode () const override |
void | copyRegsFrom (ThreadContext *src) override |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. More... | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. More... | |
void | setThreadContext (ThreadContext *_tc) override |
std::string | getVendorString () const |
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virtual void | takeOverFrom (ThreadContext *new_tc, ThreadContext *old_tc) |
virtual uint64_t | getExecutingAsid () const |
const RegClasses & | regClasses () const |
virtual void | handleLockedRead (const RequestPtr &req) |
virtual void | handleLockedRead (ExecContext *xc, const RequestPtr &req) |
virtual bool | handleLockedWrite (const RequestPtr &req, Addr cacheBlockMask) |
virtual bool | handleLockedWrite (ExecContext *xc, const RequestPtr &req, Addr cacheBlockMask) |
virtual void | handleLockedSnoop (PacketPtr pkt, Addr cacheBlockMask) |
virtual void | handleLockedSnoop (ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask) |
virtual void | handleLockedSnoopHit () |
virtual void | handleLockedSnoopHit (ExecContext *xc) |
virtual void | globalClearExclusive () |
virtual void | globalClearExclusive (ExecContext *xc) |
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const Params & | params () const |
SimObject (const Params &p) | |
virtual | ~SimObject () |
virtual void | init () |
init() is called after all C++ SimObjects have been created and all ports are connected. More... | |
virtual void | loadState (CheckpointIn &cp) |
loadState() is called on each SimObject when restoring from a checkpoint. More... | |
virtual void | initState () |
initState() is called on each SimObject when not restoring from a checkpoint. More... | |
virtual void | regProbePoints () |
Register probe points for this object. More... | |
virtual void | regProbeListeners () |
Register probe listeners for this object. More... | |
ProbeManager * | getProbeManager () |
Get the probe manager for this object. More... | |
virtual Port & | getPort (const std::string &if_name, PortID idx=InvalidPortID) |
Get a port with a given name and index. More... | |
virtual void | startup () |
startup() is the final initialization call before simulation. More... | |
DrainState | drain () override |
Provide a default implementation of the drain interface for objects that don't need draining. More... | |
virtual void | memWriteback () |
Write back dirty buffers to memory using functional writes. More... | |
virtual void | memInvalidate () |
Invalidate the contents of memory buffers. More... | |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. More... | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. More... | |
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EventQueue * | eventQueue () const |
void | schedule (Event &event, Tick when) |
void | deschedule (Event &event) |
void | reschedule (Event &event, Tick when, bool always=false) |
void | schedule (Event *event, Tick when) |
void | deschedule (Event *event) |
void | reschedule (Event *event, Tick when, bool always=false) |
void | wakeupEventQueue (Tick when=(Tick) -1) |
This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More... | |
void | setCurTick (Tick newVal) |
EventManager (EventManager &em) | |
Event manger manages events in the event queue. More... | |
EventManager (EventManager *em) | |
EventManager (EventQueue *eq) | |
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Serializable () | |
virtual | ~Serializable () |
void | serializeSection (CheckpointOut &cp, const char *name) const |
Serialize an object into a new section. More... | |
void | serializeSection (CheckpointOut &cp, const std::string &name) const |
void | unserializeSection (CheckpointIn &cp, const char *name) |
Unserialize an a child object. More... | |
void | unserializeSection (CheckpointIn &cp, const std::string &name) |
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DrainState | drainState () const |
Return the current drain state of an object. More... | |
virtual void | notifyFork () |
Notify a child process of a fork. More... | |
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Group (Group *parent, const char *name=nullptr) | |
Construct a new statistics group. More... | |
virtual | ~Group () |
virtual void | regStats () |
Callback to set stat parameters. More... | |
virtual void | resetStats () |
Callback to reset stats. More... | |
virtual void | preDumpStats () |
Callback before stats are dumped. More... | |
void | addStat (statistics::Info *info) |
Register a stat with this group. More... | |
const std::map< std::string, Group * > & | getStatGroups () const |
Get all child groups associated with this object. More... | |
const std::vector< Info * > & | getStats () const |
Get all stats associated with this object. More... | |
void | addStatGroup (const char *name, Group *block) |
Add a stat block as a child of this block. More... | |
const Info * | resolveStat (std::string name) const |
Resolve a stat by its name within this group. More... | |
void | mergeStatGroup (Group *block) |
Merge the contents (stats & children) of a block to this block. More... | |
Group ()=delete | |
Group (const Group &)=delete | |
Group & | operator= (const Group &)=delete |
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Named (const std::string &name_) | |
virtual | ~Named ()=default |
virtual std::string | name () const |
Private Member Functions | |
void | updateHandyM5Reg (Efer efer, CR0 cr0, SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags) |
Private Attributes | |
RegVal | regVal [NUM_MISCREGS] |
std::string | vendorString |
Additional Inherited Members | |
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static void | serializeAll (const std::string &cpt_dir) |
Create a checkpoint by serializing all SimObjects in the system. More... | |
static SimObject * | find (const char *name) |
Find the SimObject with the given name and return a pointer to it. More... | |
static void | setSimObjectResolver (SimObjectResolver *resolver) |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More... | |
static SimObjectResolver * | getSimObjectResolver () |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More... | |
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static const std::string & | currentSection () |
Gets the fully-qualified name of the active section. More... | |
static void | generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream) |
Generate a checkpoint file so that the serialization can be routed to it. More... | |
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SimObject (const Params &p) | |
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Drainable () | |
virtual | ~Drainable () |
virtual void | drainResume () |
Resume execution after a successful drain. More... | |
void | signalDrainDone () const |
Signal that an object is drained. More... | |
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ThreadContext * | tc = nullptr |
RegClasses | _regClasses |
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const SimObjectParams & | _params |
Cached copy of the object parameters. More... | |
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EventQueue * | eventq |
A pointer to this object's event queue. More... | |
using gem5::X86ISA::ISA::Params = X86ISAParams |
gem5::X86ISA::ISA::ISA | ( | const Params & | p | ) |
Definition at line 140 of file isa.cc.
References gem5::BaseISA::_regClasses, clear(), fatal_if, gem5::X86ISA::NUM_CCREGS, gem5::X86ISA::NUM_MISCREGS, gem5::X86ISA::NumFloatRegs, gem5::X86ISA::NumIntRegs, and vendorString.
void gem5::X86ISA::ISA::clear | ( | ) |
Definition at line 110 of file isa.cc.
References gem5::X86ISA::mask, gem5::X86ISA::MISCREG_APIC_BASE, gem5::X86ISA::MISCREG_CR0, gem5::X86ISA::MISCREG_DR6, gem5::X86ISA::MISCREG_DR7, gem5::X86ISA::MISCREG_MCG_CAP, gem5::X86ISA::MISCREG_MTRRCAP, gem5::X86ISA::MISCREG_PAT, gem5::X86ISA::MISCREG_SYSCFG, gem5::X86ISA::MISCREG_TOP_MEM, gem5::X86ISA::NUM_MISCREGS, and regVal.
Referenced by ISA().
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overridevirtual |
Implements gem5::BaseISA.
Definition at line 177 of file isa.cc.
References gem5::X86ISA::copyMiscRegs(), gem5::ArmISA::i, gem5::X86ISA::NUM_CCREGS, gem5::X86ISA::NumFloatRegs, gem5::X86ISA::NumIntRegs, gem5::ThreadContext::pcState(), gem5::ThreadContext::readCCRegFlat(), gem5::ThreadContext::readFloatRegFlat(), gem5::ThreadContext::readIntRegFlat(), gem5::ThreadContext::setCCRegFlat(), gem5::ThreadContext::setFloatRegFlat(), gem5::ThreadContext::setIntRegFlat(), and gem5::BaseISA::tc.
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inline |
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inline |
Definition at line 100 of file isa.hh.
References gem5::X86ISA::FLOATREG_STACK(), gem5::X86ISA::MISCREG_X87_TOP, gem5::X86ISA::NUM_FLOATREGS, gem5::X86ISA::reg, and regVal.
Referenced by flattenRegId().
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inline |
Definition at line 97 of file isa.hh.
References gem5::X86ISA::IntFoldBit, and gem5::X86ISA::reg.
Referenced by flattenRegId().
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inline |
Definition at line 80 of file isa.hh.
References gem5::CCRegClass, gem5::RegId::classValue(), flattenCCIndex(), flattenFloatIndex(), flattenIntIndex(), flattenMiscIndex(), gem5::FloatRegClass, gem5::RegId::index(), gem5::IntRegClass, and gem5::MiscRegClass.
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inline |
Definition at line 110 of file isa.hh.
References gem5::X86ISA::reg.
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inline |
Definition at line 109 of file isa.hh.
References gem5::X86ISA::reg.
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inline |
Definition at line 111 of file isa.hh.
References gem5::X86ISA::reg.
std::string gem5::X86ISA::ISA::getVendorString | ( | ) | const |
Definition at line 486 of file isa.cc.
References vendorString.
Referenced by gem5::X86ISA::doCpuid().
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inlineoverridevirtual |
Implements gem5::BaseISA.
Definition at line 116 of file isa.hh.
References gem5::X86ISA::MISCREG_M5_REG, and readMiscRegNoEffect().
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inlineoverridevirtual |
Implements gem5::BaseISA.
RegVal gem5::X86ISA::ISA::readMiscReg | ( | int | miscReg | ) |
Definition at line 204 of file isa.cc.
References gem5::X86ISA::base, gem5::ThreadContext::contextId(), gem5::ThreadContext::getCpuPtr(), gem5::insertBits(), gem5::X86ISA::MISCREG_APIC_BASE, gem5::X86ISA::MISCREG_FSW, gem5::X86ISA::MISCREG_TSC, gem5::X86ISA::MISCREG_X87_TOP, readMiscRegNoEffect(), regVal, and gem5::BaseISA::tc.
RegVal gem5::X86ISA::ISA::readMiscRegNoEffect | ( | int | miscReg | ) | const |
Definition at line 193 of file isa.cc.
References gem5::X86ISA::isValidMiscReg(), and regVal.
Referenced by inUserMode(), and readMiscReg().
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overridevirtual |
Serialize an object.
Output an object's state into the current checkpoint section.
cp | Checkpoint state |
Implements gem5::Serializable.
Definition at line 462 of file isa.cc.
References gem5::X86ISA::NUM_MISCREGS, regVal, and SERIALIZE_ARRAY.
void gem5::X86ISA::ISA::setMiscReg | ( | int | miscReg, |
RegVal | val | ||
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Definition at line 268 of file isa.cc.
References gem5::BaseMMU::flushAll(), gem5::ThreadContext::getCpuPtr(), gem5::ThreadContext::getMMUPtr(), gem5::X86ISA::MISCREG_CR0, gem5::X86ISA::MISCREG_CR2, gem5::X86ISA::MISCREG_CR3, gem5::X86ISA::MISCREG_CR4, gem5::X86ISA::MISCREG_CR8, gem5::X86ISA::MISCREG_CS_ATTR, gem5::X86ISA::MISCREG_CS_BASE, gem5::X86ISA::MISCREG_CS_EFF_BASE, gem5::X86ISA::MISCREG_DR0, gem5::X86ISA::MISCREG_DR1, gem5::X86ISA::MISCREG_DR2, gem5::X86ISA::MISCREG_DR3, gem5::X86ISA::MISCREG_DR4, gem5::X86ISA::MISCREG_DR5, gem5::X86ISA::MISCREG_DR6, gem5::X86ISA::MISCREG_DR7, gem5::X86ISA::MISCREG_DS_BASE, gem5::X86ISA::MISCREG_DS_EFF_BASE, gem5::X86ISA::MISCREG_EFER, gem5::X86ISA::MISCREG_ES_BASE, gem5::X86ISA::MISCREG_ES_EFF_BASE, gem5::X86ISA::MISCREG_FS_BASE, gem5::X86ISA::MISCREG_GS_BASE, gem5::X86ISA::MISCREG_HS_BASE, gem5::X86ISA::MISCREG_IDTR_BASE, gem5::X86ISA::MISCREG_M5_REG, gem5::X86ISA::MISCREG_RFLAGS, gem5::X86ISA::MISCREG_SEG_BASE_BASE, gem5::X86ISA::MISCREG_SEG_EFF_BASE(), gem5::X86ISA::MISCREG_SS_ATTR, gem5::X86ISA::MISCREG_SS_BASE, gem5::X86ISA::MISCREG_SS_EFF_BASE, gem5::X86ISA::MISCREG_TR_BASE, gem5::X86ISA::MISCREG_TSC, gem5::X86ISA::MISCREG_TSG_BASE, gem5::X86ISA::MISCREG_TSL_BASE, panic, regVal, setMiscRegNoEffect(), gem5::BaseISA::tc, updateHandyM5Reg(), and gem5::X86ISA::val.
void gem5::X86ISA::ISA::setMiscRegNoEffect | ( | int | miscReg, |
RegVal | val | ||
) |
Definition at line 226 of file isa.cc.
References gem5::X86ISA::isValidMiscReg(), gem5::X86ISA::mask, gem5::X86ISA::MISCREG_FCW, gem5::X86ISA::MISCREG_FIOFF, gem5::X86ISA::MISCREG_FISEG, gem5::X86ISA::MISCREG_FOOFF, gem5::X86ISA::MISCREG_FOP, gem5::X86ISA::MISCREG_FOSEG, gem5::X86ISA::MISCREG_FSW, gem5::X86ISA::MISCREG_FTW, gem5::X86ISA::MISCREG_M5_REG, gem5::X86ISA::MISCREG_MXCSR, gem5::X86ISA::MISCREG_X87_TOP, regVal, gem5::X86ISA::SixtyFourBitMode, and gem5::X86ISA::val.
Referenced by setMiscReg().
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overridevirtual |
Reimplemented from gem5::BaseISA.
Definition at line 479 of file isa.cc.
References gem5::InstDecoder::as(), gem5::ThreadContext::getDecoderPtr(), gem5::X86ISA::MISCREG_M5_REG, regVal, gem5::BaseISA::setThreadContext(), and gem5::BaseISA::tc.
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overridevirtual |
Unserialize an object.
Read an object's state from the current checkpoint section.
cp | Checkpoint state |
Implements gem5::Serializable.
Definition at line 468 of file isa.cc.
References gem5::X86ISA::MISCREG_CR0, gem5::X86ISA::MISCREG_CS_ATTR, gem5::X86ISA::MISCREG_EFER, gem5::X86ISA::MISCREG_RFLAGS, gem5::X86ISA::MISCREG_SS_ATTR, gem5::X86ISA::NUM_MISCREGS, regVal, UNSERIALIZE_ARRAY, and updateHandyM5Reg().
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private |
Definition at line 49 of file isa.cc.
References gem5::InstDecoder::as(), gem5::X86ISA::CompatabilityMode, gem5::ThreadContext::getDecoderPtr(), gem5::X86ISA::MISCREG_M5_REG, gem5::X86ISA::ProtectedMode, gem5::X86ISA::RealMode, regVal, gem5::X86ISA::SixtyFourBitMode, gem5::BaseISA::tc, and gem5::X86ISA::Virtual8086Mode.
Referenced by setMiscReg(), and unserialize().
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private |
Definition at line 54 of file isa.hh.
Referenced by clear(), flattenFloatIndex(), readMiscReg(), readMiscRegNoEffect(), serialize(), setMiscReg(), setMiscRegNoEffect(), setThreadContext(), unserialize(), and updateHandyM5Reg().
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private |
Definition at line 58 of file isa.hh.
Referenced by getVendorString(), and ISA().