arm_cpu.hh

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/*
 * Copyright (c) 2012 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ARCH_ARM_KVM_ARM_CPU_HH__
#define __ARCH_ARM_KVM_ARM_CPU_HH__
 
#include <set>
#include <vector>
 
#include "arch/arm/pcstate.hh"
#include "cpu/kvm/base.hh"
#include "params/ArmKvmCPU.hh"
 
namespace gem5
{
 
class ArmKvmCPU : public BaseKvmCPU
{
  public:
    ArmKvmCPU(const ArmKvmCPUParams &params);
    virtual ~ArmKvmCPU();
 
    void startup();
 
    void dump();
 
  protected:
    struct KvmIntRegInfo
    {
        const uint64_t id;
        const ArmISA::IntRegIndex idx;
        const char *name;
    };
 
    struct KvmCoreMiscRegInfo
    {
        const uint64_t id;
        const ArmISA::MiscRegIndex idx;
        const char *name;
    };
 
    typedef std::vector<uint64_t> RegIndexVector;
 
    Tick kvmRun(Tick ticks);
 
    void updateKvmState();
    void updateThreadContext();
    void
    stutterPC(PCStateBase &pc) const
    {
        pc.as<X86ISA::PCState>().setNPC(pc->instAddr());
    }
 
    const RegIndexVector &getRegList() const;
 
    void kvmArmVCpuInit(uint32_t target);
    void kvmArmVCpuInit(const struct kvm_vcpu_init &init);
 
    ArmISA::MiscRegIndex decodeCoProcReg(uint64_t id) const;
 
    ArmISA::MiscRegIndex decodeVFPCtrlReg(uint64_t id) const;
 
    bool isInvariantReg(uint64_t id);
 
    static KvmIntRegInfo kvmIntRegs[];
    static KvmCoreMiscRegInfo kvmCoreMiscRegs[];
 
  private:
    bool getRegList(struct kvm_reg_list &regs) const;
 
    void dumpKvmStateCore();
    void dumpKvmStateMisc();
    void dumpKvmStateCoProc(uint64_t id);
    void dumpKvmStateVFP(uint64_t id);
 
    void updateKvmStateCore();
    void updateKvmStateMisc();
    void updateKvmStateCoProc(uint64_t id, bool show_warnings);
    void updateKvmStateVFP(uint64_t id, bool show_warnings);
 
    void updateTCStateCore();
    void updateTCStateMisc();
    void updateTCStateCoProc(uint64_t id, bool show_warnings);
    void updateTCStateVFP(uint64_t id, bool show_warnings);
 
 
    bool irqAsserted;
    bool fiqAsserted;
 
    mutable RegIndexVector _regIndexList;
 
    static const std::set<uint64_t> invariant_regs;
};
 
} // namespace gem5
 
#endif // __ARCH_ARM_KVM_ARM_CPU_HH__