TLB Invalidate by Intermediate Physical Address. More...

#include <tlbi_op.hh>

Inheritance diagram for gem5::ArmISA::TLBIIPA:

Public Member Functions
	TLBIIPA (ExceptionLevel _targetEL, bool _secure, Addr _addr)

void	operator() (ThreadContext *tc) override

bool	stage1Flush () const override
	Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class. More...

TLBIMVAA	makeStage2 () const
	TLBIIPA is basically a TLBIMVAA for stage2 TLBs. More...

Public Member Functions inherited from gem5::ArmISA::TLBIOp
	TLBIOp (ExceptionLevel _targetEL, bool _secure)

virtual	~TLBIOp ()

void	broadcast (ThreadContext *tc)
	Broadcast the TLB Invalidate operation to all TLBs in the Arm system. More...

virtual bool	stage2Flush () const
	Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class. More...

Public Attributes
Addr	addr

Public Attributes inherited from gem5::ArmISA::TLBIOp
bool	secureLookup

ExceptionLevel	targetEL

Detailed Description

TLB Invalidate by Intermediate Physical Address.

Definition at line 341 of file tlbi_op.hh.

Constructor & Destructor Documentation

◆ TLBIIPA()

gem5::ArmISA::TLBIIPA::TLBIIPA	(	ExceptionLevel	_targetEL,
		bool	_secure,
		Addr	_addr
	)

inline

Definition at line 344 of file tlbi_op.hh.

Member Function Documentation

◆ makeStage2()

TLBIMVAA gem5::ArmISA::TLBIIPA::makeStage2 ( ) const

inline

TLBIIPA is basically a TLBIMVAA for stage2 TLBs.

Definition at line 358 of file tlbi_op.hh.

References addr, gem5::ArmISA::EL1, and gem5::ArmISA::TLBIOp::secureLookup.

Referenced by operator()().

◆ operator()()

void gem5::ArmISA::TLBIIPA::operator() ( ThreadContext * tc )

overridevirtual

Reimplemented from gem5::ArmISA::TLBIOp.

Definition at line 187 of file tlbi_op.cc.

References gem5::ArmISA::MMU::flushStage2(), gem5::ThreadContext::getCheckerCpuPtr(), gem5::ArmISA::getMMUPtr(), and makeStage2().

◆ stage1Flush()

bool gem5::ArmISA::TLBIIPA::stage1Flush ( ) const

inlineoverridevirtual

Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class.

Reimplemented from gem5::ArmISA::TLBIOp.

Definition at line 351 of file tlbi_op.hh.

Member Data Documentation

◆ addr

Addr gem5::ArmISA::TLBIIPA::addr

Definition at line 363 of file tlbi_op.hh.

Referenced by makeStage2().

The documentation for this class was generated from the following files:

arch/arm/tlbi_op.hh
arch/arm/tlbi_op.cc

Public Member Functions

Public Attributes