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gem5
v21.2.1.1
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gem5
v21.2.1.1
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This is the complete list of members for gem5::DummyChecker, including all inherited members.
| amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override | gem5::CheckerCPU | inline |
| gem5::ExecContext::amoMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) | gem5::ExecContext | inlinevirtual |
| armMonitor(Addr address) override | gem5::CheckerCPU | inlinevirtual |
| changedPC | gem5::CheckerCPU | |
| CheckerCPU(const Params &p) | gem5::CheckerCPU | |
| checkFlags(const RequestPtr &unverified_req, Addr vAddr, Addr pAddr, int flags) | gem5::CheckerCPU | |
| curMacroStaticInst | gem5::CheckerCPU | protected |
| curStaticInst | gem5::CheckerCPU | protected |
| dcachePort | gem5::CheckerCPU | protected |
| demapPage(Addr vaddr, uint64_t asn) override | gem5::CheckerCPU | inlinevirtual |
| DummyChecker(const Params &p) | gem5::DummyChecker | inline |
| dumpAndExit() | gem5::CheckerCPU | |
| exitOnError | gem5::CheckerCPU | |
| genMemFragmentRequest(Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) const | gem5::CheckerCPU | |
| getAddrMonitor() override | gem5::CheckerCPU | inlinevirtual |
| getDataPort() override | gem5::CheckerCPU | inline |
| getHtmTransactionalDepth() const override | gem5::CheckerCPU | inlinevirtual |
| getHtmTransactionUid() const override | gem5::CheckerCPU | inlinevirtual |
| getInstPort() override | gem5::CheckerCPU | inline |
| getMMUPtr() | gem5::CheckerCPU | inline |
| getWritableVecPredRegOperand(const StaticInst *si, int idx) override | gem5::CheckerCPU | inlinevirtual |
| getWritableVecRegOperand(const StaticInst *si, int idx) override | gem5::CheckerCPU | inlinevirtual |
| handleError() | gem5::CheckerCPU | inline |
| icachePort | gem5::CheckerCPU | protected |
| inHtmTransactionalState() const override | gem5::CheckerCPU | inlinevirtual |
| init() override | gem5::CheckerCPU | |
| initiateHtmCmd(Request::Flags flags) override | gem5::CheckerCPU | inlinevirtual |
| initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) | gem5::ExecContext | inlinevirtual |
| initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) | gem5::ExecContext | inlinevirtual |
| miscRegIdxs | gem5::CheckerCPU | protected |
| mmu | gem5::CheckerCPU | protected |
| mwait(PacketPtr pkt) override | gem5::CheckerCPU | inlinevirtual |
| mwaitAtomic(ThreadContext *tc) override | gem5::CheckerCPU | inlinevirtual |
| newHtmTransactionUid() const override | gem5::CheckerCPU | inlinevirtual |
| newPCState | gem5::CheckerCPU | |
| numInst | gem5::CheckerCPU | protected |
| numLoad | gem5::CheckerCPU | |
| PARAMS(CheckerCPU) | gem5::CheckerCPU | |
| pcState() const override | gem5::CheckerCPU | inlinevirtual |
| pcState(const PCStateBase &val) override | gem5::CheckerCPU | inlinevirtual |
| readCCRegOperand(const StaticInst *si, int idx) override | gem5::CheckerCPU | inlinevirtual |
| readFloatRegOperandBits(const StaticInst *si, int idx) override | gem5::CheckerCPU | inlinevirtual |
| readIntRegOperand(const StaticInst *si, int idx) override | gem5::CheckerCPU | inlinevirtual |
| readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override | gem5::CheckerCPU | |
| gem5::ExecContext::readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) | gem5::ExecContext | inlinevirtual |
| readMemAccPredicate() const override | gem5::CheckerCPU | inlinevirtual |
| readMiscReg(int misc_reg) override | gem5::CheckerCPU | inlinevirtual |
| readMiscRegNoEffect(int misc_reg) const | gem5::CheckerCPU | inline |
| readMiscRegOperand(const StaticInst *si, int idx) override | gem5::CheckerCPU | inlinevirtual |
| readPredicate() const override | gem5::CheckerCPU | inlinevirtual |
| readStCondFailures() const override | gem5::CheckerCPU | inlinevirtual |
| readVecElemOperand(const StaticInst *si, int idx) const override | gem5::CheckerCPU | inlinevirtual |
| readVecPredRegOperand(const StaticInst *si, int idx) const override | gem5::CheckerCPU | inlinevirtual |
| readVecRegOperand(const StaticInst *si, int idx) const override | gem5::CheckerCPU | inlinevirtual |
| recordPCChange(const PCStateBase &val) | gem5::CheckerCPU | inline |
| requestorId | gem5::CheckerCPU | protected |
| result | gem5::CheckerCPU | protected |
| serialize(CheckpointOut &cp) const override | gem5::CheckerCPU | |
| setCCRegOperand(const StaticInst *si, int idx, RegVal val) override | gem5::CheckerCPU | inlinevirtual |
| setDcachePort(RequestPort *dcache_port) | gem5::CheckerCPU | |
| setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override | gem5::CheckerCPU | inlinevirtual |
| setIcachePort(RequestPort *icache_port) | gem5::CheckerCPU | |
| setIntRegOperand(const StaticInst *si, int idx, RegVal val) override | gem5::CheckerCPU | inlinevirtual |
| setMemAccPredicate(bool val) override | gem5::CheckerCPU | inlinevirtual |
| setMiscReg(int misc_reg, RegVal val) override | gem5::CheckerCPU | inlinevirtual |
| setMiscRegNoEffect(int misc_reg, RegVal val) | gem5::CheckerCPU | inline |
| setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override | gem5::CheckerCPU | inlinevirtual |
| setPredicate(bool val) override | gem5::CheckerCPU | inlinevirtual |
| setStCondFailures(unsigned int sc_failures) override | gem5::CheckerCPU | inlinevirtual |
| setSystem(System *system) | gem5::CheckerCPU | |
| setVecElemOperand(const StaticInst *si, int idx, RegVal val) override | gem5::CheckerCPU | inlinevirtual |
| setVecPredRegOperand(const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override | gem5::CheckerCPU | inlinevirtual |
| setVecRegOperand(const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override | gem5::CheckerCPU | inlinevirtual |
| startNumInst | gem5::CheckerCPU | protected |
| startNumLoad | gem5::CheckerCPU | |
| systemPtr | gem5::CheckerCPU | protected |
| tc | gem5::CheckerCPU | protected |
| tcBase() const override | gem5::CheckerCPU | inlinevirtual |
| thread | gem5::CheckerCPU | |
| threadBase() | gem5::CheckerCPU | inline |
| totalInsts() const override | gem5::CheckerCPU | inlinevirtual |
| totalOps() const override | gem5::CheckerCPU | inlinevirtual |
| unserialize(CheckpointIn &cp) override | gem5::CheckerCPU | |
| unverifiedMemData | gem5::CheckerCPU | |
| unverifiedReq | gem5::CheckerCPU | |
| unverifiedResult | gem5::CheckerCPU | |
| updateOnError | gem5::CheckerCPU | |
| wakeup(ThreadID tid) override | gem5::CheckerCPU | inline |
| warnOnlyOnLoadError | gem5::CheckerCPU | |
| willChangePC | gem5::CheckerCPU | |
| workload | gem5::CheckerCPU | protected |
| writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override | gem5::CheckerCPU | |
| gem5::ExecContext::writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable)=0 | gem5::ExecContext | pure virtual |
| youngestSN | gem5::CheckerCPU | |
| zeroReg | gem5::CheckerCPU | protected |
| ~CheckerCPU() | gem5::CheckerCPU | virtual |