The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate the state of the CPU model. More...

#include <exec_context.hh>

Inheritance diagram for gem5::ExecContext:

Public Member Functions
virtual ThreadContext *	tcBase () const =0
	Returns a pointer to the ThreadContext. More...

Integer Register Interfaces
virtual RegVal	readIntRegOperand (const StaticInst *si, int idx)=0
	Reads an integer register. More...

virtual void	setIntRegOperand (const StaticInst *si, int idx, RegVal val)=0
	Sets an integer register to a value. More...

Floating Point Register Interfaces
virtual RegVal	readFloatRegOperandBits (const StaticInst *si, int idx)=0
	Reads a floating point register in its binary format, instead of by value. More...

virtual void	setFloatRegOperandBits (const StaticInst *si, int idx, RegVal val)=0
	Sets the bits of a floating point register of single width to a binary value. More...


virtual const TheISA::VecRegContainer &	readVecRegOperand (const StaticInst *si, int idx) const =0
	Vector Register Interfaces. More...

virtual TheISA::VecRegContainer &	getWritableVecRegOperand (const StaticInst *si, int idx)=0
	Gets destination vector register operand for modification. More...

virtual void	setVecRegOperand (const StaticInst *si, int idx, const TheISA::VecRegContainer &val)=0
	Sets a destination vector register operand to a value. More...


virtual RegVal	readVecElemOperand (const StaticInst *si, int idx) const =0
	Vector Elem Interfaces. More...

virtual void	setVecElemOperand (const StaticInst *si, int idx, RegVal val)=0
	Sets a vector register to a value. More...


virtual const TheISA::VecPredRegContainer &	readVecPredRegOperand (const StaticInst *si, int idx) const =0
	Predicate registers interface. More...

virtual TheISA::VecPredRegContainer &	getWritableVecPredRegOperand (const StaticInst *si, int idx)=0
	Gets destination predicate register operand for modification. More...

virtual void	setVecPredRegOperand (const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val)=0
	Sets a destination predicate register operand to a value. More...

Condition Code Registers
virtual RegVal	readCCRegOperand (const StaticInst *si, int idx)=0

virtual void	setCCRegOperand (const StaticInst *si, int idx, RegVal val)=0

Misc Register Interfaces
virtual RegVal	readMiscRegOperand (const StaticInst *si, int idx)=0

virtual void	setMiscRegOperand (const StaticInst *si, int idx, RegVal val)=0

virtual RegVal	readMiscReg (int misc_reg)=0
	Reads a miscellaneous register, handling any architectural side effects due to reading that register. More...

virtual void	setMiscReg (int misc_reg, RegVal val)=0
	Sets a miscellaneous register, handling any architectural side effects due to writing that register. More...

PC Control
virtual const PCStateBase &	pcState () const =0

virtual void	pcState (const PCStateBase &val)=0

Memory Interface
virtual Fault	readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
	Perform an atomic memory read operation. More...

virtual Fault	initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
	Initiate a timing memory read operation. More...

virtual Fault	initiateHtmCmd (Request::Flags flags)=0
	Initiate an HTM command, e.g. More...

virtual Fault	writeMem (uint8_t data, unsigned int size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable)=0
	For atomic-mode contexts, perform an atomic memory write operation. More...

virtual Fault	amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
	For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More...

virtual Fault	initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
	For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More...

virtual void	setStCondFailures (unsigned int sc_failures)=0
	Sets the number of consecutive store conditional failures. More...

virtual unsigned int	readStCondFailures () const =0
	Returns the number of consecutive store conditional failures. More...

ARM-Specific Interfaces
virtual bool	readPredicate () const =0

virtual void	setPredicate (bool val)=0

virtual bool	readMemAccPredicate () const =0

virtual void	setMemAccPredicate (bool val)=0

virtual uint64_t	newHtmTransactionUid () const =0

virtual uint64_t	getHtmTransactionUid () const =0

virtual bool	inHtmTransactionalState () const =0

virtual uint64_t	getHtmTransactionalDepth () const =0

X86-Specific Interfaces
virtual void	demapPage (Addr vaddr, uint64_t asn)=0
	Invalidate a page in the DTLB and ITLB. More...

virtual void	armMonitor (Addr address)=0

virtual bool	mwait (PacketPtr pkt)=0

virtual void	mwaitAtomic (ThreadContext *tc)=0

virtual AddressMonitor *	getAddrMonitor ()=0

Detailed Description

The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate the state of the CPU model.

Register accessor methods in this class typically provide the index of the instruction's operand (e.g., 0 or 1), not the architectural register index, to simplify the implementation of register renaming. The architectural register index can be found by indexing into the instruction's own operand index table.

Note: The methods in this class typically take a raw pointer to the StaticInst is provided instead of a ref-counted StaticInstPtr to reduce overhead as an argument. This is fine as long as the implementation doesn't copy the pointer into any long-term storage (which is pretty hard to imagine they would have reason to do).

Definition at line 73 of file exec_context.hh.

Member Function Documentation

◆ amoMem()

virtual Fault gem5::ExecContext::amoMem	(	Addr	addr,
		uint8_t *	data,
		unsigned int	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op
	)

inlinevirtual

For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)

Reimplemented in gem5::SimpleExecContext.

Definition at line 238 of file exec_context.hh.

References panic.

◆ armMonitor()

virtual void gem5::ExecContext::armMonitor ( Addr address )

pure virtual

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ demapPage()

virtual void gem5::ExecContext::demapPage	(	Addr	vaddr,
		uint64_t	asn
	)

pure virtual

Invalidate a page in the DTLB and ITLB.

Implemented in gem5::SimpleExecContext, gem5::CheckerCPU, gem5::o3::DynInst, and gem5::minor::ExecContext.

◆ getAddrMonitor()

virtual AddressMonitor* gem5::ExecContext::getAddrMonitor ( )

pure virtual

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ getHtmTransactionalDepth()

virtual uint64_t gem5::ExecContext::getHtmTransactionalDepth ( ) const

pure virtual

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ getHtmTransactionUid()

virtual uint64_t gem5::ExecContext::getHtmTransactionUid ( ) const

pure virtual

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ getWritableVecPredRegOperand()

virtual TheISA::VecPredRegContainer& gem5::ExecContext::getWritableVecPredRegOperand	(	const StaticInst *	si,
		int	idx
	)

pure virtual

Gets destination predicate register operand for modification.

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ getWritableVecRegOperand()

virtual TheISA::VecRegContainer& gem5::ExecContext::getWritableVecRegOperand	(	const StaticInst *	si,
		int	idx
	)

pure virtual

Gets destination vector register operand for modification.

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ inHtmTransactionalState()

virtual bool gem5::ExecContext::inHtmTransactionalState ( ) const

pure virtual

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ initiateHtmCmd()

virtual Fault gem5::ExecContext::initiateHtmCmd ( Request::Flags flags )

pure virtual

Initiate an HTM command, e.g.

tell Ruby we're starting/stopping a transaction

Implemented in gem5::SimpleExecContext, gem5::o3::DynInst, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ initiateMemAMO()

virtual Fault gem5::ExecContext::initiateMemAMO	(	Addr	addr,
		unsigned int	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op
	)

inlinevirtual

For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)

Reimplemented in gem5::SimpleExecContext, and gem5::minor::ExecContext.

Definition at line 249 of file exec_context.hh.

References panic.

◆ initiateMemRead()

virtual Fault gem5::ExecContext::initiateMemRead	(	Addr	addr,
		unsigned int	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable
	)

inlinevirtual

Initiate a timing memory read operation.

Must be overridden for exec contexts that support timing memory mode. Not pure virtual since exec contexts that only support atomic memory mode need not override (though in that case this function should never be called).

Reimplemented in gem5::SimpleExecContext, and gem5::minor::ExecContext.

Definition at line 214 of file exec_context.hh.

References panic.

Referenced by gem5::X86ISA::initiateMemRead().

◆ mwait()

virtual bool gem5::ExecContext::mwait ( PacketPtr pkt )

pure virtual

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ mwaitAtomic()

virtual void gem5::ExecContext::mwaitAtomic ( ThreadContext * tc )

pure virtual

Implemented in gem5::SimpleExecContext, gem5::CheckerCPU, gem5::minor::ExecContext, and gem5::o3::DynInst.

◆ newHtmTransactionUid()

virtual uint64_t gem5::ExecContext::newHtmTransactionUid ( ) const

pure virtual

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ pcState() [1/2]

virtual const PCStateBase& gem5::ExecContext::pcState ( ) const

pure virtual

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

Referenced by gem5::DecoderFaultInst::execute(), gem5::DebugStep::execute(), gem5::ArmISA::ArmStaticInst::readPC(), gem5::ArmISA::ArmStaticInst::setAIWNextPC(), gem5::ArmISA::ArmStaticInst::setIWNextPC(), and gem5::ArmISA::ArmStaticInst::setNextPC().

◆ pcState() [2/2]

virtual void gem5::ExecContext::pcState ( const PCStateBase & val )

pure virtual

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ readCCRegOperand()

virtual RegVal gem5::ExecContext::readCCRegOperand	(	const StaticInst *	si,
		int	idx
	)

pure virtual

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::minor::ExecContext, and gem5::CheckerCPU.

◆ readFloatRegOperandBits()

virtual RegVal gem5::ExecContext::readFloatRegOperandBits	(	const StaticInst *	si,
		int	idx
	)

pure virtual

Reads a floating point register in its binary format, instead of by value.

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ readIntRegOperand()

virtual RegVal gem5::ExecContext::readIntRegOperand	(	const StaticInst *	si,
		int	idx
	)

pure virtual

Reads an integer register.

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ readMem()

virtual Fault gem5::ExecContext::readMem	(	Addr	addr,
		uint8_t *	data,
		unsigned int	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable
	)

inlinevirtual

Perform an atomic memory read operation.

Must be overridden for exec contexts that support atomic memory mode. Not pure virtual since exec contexts that only support timing memory mode need not override (though in that case this function should never be called).

Reimplemented in gem5::SimpleExecContext.

Definition at line 200 of file exec_context.hh.

References panic.

Referenced by gem5::X86ISA::readMemAtomic(), and gem5::X86ISA::readPackedMemAtomic().

◆ readMemAccPredicate()

virtual bool gem5::ExecContext::readMemAccPredicate ( ) const

pure virtual

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ readMiscReg()

virtual RegVal gem5::ExecContext::readMiscReg ( int misc_reg )

pure virtual

Reads a miscellaneous register, handling any architectural side effects due to reading that register.

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

Referenced by gem5::ArmISA::ISA::handleLockedSnoopHit().

◆ readMiscRegOperand()

virtual RegVal gem5::ExecContext::readMiscRegOperand	(	const StaticInst *	si,
		int	idx
	)

pure virtual

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ readPredicate()

virtual bool gem5::ExecContext::readPredicate ( ) const

pure virtual

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ readStCondFailures()

virtual unsigned int gem5::ExecContext::readStCondFailures ( ) const

pure virtual

Returns the number of consecutive store conditional failures.

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ readVecElemOperand()

virtual RegVal gem5::ExecContext::readVecElemOperand	(	const StaticInst *	si,
		int	idx
	)		const

pure virtual

Vector Elem Interfaces.

Reads an element of a vector register.

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ readVecPredRegOperand()

virtual const TheISA::VecPredRegContainer& gem5::ExecContext::readVecPredRegOperand	(	const StaticInst *	si,
		int	idx
	)		const

pure virtual

Predicate registers interface.

Reads source predicate register operand.

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ readVecRegOperand()

virtual const TheISA::VecRegContainer& gem5::ExecContext::readVecRegOperand	(	const StaticInst *	si,
		int	idx
	)		const

pure virtual

Vector Register Interfaces.

Reads source vector register operand.

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ setCCRegOperand()

virtual void gem5::ExecContext::setCCRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

pure virtual

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::minor::ExecContext, and gem5::CheckerCPU.

◆ setFloatRegOperandBits()

virtual void gem5::ExecContext::setFloatRegOperandBits	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

pure virtual

Sets the bits of a floating point register of single width to a binary value.

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ setIntRegOperand()

virtual void gem5::ExecContext::setIntRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

pure virtual

Sets an integer register to a value.

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ setMemAccPredicate()

virtual void gem5::ExecContext::setMemAccPredicate ( bool val )

pure virtual

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ setMiscReg()

virtual void gem5::ExecContext::setMiscReg	(	int	misc_reg,
		RegVal	val
	)

pure virtual

Sets a miscellaneous register, handling any architectural side effects due to writing that register.

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

Referenced by gem5::ArmISA::ISA::globalClearExclusive(), gem5::ArmISA::ISA::handleLockedRead(), and gem5::ArmISA::ISA::handleLockedSnoopHit().

◆ setMiscRegOperand()

virtual void gem5::ExecContext::setMiscRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

pure virtual

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ setPredicate()

virtual void gem5::ExecContext::setPredicate ( bool val )

pure virtual

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ setStCondFailures()

virtual void gem5::ExecContext::setStCondFailures ( unsigned int sc_failures )

pure virtual

Sets the number of consecutive store conditional failures.

Implemented in gem5::minor::ExecContext, gem5::o3::DynInst, gem5::SimpleExecContext, and gem5::CheckerCPU.

◆ setVecElemOperand()

virtual void gem5::ExecContext::setVecElemOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

pure virtual

Sets a vector register to a value.

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ setVecPredRegOperand()

virtual void gem5::ExecContext::setVecPredRegOperand	(	const StaticInst *	si,
		int	idx,
		const TheISA::VecPredRegContainer &	val
	)

pure virtual

Sets a destination predicate register operand to a value.

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ setVecRegOperand()

virtual void gem5::ExecContext::setVecRegOperand	(	const StaticInst *	si,
		int	idx,
		const TheISA::VecRegContainer &	val
	)

pure virtual

Sets a destination vector register operand to a value.

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

◆ tcBase()

virtual ThreadContext* gem5::ExecContext::tcBase ( ) const

pure virtual

Returns a pointer to the ThreadContext.

Implemented in gem5::o3::DynInst, gem5::SimpleExecContext, gem5::CheckerCPU, and gem5::minor::ExecContext.

Referenced by gem5::X86ISA::MicroHalt::execute(), gem5::DebugStep::execute(), gem5::MiscRegImplDefined64::execute(), gem5::McrMrcMiscInst::execute(), gem5::McrMrcImplDefined::execute(), gem5::ArmISA::ISA::globalClearExclusive(), gem5::ArmISA::ISA::handleLockedRead(), gem5::ArmISA::ISA::handleLockedSnoop(), gem5::ArmISA::ISA::handleLockedSnoopHit(), gem5::ArmISA::ISA::handleLockedWrite(), gem5::MipsISA::readRegOtherThread(), gem5::MipsISA::setRegOtherThread(), and gem5::ArmISA::ArmStaticInst::softwareBreakpoint32().

◆ writeMem()

virtual Fault gem5::ExecContext::writeMem	(	uint8_t *	data,
		unsigned int	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		const std::vector< bool > &	byte_enable
	)

pure virtual

For atomic-mode contexts, perform an atomic memory write operation.

For timing-mode contexts, initiate a timing memory write operation.

Implemented in gem5::SimpleExecContext, and gem5::minor::ExecContext.

Referenced by gem5::X86ISA::writeMemAtomic(), gem5::X86ISA::writeMemTiming(), and gem5::X86ISA::writePackedMem().

The documentation for this class was generated from the following file:

cpu/exec_context.hh

Public Member Functions

Detailed Description

Member Function Documentation

◆ amoMem()

◆ armMonitor()

◆ demapPage()

◆ getAddrMonitor()

◆ getHtmTransactionalDepth()

◆ getHtmTransactionUid()

◆ getWritableVecPredRegOperand()

◆ getWritableVecRegOperand()

◆ inHtmTransactionalState()

◆ initiateHtmCmd()

◆ initiateMemAMO()

◆ initiateMemRead()

◆ mwait()

◆ mwaitAtomic()

◆ newHtmTransactionUid()

◆ pcState() [1/2]

◆ pcState() [2/2]

◆ readCCRegOperand()

◆ readFloatRegOperandBits()

◆ readIntRegOperand()

◆ readMem()

◆ readMemAccPredicate()

◆ readMiscReg()

◆ readMiscRegOperand()

◆ readPredicate()

◆ readStCondFailures()

◆ readVecElemOperand()

◆ readVecPredRegOperand()

◆ readVecRegOperand()

◆ setCCRegOperand()

◆ setFloatRegOperandBits()

◆ setIntRegOperand()

◆ setMemAccPredicate()

◆ setMiscReg()

◆ setMiscRegOperand()

◆ setPredicate()

◆ setStCondFailures()

◆ setVecElemOperand()

◆ setVecPredRegOperand()

◆ setVecRegOperand()

◆ tcBase()

◆ writeMem()