tlb.hh

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#ifndef __ARCH_ARM_TLB_HH__
#define __ARCH_ARM_TLB_HH__
 
 
#include "arch/arm/faults.hh"
#include "arch/arm/pagetable.hh"
#include "arch/arm/utility.hh"
#include "arch/generic/tlb.hh"
#include "base/statistics.hh"
#include "enums/TypeTLB.hh"
#include "mem/request.hh"
#include "params/ArmTLB.hh"
#include "sim/probe/pmu.hh"
 
namespace gem5
{
 
class ThreadContext;
 
namespace ArmISA {
 
class TableWalker;
class TLB;
 
class TLBIALL;
class ITLBIALL;
class DTLBIALL;
class TLBIALLEL;
class TLBIVMALL;
class TLBIALLN;
class TLBIMVA;
class ITLBIMVA;
class DTLBIMVA;
class TLBIASID;
class ITLBIASID;
class DTLBIASID;
class TLBIMVAA;
 
class TlbTestInterface
{
  public:
    TlbTestInterface() {}
    virtual ~TlbTestInterface() {}
 
    virtual Fault translationCheck(const RequestPtr &req, bool is_priv,
                                   BaseMMU::Mode mode,
                                   TlbEntry::DomainType domain) = 0;
 
    virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure,
                            Addr is_priv, BaseMMU::Mode mode,
                            TlbEntry::DomainType domain,
                            enums::ArmLookupLevel lookup_level) = 0;
};
 
class TLB : public BaseTLB
{
  protected:
    TlbEntry* table;
 
    int size;
 
    bool isStage2;
 
    std::unordered_map<enums::ArmLookupLevel, bool> partialLevels;
 
    bool _walkCache;
 
    TableWalker *tableWalker;
 
    struct TlbStats : public statistics::Group
    {
        TlbStats(TLB &parent);
 
        const TLB &tlb;
 
        // Access Stats
        mutable statistics::Scalar partialHits;
        mutable statistics::Scalar instHits;
        mutable statistics::Scalar instMisses;
        mutable statistics::Scalar readHits;
        mutable statistics::Scalar readMisses;
        mutable statistics::Scalar writeHits;
        mutable statistics::Scalar writeMisses;
        mutable statistics::Scalar inserts;
        mutable statistics::Scalar flushTlb;
        mutable statistics::Scalar flushTlbMva;
        mutable statistics::Scalar flushTlbMvaAsid;
        mutable statistics::Scalar flushTlbAsid;
        mutable statistics::Scalar flushedEntries;
 
        statistics::Formula readAccesses;
        statistics::Formula writeAccesses;
        statistics::Formula instAccesses;
        statistics::Formula hits;
        statistics::Formula misses;
        statistics::Formula accesses;
    } stats;
 
    probing::PMUUPtr ppRefills;
 
    int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
    vmid_t vmid;
 
  public:
    using Params = ArmTLBParams;
    using Lookup = TlbEntry::Lookup;
    using LookupLevel = enums::ArmLookupLevel;
 
    TLB(const Params &p);
    TLB(const Params &p, int _size, TableWalker *_walker);
 
    TlbEntry *lookup(const Lookup &lookup_data);
 
    TlbEntry *multiLookup(const Lookup &lookup_data);
 
    virtual ~TLB();
 
    void takeOverFrom(BaseTLB *otlb) override;
 
    void setTableWalker(TableWalker *table_walker);
 
    TableWalker *getTableWalker() { return tableWalker; }
 
    int getsize() const { return size; }
 
    bool walkCache() const { return _walkCache; }
 
    void setVMID(vmid_t _vmid) { vmid = _vmid; }
 
    void insert(TlbEntry &pte);
 
    void multiInsert(TlbEntry &pte);
 
    void flushAll() override;
 
 
    void flush(const TLBIALL &tlbi_op);
    void flush(const ITLBIALL &tlbi_op);
    void flush(const DTLBIALL &tlbi_op);
 
    void flush(const TLBIALLEL &tlbi_op);
 
    void flush(const TLBIVMALL &tlbi_op);
 
    void flush(const TLBIALLN &tlbi_op);
 
    void flush(const TLBIMVA &tlbi_op);
    void flush(const ITLBIMVA &tlbi_op);
    void flush(const DTLBIMVA &tlbi_op);
 
    void flush(const TLBIASID &tlbi_op);
    void flush(const ITLBIASID &tlbi_op);
    void flush(const DTLBIASID &tlbi_op);
 
    void flush(const TLBIMVAA &tlbi_op);
 
    Fault trickBoxCheck(const RequestPtr &req, BaseMMU::Mode mode,
                        TlbEntry::DomainType domain);
 
    Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz,
                            bool is_exec, bool is_write,
                            TlbEntry::DomainType domain,
                            LookupLevel lookup_level);
 
    void printTlb() const;
 
    void demapPage(Addr vaddr, uint64_t asn) override
    {
        // needed for x86 only
        panic("demapPage() is not implemented.\n");
    }
 
    Fault
    translateAtomic(const RequestPtr &req, ThreadContext *tc,
                    BaseMMU::Mode mode) override
    {
        panic("unimplemented");
    }
 
    void
    translateTiming(const RequestPtr &req, ThreadContext *tc,
                    BaseMMU::Translation *translation,
                    BaseMMU::Mode mode) override
    {
        panic("unimplemented");
    }
 
    Fault
    finalizePhysical(const RequestPtr &req, ThreadContext *tc,
                     BaseMMU::Mode mode) const override
    {
        panic("unimplemented");
    }
 
    void regProbePoints() override;
 
    Port *getTableWalkerPort() override;
 
    // Caching misc register values here.
    // Writing to misc registers needs to invalidate them.
    // translateFunctional/translateSe/translateFs checks if they are
    // invalid and call updateMiscReg if necessary.
 
  private:
    void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
                   bool ignore_asn, ExceptionLevel target_el,
                   bool in_host, TypeTLB entry_type);
 
    void checkPromotion(TlbEntry *entry, BaseMMU::Mode mode);
 
    TlbEntry *match(const Lookup &lookup_data);
};
 
} // namespace ArmISA
} // namespace gem5
 
#endif // __ARCH_ARM_TLB_HH__