gem5  v22.0.0.0
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int.hh File Reference
#include "cpu/reg_class.hh"

Go to the source code of this file.

Namespaces

 gem5
 Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
 
 gem5::PowerISA
 
 gem5::PowerISA::int_reg
 

Enumerations

enum  : RegIndex {
  gem5::PowerISA::int_reg::_R0Idx, gem5::PowerISA::int_reg::_R1Idx, gem5::PowerISA::int_reg::_R2Idx, gem5::PowerISA::int_reg::_R3Idx,
  gem5::PowerISA::int_reg::_R4Idx, gem5::PowerISA::int_reg::_R5Idx, gem5::PowerISA::int_reg::_R6Idx, gem5::PowerISA::int_reg::_R7Idx,
  gem5::PowerISA::int_reg::_R8Idx, gem5::PowerISA::int_reg::_R9Idx, gem5::PowerISA::int_reg::_R10Idx, gem5::PowerISA::int_reg::_R11Idx,
  gem5::PowerISA::int_reg::_R12Idx, gem5::PowerISA::int_reg::_R13Idx, gem5::PowerISA::int_reg::_R14Idx, gem5::PowerISA::int_reg::_R15Idx,
  gem5::PowerISA::int_reg::_R16Idx, gem5::PowerISA::int_reg::_R17Idx, gem5::PowerISA::int_reg::_R18Idx, gem5::PowerISA::int_reg::_R19Idx,
  gem5::PowerISA::int_reg::_R20Idx, gem5::PowerISA::int_reg::_R21Idx, gem5::PowerISA::int_reg::_R22Idx, gem5::PowerISA::int_reg::_R23Idx,
  gem5::PowerISA::int_reg::_R24Idx, gem5::PowerISA::int_reg::_R25Idx, gem5::PowerISA::int_reg::_R26Idx, gem5::PowerISA::int_reg::_R27Idx,
  gem5::PowerISA::int_reg::_R28Idx, gem5::PowerISA::int_reg::_R29Idx, gem5::PowerISA::int_reg::_R30Idx, gem5::PowerISA::int_reg::_R31Idx,
  gem5::PowerISA::int_reg::NumArchRegs, gem5::PowerISA::int_reg::_CrIdx = NumArchRegs, gem5::PowerISA::int_reg::_XerIdx, gem5::PowerISA::int_reg::_LrIdx,
  gem5::PowerISA::int_reg::_CtrIdx, gem5::PowerISA::int_reg::_TarIdx, gem5::PowerISA::int_reg::_FpscrIdx, gem5::PowerISA::int_reg::_MsrIdx,
  gem5::PowerISA::int_reg::_RsvIdx, gem5::PowerISA::int_reg::_RsvLenIdx, gem5::PowerISA::int_reg::_RsvAddrIdx, gem5::PowerISA::int_reg::NumRegs
}
 

Functions

constexpr RegId gem5::PowerISA::int_reg::R0 (IntRegClass, _R0Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R1 (IntRegClass, _R1Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R2 (IntRegClass, _R2Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R3 (IntRegClass, _R3Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R4 (IntRegClass, _R4Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R5 (IntRegClass, _R5Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R6 (IntRegClass, _R6Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R7 (IntRegClass, _R7Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R8 (IntRegClass, _R8Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R9 (IntRegClass, _R9Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R10 (IntRegClass, _R10Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R11 (IntRegClass, _R11Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R12 (IntRegClass, _R12Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R13 (IntRegClass, _R13Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R14 (IntRegClass, _R14Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R15 (IntRegClass, _R15Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R16 (IntRegClass, _R16Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R17 (IntRegClass, _R17Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R18 (IntRegClass, _R18Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R19 (IntRegClass, _R19Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R20 (IntRegClass, _R20Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R21 (IntRegClass, _R21Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R22 (IntRegClass, _R22Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R23 (IntRegClass, _R23Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R24 (IntRegClass, _R24Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R25 (IntRegClass, _R25Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R26 (IntRegClass, _R26Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R27 (IntRegClass, _R27Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R28 (IntRegClass, _R28Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R29 (IntRegClass, _R29Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R30 (IntRegClass, _R30Idx)
 
constexpr RegId gem5::PowerISA::int_reg::R31 (IntRegClass, _R31Idx)
 
constexpr RegId gem5::PowerISA::int_reg::Cr (IntRegClass, _CrIdx)
 
constexpr RegId gem5::PowerISA::int_reg::Xer (IntRegClass, _XerIdx)
 
constexpr RegId gem5::PowerISA::int_reg::Lr (IntRegClass, _LrIdx)
 
constexpr RegId gem5::PowerISA::int_reg::Ctr (IntRegClass, _CtrIdx)
 
constexpr RegId gem5::PowerISA::int_reg::Tar (IntRegClass, _TarIdx)
 
constexpr RegId gem5::PowerISA::int_reg::Fpscr (IntRegClass, _FpscrIdx)
 
constexpr RegId gem5::PowerISA::int_reg::Msr (IntRegClass, _MsrIdx)
 
constexpr RegId gem5::PowerISA::int_reg::Rsv (IntRegClass, _RsvIdx)
 
constexpr RegId gem5::PowerISA::int_reg::RsvLen (IntRegClass, _RsvLenIdx)
 
constexpr RegId gem5::PowerISA::int_reg::RsvAddr (IntRegClass, _RsvAddrIdx)
 

Variables

constexpr auto & gem5::PowerISA::ReturnValueReg = int_reg::R3
 
constexpr auto & gem5::PowerISA::ArgumentReg0 = int_reg::R3
 
constexpr auto & gem5::PowerISA::ArgumentReg1 = int_reg::R4
 
constexpr auto & gem5::PowerISA::ArgumentReg2 = int_reg::R5
 
constexpr auto & gem5::PowerISA::ArgumentReg3 = int_reg::R6
 
constexpr auto & gem5::PowerISA::ArgumentReg4 = int_reg::R7
 
constexpr auto & gem5::PowerISA::ArgumentReg5 = int_reg::R8
 
constexpr auto & gem5::PowerISA::StackPointerReg = int_reg::R1
 
constexpr auto & gem5::PowerISA::TOCPointerReg = int_reg::R2
 
constexpr auto & gem5::PowerISA::ThreadPointerReg = int_reg::R13
 
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