reg_class.hh

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#ifndef __CPU__REG_CLASS_HH__
#define __CPU__REG_CLASS_HH__
 
#include <cstddef>
#include <string>
 
#include "base/cprintf.hh"
#include "base/debug.hh"
#include "base/intmath.hh"
#include "base/types.hh"
 
namespace gem5
{
 
enum RegClassType
{
    IntRegClass,        
    FloatRegClass,      
 
    VecRegClass,
    VecElemClass,
    VecPredRegClass,
    CCRegClass,         
    MiscRegClass,       
    InvalidRegClass = -1
};
 
class RegId;
 
class RegClassOps
{
  public:
    virtual std::string regName(const RegId &id) const;
    virtual std::string valString(const void *val, size_t size) const;
};
 
class RegClass
{
  private:
    size_t _numRegs;
    size_t _regBytes;
    // This is how much to shift an index by to get an offset of a register in
    // a register file from the register index, which would otherwise need to
    // be calculated with a multiply.
    size_t _regShift;
 
    static inline RegClassOps defaultOps;
    RegClassOps *_ops = &defaultOps;
    const debug::Flag &debugFlag;
 
  public:
    constexpr RegClass(size_t num_regs, const debug::Flag &debug_flag,
            size_t reg_bytes=sizeof(RegVal)) :
        _numRegs(num_regs), _regBytes(reg_bytes),
        _regShift(ceilLog2(reg_bytes)), debugFlag(debug_flag)
    {}
    constexpr RegClass(size_t num_regs, RegClassOps &new_ops,
            const debug::Flag &debug_flag, size_t reg_bytes=sizeof(RegVal)) :
        RegClass(num_regs, debug_flag, reg_bytes)
    {
        _ops = &new_ops;
    }
 
    constexpr size_t numRegs() const { return _numRegs; }
    constexpr size_t regBytes() const { return _regBytes; }
    constexpr size_t regShift() const { return _regShift; }
    constexpr const debug::Flag &debug() const { return debugFlag; }
 
    std::string regName(const RegId &id) const { return _ops->regName(id); }
    std::string
    valString(const void *val) const
    {
        return _ops->valString(val, regBytes());
    }
};
 
class RegId
{
  protected:
    static const char* regClassStrings[];
    RegClassType regClass;
    RegIndex regIdx;
    int numPinnedWrites;
 
    friend struct std::hash<RegId>;
 
  public:
    constexpr RegId() : RegId(InvalidRegClass, 0) {}
 
    constexpr RegId(RegClassType reg_class, RegIndex reg_idx)
        : regClass(reg_class), regIdx(reg_idx), numPinnedWrites(0)
    {}
 
    constexpr operator RegIndex() const
    {
        return index();
    }
 
    constexpr bool
    operator==(const RegId& that) const
    {
        return regClass == that.classValue() && regIdx == that.index();
    }
 
    constexpr bool
    operator!=(const RegId& that) const
    {
        return !(*this==that);
    }
 
    constexpr bool
    operator<(const RegId& that) const
    {
        return regClass < that.classValue() ||
            (regClass == that.classValue() && (regIdx < that.index()));
    }
 
    constexpr bool
    isRenameable() const
    {
        return regClass != MiscRegClass && regClass != InvalidRegClass;
    }
 
    constexpr bool
    is(RegClassType reg_class) const
    {
        return regClass == reg_class;
    }
 
    constexpr RegIndex index() const { return regIdx; }
 
    constexpr RegClassType classValue() const { return regClass; }
    constexpr const char*
    className() const
    {
        return regClassStrings[regClass];
    }
 
    int getNumPinnedWrites() const { return numPinnedWrites; }
    void setNumPinnedWrites(int num_writes) { numPinnedWrites = num_writes; }
 
    friend std::ostream&
    operator<<(std::ostream& os, const RegId& rid)
    {
        return os << rid.className() << "{" << rid.index() << "}";
    }
};
 
template <typename ValueType>
class TypedRegClassOps : public RegClassOps
{
  public:
    std::string
    valString(const void *val, size_t size) const override
    {
        assert(size == sizeof(ValueType));
        return csprintf("%s", *(const ValueType *)val);
    }
};
 
template <typename ValueType>
class VecElemRegClassOps : public TypedRegClassOps<ValueType>
{
  protected:
    size_t elemsPerVec;
 
  public:
    explicit VecElemRegClassOps(size_t elems_per_vec) :
        elemsPerVec(elems_per_vec)
    {}
 
    std::string
    regName(const RegId &id) const override
    {
        RegIndex reg_idx = id.index() / elemsPerVec;
        RegIndex elem_idx = id.index() % elemsPerVec;
        return csprintf("v%d[%d]", reg_idx, elem_idx);
    }
};
 
class PhysRegId : private RegId
{
  private:
    RegIndex flatIdx;
    int numPinnedWritesToComplete;
    bool pinned;
 
  public:
    explicit PhysRegId() : RegId(InvalidRegClass, -1), flatIdx(-1),
                           numPinnedWritesToComplete(0)
    {}
 
    explicit PhysRegId(RegClassType _regClass, RegIndex _regIdx,
              RegIndex _flatIdx)
        : RegId(_regClass, _regIdx), flatIdx(_flatIdx),
          numPinnedWritesToComplete(0), pinned(false)
    {}
 
    using RegId::index;
    using RegId::classValue;
    using RegId::className;
    using RegId::is;
    bool
    operator<(const PhysRegId& that) const
    {
        return RegId::operator<(that);
    }
 
    bool
    operator==(const PhysRegId& that) const
    {
        return RegId::operator==(that);
    }
 
    bool
    operator!=(const PhysRegId& that) const
    {
        return RegId::operator!=(that);
    }
    bool isFixedMapping() const { return !isRenameable(); }
 
    const RegIndex& flatIndex() const { return flatIdx; }
 
    int getNumPinnedWrites() const { return numPinnedWrites; }
 
    void
    setNumPinnedWrites(int numWrites)
    {
        // An instruction with a pinned destination reg can get
        // squashed. The numPinnedWrites counter may be zero when
        // the squash happens but we need to know if the dest reg
        // was pinned originally in order to reset counters properly
        // for a possible re-rename using the same physical reg (which
        // may be required in case of a mem access order violation).
        pinned = (numWrites != 0);
        numPinnedWrites = numWrites;
    }
 
    void decrNumPinnedWrites() { --numPinnedWrites; }
    void incrNumPinnedWrites() { ++numPinnedWrites; }
 
    bool isPinned() const { return pinned; }
 
    int
    getNumPinnedWritesToComplete() const
    {
        return numPinnedWritesToComplete;
    }
 
    void
    setNumPinnedWritesToComplete(int numWrites)
    {
        numPinnedWritesToComplete = numWrites;
    }
 
    void decrNumPinnedWritesToComplete() { --numPinnedWritesToComplete; }
    void incrNumPinnedWritesToComplete() { ++numPinnedWritesToComplete; }
};
 
using PhysRegIdPtr = PhysRegId*;
 
} // namespace gem5
 
namespace std
{
template<>
struct hash<gem5::RegId>
{
    size_t
    operator()(const gem5::RegId& reg_id) const
    {
        // Extract unique integral values for the effective fields of a RegId.
        const size_t index = static_cast<size_t>(reg_id.index());
        const size_t class_num = static_cast<size_t>(reg_id.regClass);
 
        const size_t shifted_class_num =
            class_num << (sizeof(gem5::RegIndex) << 3);
 
        // Concatenate the class_num to the end of the flat_index, in order to
        // maximize information retained.
        const size_t concatenated_hash = index | shifted_class_num;
 
        // If RegIndex is larger than size_t, then class_num will not be
        // considered by this hash function, so we may wish to perform a
        // different operation to include that information in the hash.
        static_assert(sizeof(gem5::RegIndex) < sizeof(size_t),
            "sizeof(RegIndex) should be less than sizeof(size_t)");
 
        return concatenated_hash;
    }
};
} // namespace std
 
#endif // __CPU__REG_CLASS_HH__