isa.cc File Reference

#include "arch/riscv/isa.hh"
#include <ctime>
#include <set>
#include <sstream>
#include "arch/riscv/interrupts.hh"
#include "arch/riscv/mmu.hh"
#include "arch/riscv/pagetable.hh"
#include "arch/riscv/pmp.hh"
#include "arch/riscv/regs/float.hh"
#include "arch/riscv/regs/int.hh"
#include "arch/riscv/regs/misc.hh"
#include "base/bitfield.hh"
#include "base/compiler.hh"
#include "base/logging.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "debug/Checkpoint.hh"
#include "debug/FloatRegs.hh"
#include "debug/IntRegs.hh"
#include "debug/LLSC.hh"
#include "debug/MiscRegs.hh"
#include "debug/RiscvMisc.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "params/RiscvISA.hh"
#include "sim/pseudo_inst.hh"

Go to the source code of this file.

Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
	gem5::RiscvISA

Functions
std::ostream &	operator<< (std::ostream &os, gem5::RiscvISA::PrivilegeMode pm)

Variables
const std::array< const char *, NUM_MISCREGS >	gem5::RiscvISA::MiscRegNames
const int	gem5::RiscvISA::WARN_FAILURE = 10000
const Addr	gem5::RiscvISA::INVALID_RESERVATION_ADDR = (Addr) -1
std::unordered_map< int, Addr >	gem5::RiscvISA::load_reservation_addrs

Function Documentation

operator<<()

std::ostream& operator<<	(	std::ostream &	os,
		gem5::RiscvISA::PrivilegeMode	pm
	)

Definition at line 585 of file isa.cc.

References gem5::X86ISA::os, gem5::RiscvISA::PRV_M, gem5::RiscvISA::PRV_S, and gem5::RiscvISA::PRV_U.