comm.hh

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/*
 * Copyright (c) 2011, 2016-2017 ARM Limited
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2004-2006 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 */
 
#ifndef __CPU_O3_COMM_HH__
#define __CPU_O3_COMM_HH__
 
#include <vector>
 
#include "arch/generic/pcstate.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/o3/limits.hh"
#include "sim/faults.hh"
 
namespace gem5
{
 
namespace o3
{
 
struct FetchStruct
{
    int size;
 
    DynInstPtr insts[MaxWidth];
    Fault fetchFault;
    InstSeqNum fetchFaultSN;
    bool clearFetchFault;
};
 
struct DecodeStruct
{
    int size;
 
    DynInstPtr insts[MaxWidth];
};
 
struct RenameStruct
{
    int size;
 
    DynInstPtr insts[MaxWidth];
};
 
struct IEWStruct
{
    int size;
 
    DynInstPtr insts[MaxWidth];
    DynInstPtr mispredictInst[MaxThreads];
    Addr mispredPC[MaxThreads];
    InstSeqNum squashedSeqNum[MaxThreads];
    std::unique_ptr<PCStateBase> pc[MaxThreads];
 
    bool squash[MaxThreads];
    bool branchMispredict[MaxThreads];
    bool branchTaken[MaxThreads];
    bool includeSquashInst[MaxThreads];
};
 
struct IssueStruct
{
    int size;
 
    DynInstPtr insts[MaxWidth];
};
 
struct TimeStruct
{
    struct DecodeComm
    {
        std::unique_ptr<PCStateBase> nextPC;
        DynInstPtr mispredictInst;
        DynInstPtr squashInst;
        InstSeqNum doneSeqNum;
        Addr mispredPC;
        uint64_t branchAddr;
        unsigned branchCount;
        bool squash;
        bool predIncorrect;
        bool branchMispredict;
        bool branchTaken;
    };
 
    DecodeComm decodeInfo[MaxThreads];
 
    struct RenameComm {};
 
    RenameComm renameInfo[MaxThreads];
 
    struct IewComm
    {
        // Also eventually include skid buffer space.
        unsigned freeIQEntries;
        unsigned freeLQEntries;
        unsigned freeSQEntries;
        unsigned dispatchedToLQ;
        unsigned dispatchedToSQ;
 
        unsigned iqCount;
        unsigned ldstqCount;
 
        unsigned dispatched;
        bool usedIQ;
        bool usedLSQ;
    };
 
    IewComm iewInfo[MaxThreads];
 
    struct CommitComm
    {
        // This code has been re-structured for better packing of variables
        // instead of by stage which is the more logical way to arrange the
        // data.
        // F = Fetch
        // D = Decode
        // I = IEW
        // R = Rename
        // As such each member is annotated with who consumes it
        // e.g. bool variable name // *F,R for Fetch and Rename
 
        std::unique_ptr<PCStateBase> pc; // *F
 
        DynInstPtr mispredictInst;  // *F
 
        DynInstPtr squashInst; // *F
 
        DynInstPtr strictlyOrderedLoad; // *I
 
        InstSeqNum nonSpecSeqNum; // *I
 
        InstSeqNum doneSeqNum; // *F, I
 
        unsigned freeROBEntries; // *R
 
        bool squash; // *F, D, R, I
        bool robSquashing; // *F, D, R, I
 
        bool usedROB; // *R
 
        bool emptyROB; // *R
 
        bool branchTaken; // *F
        bool interruptPending; // *F
        bool clearInterrupt; // *F
 
        bool strictlyOrdered; // *I
 
    };
 
    CommitComm commitInfo[MaxThreads];
 
    bool decodeBlock[MaxThreads];
    bool decodeUnblock[MaxThreads];
    bool renameBlock[MaxThreads];
    bool renameUnblock[MaxThreads];
    bool iewBlock[MaxThreads];
    bool iewUnblock[MaxThreads];
};
 
} // namespace o3
} // namespace gem5
 
#endif //__CPU_O3_COMM_HH__